1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/sound/nvidia,tegra210-admaif.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Tegra210 ADMAIF Device Tree Bindings
8
9description: |
10  ADMAIF is the interface between ADMA and AHUB. Each ADMA channel
11  that sends/receives data to/from AHUB must interface through an
12  ADMAIF channel. ADMA channel sending data to AHUB pairs with ADMAIF
13  Tx channel and ADMA channel receiving data from AHUB pairs with
14  ADMAIF Rx channel.
15
16maintainers:
17  - Jon Hunter <jonathanh@nvidia.com>
18  - Sameer Pujar <spujar@nvidia.com>
19
20properties:
21  $nodename:
22    pattern: "^admaif@[0-9a-f]*$"
23
24  compatible:
25    oneOf:
26      - enum:
27          - nvidia,tegra210-admaif
28          - nvidia,tegra186-admaif
29      - items:
30          - const: nvidia,tegra194-admaif
31          - const: nvidia,tegra186-admaif
32
33  reg:
34    maxItems: 1
35
36  dmas: true
37
38  dma-names: true
39
40  ports:
41    $ref: /schemas/graph.yaml#/properties/ports
42    description: |
43      Contains list of ACIF (Audio CIF) port nodes for ADMAIF channels.
44      The number of port nodes depends on the number of ADMAIF channels
45      that SoC may have. These are interfaced with respective ACIF ports
46      in AHUB (Audio Hub). Each port is capable of data transfers in
47      both directions.
48
49    patternProperties:
50      '^port@[0-9]':
51        $ref: audio-graph-port.yaml#
52        unevaluatedProperties: false
53
54if:
55  properties:
56    compatible:
57      contains:
58        const: nvidia,tegra210-admaif
59
60then:
61  properties:
62    dmas:
63      description:
64        DMA channel specifiers, equally divided for Tx and Rx.
65      minItems: 1
66      maxItems: 20
67    dma-names:
68      items:
69        pattern: "^[rt]x(10|[1-9])$"
70      description:
71        Should be "rx1", "rx2" ... "rx10" for DMA Rx channel
72        Should be "tx1", "tx2" ... "tx10" for DMA Tx channel
73      minItems: 1
74      maxItems: 20
75
76else:
77  properties:
78    dmas:
79      description:
80        DMA channel specifiers, equally divided for Tx and Rx.
81      minItems: 1
82      maxItems: 40
83    dma-names:
84      items:
85        pattern: "^[rt]x(1[0-9]|[1-9]|20)$"
86      description:
87        Should be "rx1", "rx2" ... "rx20" for DMA Rx channel
88        Should be "tx1", "tx2" ... "tx20" for DMA Tx channel
89      minItems: 1
90      maxItems: 40
91
92required:
93  - compatible
94  - reg
95  - dmas
96  - dma-names
97
98additionalProperties: false
99
100examples:
101  - |
102    admaif@702d0000 {
103        compatible = "nvidia,tegra210-admaif";
104        reg = <0x702d0000 0x800>;
105        dmas = <&adma 1>,  <&adma 1>,
106               <&adma 2>,  <&adma 2>,
107               <&adma 3>,  <&adma 3>,
108               <&adma 4>,  <&adma 4>,
109               <&adma 5>,  <&adma 5>,
110               <&adma 6>,  <&adma 6>,
111               <&adma 7>,  <&adma 7>,
112               <&adma 8>,  <&adma 8>,
113               <&adma 9>,  <&adma 9>,
114               <&adma 10>, <&adma 10>;
115        dma-names = "rx1",  "tx1",
116                    "rx2",  "tx2",
117                    "rx3",  "tx3",
118                    "rx4",  "tx4",
119                    "rx5",  "tx5",
120                    "rx6",  "tx6",
121                    "rx7",  "tx7",
122                    "rx8",  "tx8",
123                    "rx9",  "tx9",
124                    "rx10", "tx10";
125    };
126
127...
128