1*aa1a8ff2SEmmanuel Vadot# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*aa1a8ff2SEmmanuel Vadot%YAML 1.2 3*aa1a8ff2SEmmanuel Vadot--- 4*aa1a8ff2SEmmanuel Vadot$id: http://devicetree.org/schemas/spi/nvidia,tegra20-sflash.yaml# 5*aa1a8ff2SEmmanuel Vadot$schema: http://devicetree.org/meta-schemas/core.yaml# 6*aa1a8ff2SEmmanuel Vadot 7*aa1a8ff2SEmmanuel Vadottitle: NVIDIA Tegra20 SFLASH controller 8*aa1a8ff2SEmmanuel Vadot 9*aa1a8ff2SEmmanuel Vadotmaintainers: 10*aa1a8ff2SEmmanuel Vadot - Thierry Reding <thierry.reding@gmail.com> 11*aa1a8ff2SEmmanuel Vadot - Jon Hunter <jonathanh@nvidia.com> 12*aa1a8ff2SEmmanuel Vadot 13*aa1a8ff2SEmmanuel Vadotproperties: 14*aa1a8ff2SEmmanuel Vadot compatible: 15*aa1a8ff2SEmmanuel Vadot const: nvidia,tegra20-sflash 16*aa1a8ff2SEmmanuel Vadot 17*aa1a8ff2SEmmanuel Vadot reg: 18*aa1a8ff2SEmmanuel Vadot maxItems: 1 19*aa1a8ff2SEmmanuel Vadot 20*aa1a8ff2SEmmanuel Vadot interrupts: 21*aa1a8ff2SEmmanuel Vadot maxItems: 1 22*aa1a8ff2SEmmanuel Vadot 23*aa1a8ff2SEmmanuel Vadot clocks: 24*aa1a8ff2SEmmanuel Vadot items: 25*aa1a8ff2SEmmanuel Vadot - description: module clock 26*aa1a8ff2SEmmanuel Vadot 27*aa1a8ff2SEmmanuel Vadot resets: 28*aa1a8ff2SEmmanuel Vadot items: 29*aa1a8ff2SEmmanuel Vadot - description: module reset 30*aa1a8ff2SEmmanuel Vadot 31*aa1a8ff2SEmmanuel Vadot reset-names: 32*aa1a8ff2SEmmanuel Vadot items: 33*aa1a8ff2SEmmanuel Vadot - const: spi 34*aa1a8ff2SEmmanuel Vadot 35*aa1a8ff2SEmmanuel Vadot dmas: 36*aa1a8ff2SEmmanuel Vadot items: 37*aa1a8ff2SEmmanuel Vadot - description: DMA channel used for reception 38*aa1a8ff2SEmmanuel Vadot - description: DMA channel used for transmission 39*aa1a8ff2SEmmanuel Vadot 40*aa1a8ff2SEmmanuel Vadot dma-names: 41*aa1a8ff2SEmmanuel Vadot items: 42*aa1a8ff2SEmmanuel Vadot - const: rx 43*aa1a8ff2SEmmanuel Vadot - const: tx 44*aa1a8ff2SEmmanuel Vadot 45*aa1a8ff2SEmmanuel Vadot spi-max-frequency: 46*aa1a8ff2SEmmanuel Vadot description: Maximum SPI clocking speed of the controller in Hz. 47*aa1a8ff2SEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/uint32 48*aa1a8ff2SEmmanuel Vadot 49*aa1a8ff2SEmmanuel VadotallOf: 50*aa1a8ff2SEmmanuel Vadot - $ref: spi-controller.yaml 51*aa1a8ff2SEmmanuel Vadot 52*aa1a8ff2SEmmanuel VadotunevaluatedProperties: false 53*aa1a8ff2SEmmanuel Vadot 54*aa1a8ff2SEmmanuel Vadotrequired: 55*aa1a8ff2SEmmanuel Vadot - compatible 56*aa1a8ff2SEmmanuel Vadot - reg 57*aa1a8ff2SEmmanuel Vadot - interrupts 58*aa1a8ff2SEmmanuel Vadot - clocks 59*aa1a8ff2SEmmanuel Vadot - resets 60*aa1a8ff2SEmmanuel Vadot - reset-names 61*aa1a8ff2SEmmanuel Vadot - dmas 62*aa1a8ff2SEmmanuel Vadot - dma-names 63*aa1a8ff2SEmmanuel Vadot 64*aa1a8ff2SEmmanuel Vadotexamples: 65*aa1a8ff2SEmmanuel Vadot - | 66*aa1a8ff2SEmmanuel Vadot #include <dt-bindings/clock/tegra20-car.h> 67*aa1a8ff2SEmmanuel Vadot #include <dt-bindings/interrupt-controller/arm-gic.h> 68*aa1a8ff2SEmmanuel Vadot 69*aa1a8ff2SEmmanuel Vadot spi@7000c380 { 70*aa1a8ff2SEmmanuel Vadot compatible = "nvidia,tegra20-sflash"; 71*aa1a8ff2SEmmanuel Vadot reg = <0x7000c380 0x80>; 72*aa1a8ff2SEmmanuel Vadot interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 73*aa1a8ff2SEmmanuel Vadot spi-max-frequency = <25000000>; 74*aa1a8ff2SEmmanuel Vadot #address-cells = <1>; 75*aa1a8ff2SEmmanuel Vadot #size-cells = <0>; 76*aa1a8ff2SEmmanuel Vadot clocks = <&tegra_car TEGRA20_CLK_SPI>; 77*aa1a8ff2SEmmanuel Vadot resets = <&tegra_car 43>; 78*aa1a8ff2SEmmanuel Vadot reset-names = "spi"; 79*aa1a8ff2SEmmanuel Vadot dmas = <&apbdma 11>, <&apbdma 11>; 80*aa1a8ff2SEmmanuel Vadot dma-names = "rx", "tx"; 81*aa1a8ff2SEmmanuel Vadot }; 82