1GENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
2
3The QUP v3 core is a GENI based AHB slave that provides a common data path
4(an output FIFO and an input FIFO) for serial peripheral interface (SPI)
5mini-core.
6
7SPI in master mode supports up to 50MHz, up to four chip selects, programmable
8data path from 4 bits to 32 bits and numerous protocol variants.
9
10Required properties:
11- compatible:		Must contain "qcom,geni-spi".
12- reg:			Must contain SPI register location and length.
13- interrupts:		Must contain SPI controller interrupts.
14- clock-names:		Must contain "se".
15- clocks:		Serial engine core clock needed by the device.
16- #address-cells:	Must be <1> to define a chip select address on
17			the SPI bus.
18- #size-cells:		Must be <0>.
19
20SPI Controller nodes must be child of GENI based Qualcomm Universal
21Peripharal. Please refer GENI based QUP wrapper controller node bindings
22described in Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml.
23
24SPI slave nodes must be children of the SPI master node and conform to SPI bus
25binding as described in Documentation/devicetree/bindings/spi/spi-bus.txt.
26
27Example:
28	spi0: spi@a84000 {
29		compatible = "qcom,geni-spi";
30		reg = <0xa84000 0x4000>;
31		interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
32		clock-names = "se";
33		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>;
34		pinctrl-names = "default", "sleep";
35		pinctrl-0 = <&qup_1_spi_2_active>;
36		pinctrl-1 = <&qup_1_spi_2_sleep>;
37		#address-cells = <1>;
38		#size-cells = <0>;
39	};
40