1Qualcomm SPMI Controller (PMIC Arbiter)
2
3The SPMI PMIC Arbiter is found on Snapdragon chipsets.  It is an SPMI
4controller with wrapping arbitration logic to allow for multiple on-chip
5devices to control a single SPMI master.
6
7The PMIC Arbiter can also act as an interrupt controller, providing interrupts
8to slave devices.
9
10See Documentation/devicetree/bindings/spmi/spmi.yaml for the generic SPMI
11controller binding requirements for child nodes.
12
13See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for
14generic interrupt controller binding documentation.
15
16Required properties:
17- compatible : should be "qcom,spmi-pmic-arb".
18- reg-names  : must contain:
19     "core" - core registers
20     "intr" - interrupt controller registers
21     "cnfg" - configuration registers
22   Registers used only for V2 PMIC Arbiter:
23     "chnls"  - tx-channel per virtual slave registers.
24     "obsrvr" - rx-channel (called observer) per virtual slave registers.
25
26- reg : address + size pairs describing the PMIC arb register sets; order must
27        correspond with the order of entries in reg-names
28- #address-cells : must be set to 2
29- #size-cells : must be set to 0
30- qcom,ee : indicates the active Execution Environment identifier (0-5)
31- qcom,channel : which of the PMIC Arb provided channels to use for accesses (0-5)
32- interrupts : interrupt list for the PMIC Arb controller, must contain a
33               single interrupt entry for the peripheral interrupt
34- interrupt-names : corresponding interrupt names for the interrupts
35                    listed in the 'interrupts' property, must contain:
36     "periph_irq" - summary interrupt for PMIC peripherals
37- interrupt-controller : boolean indicator that the PMIC arbiter is an interrupt controller
38- #interrupt-cells :  must be set to 4. Interrupts are specified as a 4-tuple:
39    cell 1: slave ID for the requested interrupt (0-15)
40    cell 2: peripheral ID for requested interrupt (0-255)
41    cell 3: the requested peripheral interrupt (0-7)
42    cell 4: interrupt flags indicating level-sense information, as defined in
43            dt-bindings/interrupt-controller/irq.h
44
45Example:
46
47	spmi {
48		compatible = "qcom,spmi-pmic-arb";
49		reg-names = "core", "intr", "cnfg";
50		reg = <0xfc4cf000 0x1000>,
51		      <0xfc4cb000 0x1000>,
52		      <0xfc4ca000 0x1000>;
53
54		interrupt-names = "periph_irq";
55		interrupts = <0 190 0>;
56
57		qcom,ee = <0>;
58		qcom,channel = <0>;
59
60		#address-cells = <2>;
61		#size-cells = <0>;
62
63		interrupt-controller;
64		#interrupt-cells = <4>;
65	};
66