1NVIDIA Tegra20 timer
2
3The Tegra20 timer provides four 29-bit timer channels and a single 32-bit free
4running counter. The first two channels may also trigger a watchdog reset.
5
6Required properties:
7
8- compatible : should be "nvidia,tegra20-timer".
9- reg : Specifies base physical address and size of the registers.
10- interrupts : A list of 4 interrupts; one per timer channel.
11- clocks : Must contain one entry, for the module clock.
12  See ../clocks/clock-bindings.txt for details.
13
14Example:
15
16timer {
17	compatible = "nvidia,tegra20-timer";
18	reg = <0x60005000 0x60>;
19	interrupts = <0 0 0x04
20			0 1 0x04
21			0 41 0x04
22			0 42 0x04>;
23	clocks = <&tegra_car 132>;
24};
25