1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Universal Flash Storage (UFS) Controller
8
9maintainers:
10  - Bjorn Andersson <bjorn.andersson@linaro.org>
11  - Andy Gross <agross@kernel.org>
12
13# Select only our matches, not all jedec,ufs-2.0
14select:
15  properties:
16    compatible:
17      contains:
18        const: qcom,ufshc
19  required:
20    - compatible
21
22properties:
23  compatible:
24    items:
25      - enum:
26          - qcom,msm8994-ufshc
27          - qcom,msm8996-ufshc
28          - qcom,msm8998-ufshc
29          - qcom,sc8280xp-ufshc
30          - qcom,sdm845-ufshc
31          - qcom,sm6350-ufshc
32          - qcom,sm8150-ufshc
33          - qcom,sm8250-ufshc
34          - qcom,sm8350-ufshc
35          - qcom,sm8450-ufshc
36          - qcom,sm8550-ufshc
37      - const: qcom,ufshc
38      - const: jedec,ufs-2.0
39
40  clocks:
41    minItems: 8
42    maxItems: 11
43
44  clock-names:
45    minItems: 8
46    maxItems: 11
47
48  dma-coherent: true
49
50  interconnects:
51    minItems: 2
52    maxItems: 2
53
54  interconnect-names:
55    items:
56      - const: ufs-ddr
57      - const: cpu-ufs
58
59  iommus:
60    minItems: 1
61    maxItems: 2
62
63  phys:
64    maxItems: 1
65
66  phy-names:
67    items:
68      - const: ufsphy
69
70  power-domains:
71    maxItems: 1
72
73  reg:
74    minItems: 1
75    maxItems: 2
76
77  required-opps:
78    maxItems: 1
79
80  resets:
81    maxItems: 1
82
83  '#reset-cells':
84    const: 1
85
86  reset-names:
87    items:
88      - const: rst
89
90  reset-gpios:
91    maxItems: 1
92    description:
93      GPIO connected to the RESET pin of the UFS memory device.
94
95required:
96  - compatible
97  - reg
98
99allOf:
100  - $ref: ufs-common.yaml
101
102  - if:
103      properties:
104        compatible:
105          contains:
106            enum:
107              - qcom,msm8998-ufshc
108              - qcom,sc8280xp-ufshc
109              - qcom,sm8250-ufshc
110              - qcom,sm8350-ufshc
111              - qcom,sm8450-ufshc
112              - qcom,sm8550-ufshc
113    then:
114      properties:
115        clocks:
116          minItems: 8
117          maxItems: 8
118        clock-names:
119          items:
120            - const: core_clk
121            - const: bus_aggr_clk
122            - const: iface_clk
123            - const: core_clk_unipro
124            - const: ref_clk
125            - const: tx_lane0_sync_clk
126            - const: rx_lane0_sync_clk
127            - const: rx_lane1_sync_clk
128        reg:
129          minItems: 1
130          maxItems: 1
131
132  - if:
133      properties:
134        compatible:
135          contains:
136            enum:
137              - qcom,sdm845-ufshc
138              - qcom,sm6350-ufshc
139              - qcom,sm8150-ufshc
140    then:
141      properties:
142        clocks:
143          minItems: 9
144          maxItems: 9
145        clock-names:
146          items:
147            - const: core_clk
148            - const: bus_aggr_clk
149            - const: iface_clk
150            - const: core_clk_unipro
151            - const: ref_clk
152            - const: tx_lane0_sync_clk
153            - const: rx_lane0_sync_clk
154            - const: rx_lane1_sync_clk
155            - const: ice_core_clk
156        reg:
157          minItems: 2
158          maxItems: 2
159
160  - if:
161      properties:
162        compatible:
163          contains:
164            enum:
165              - qcom,msm8996-ufshc
166    then:
167      properties:
168        clocks:
169          minItems: 11
170          maxItems: 11
171        clock-names:
172          items:
173            - const: core_clk_src
174            - const: core_clk
175            - const: bus_clk
176            - const: bus_aggr_clk
177            - const: iface_clk
178            - const: core_clk_unipro_src
179            - const: core_clk_unipro
180            - const: core_clk_ice
181            - const: ref_clk
182            - const: tx_lane0_sync_clk
183            - const: rx_lane0_sync_clk
184        reg:
185          minItems: 1
186          maxItems: 1
187
188    # TODO: define clock bindings for qcom,msm8994-ufshc
189
190unevaluatedProperties: false
191
192examples:
193  - |
194    #include <dt-bindings/clock/qcom,gcc-sm8450.h>
195    #include <dt-bindings/clock/qcom,rpmh.h>
196    #include <dt-bindings/gpio/gpio.h>
197    #include <dt-bindings/interconnect/qcom,sm8450.h>
198    #include <dt-bindings/interrupt-controller/arm-gic.h>
199
200    soc {
201        #address-cells = <2>;
202        #size-cells = <2>;
203
204        ufs@1d84000 {
205            compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
206                         "jedec,ufs-2.0";
207            reg = <0 0x01d84000 0 0x3000>;
208            interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
209            phys = <&ufs_mem_phy_lanes>;
210            phy-names = "ufsphy";
211            lanes-per-direction = <2>;
212            #reset-cells = <1>;
213            resets = <&gcc GCC_UFS_PHY_BCR>;
214            reset-names = "rst";
215            reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
216
217            vcc-supply = <&vreg_l7b_2p5>;
218            vcc-max-microamp = <1100000>;
219            vccq-supply = <&vreg_l9b_1p2>;
220            vccq-max-microamp = <1200000>;
221
222            power-domains = <&gcc UFS_PHY_GDSC>;
223            iommus = <&apps_smmu 0xe0 0x0>;
224            interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
225                            <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
226            interconnect-names = "ufs-ddr", "cpu-ufs";
227
228            clock-names = "core_clk",
229                          "bus_aggr_clk",
230                          "iface_clk",
231                          "core_clk_unipro",
232                          "ref_clk",
233                          "tx_lane0_sync_clk",
234                          "rx_lane0_sync_clk",
235                          "rx_lane1_sync_clk";
236            clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
237                     <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
238                     <&gcc GCC_UFS_PHY_AHB_CLK>,
239                     <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
240                     <&rpmhcc RPMH_CXO_CLK>,
241                     <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
242                     <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
243                     <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
244            freq-table-hz = <75000000 300000000>,
245                            <0 0>,
246                            <0 0>,
247                            <75000000 300000000>,
248                            <75000000 300000000>,
249                            <0 0>,
250                            <0 0>,
251                            <0 0>;
252        };
253    };
254