1* USB2 ChipIdea USB controller for ci13xxx
2
3Required properties:
4- compatible: should be one of:
5	"fsl,imx23-usb"
6	"fsl,imx27-usb"
7	"fsl,imx28-usb"
8	"fsl,imx6q-usb"
9	"fsl,imx6sl-usb"
10	"fsl,imx6sx-usb"
11	"fsl,imx6ul-usb"
12	"fsl,imx7d-usb"
13	"fsl,imx7ulp-usb"
14	"fsl,imx8mm-usb"
15	"lsi,zevio-usb"
16	"qcom,ci-hdrc"
17	"chipidea,usb2"
18	"xlnx,zynq-usb-2.20a"
19	"nvidia,tegra20-udc"
20	"nvidia,tegra30-udc"
21	"nvidia,tegra114-udc"
22	"nvidia,tegra124-udc"
23- reg: base address and length of the registers
24- interrupts: interrupt for the USB controller
25
26Recommended properies:
27- phy_type: the type of the phy connected to the core. Should be one
28  of "utmi", "utmi_wide", "ulpi", "serial" or "hsic". Without this
29  property the PORTSC register won't be touched.
30- dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg"
31
32Deprecated properties:
33- usb-phy:      phandle for the PHY device. Use "phys" instead.
34- fsl,usbphy: phandle of usb phy that connects to the port. Use "phys" instead.
35
36Optional properties:
37- clocks: reference to the USB clock
38- phys: reference to the USB PHY
39- phy-names: should be "usb-phy"
40- vbus-supply: reference to the VBUS regulator
41- maximum-speed: limit the maximum connection speed to "full-speed".
42- tpl-support: TPL (Targeted Peripheral List) feature for targeted hosts
43- itc-setting: interrupt threshold control register control, the setting
44  should be aligned with ITC bits at register USBCMD.
45- ahb-burst-config: it is vendor dependent, the required value should be
46  aligned with AHBBRST at SBUSCFG, the range is from 0x0 to 0x7. This
47  property is used to change AHB burst configuration, check the chipidea
48  spec for meaning of each value. If this property is not existed, it
49  will use the reset value.
50- tx-burst-size-dword: it is vendor dependent, the tx burst size in dword
51  (4 bytes), This register represents the maximum length of a the burst
52  in 32-bit words while moving data from system memory to the USB
53  bus, the value of this property will only take effect if property
54  "ahb-burst-config" is set to 0, if this property is missing the reset
55  default of the hardware implementation will be used.
56- rx-burst-size-dword: it is vendor dependent, the rx burst size in dword
57  (4 bytes), This register represents the maximum length of a the burst
58  in 32-bit words while moving data from the USB bus to system memory,
59  the value of this property will only take effect if property
60  "ahb-burst-config" is set to 0, if this property is missing the reset
61  default of the hardware implementation will be used.
62- extcon: phandles to external connector devices. First phandle should point to
63  external connector, which provide "USB" cable events, the second should point
64  to external connector device, which provide "USB-HOST" cable events. If one
65  of the external connector devices is not required, empty <0> phandle should
66  be specified.
67- phy-clkgate-delay-us: the delay time (us) between putting the PHY into
68  low power mode and gating the PHY clock.
69- non-zero-ttctrl-ttha: after setting this property, the value of register
70  ttctrl.ttha will be 0x7f; if not, the value will be 0x0, this is the default
71  value. It needs to be very carefully for setting this property, it is
72  recommended that consult with your IC engineer before setting this value.
73  On the most of chipidea platforms, the "usage_tt" flag at RTL is 0, so this
74  property only affects siTD.
75  If this property is not set, the max packet size is 1023 bytes, and if
76  the total of packet size for pervious transactions are more than 256 bytes,
77  it can't accept any transactions within this frame. The use case is single
78  transaction, but higher frame rate.
79  If this property is set, the max packet size is 188 bytes, it can handle
80  more transactions than above case, it can accept transactions until it
81  considers the left room size within frame is less than 188 bytes, software
82  needs to make sure it does not send more than 90%
83  maximum_periodic_data_per_frame. The use case is multiple transactions, but
84  less frame rate.
85- mux-controls: The mux control for toggling host/device output of this
86  controller. It's expected that a mux state of 0 indicates device mode and a
87  mux state of 1 indicates host mode.
88- mux-control-names: Shall be "usb_switch" if mux-controls is specified.
89- pinctrl-names: Names for optional pin modes in "default", "host", "device".
90  In case of HSIC-mode, "idle" and "active" pin modes are mandatory. In this
91  case, the "idle" state needs to pull down the data and strobe pin
92  and the "active" state needs to pull up the strobe pin.
93- pinctrl-n: alternate pin modes
94
95i.mx specific properties
96- fsl,usbmisc: phandler of non-core register device, with one
97  argument that indicate usb controller index
98- disable-over-current: disable over current detect
99- over-current-active-low: over current signal polarity is active low.
100- over-current-active-high: over current signal polarity is active high.
101  It's recommended to specify the over current polarity.
102- power-active-high: power signal polarity is active high
103- external-vbus-divider: enables off-chip resistor divider for Vbus
104- samsung,picophy-pre-emp-curr-control: HS Transmitter Pre-Emphasis Current
105  Control. This signal controls the amount of current sourced to the
106  USB_OTG*_DP and USB_OTG*_DN pins after a J-to-K or K-to-J transition.
107  The range is from 0x0 to 0x3, the default value is 0x1.
108  Details can refer to TXPREEMPAMPTUNE0 bits of USBNC_n_PHY_CFG1.
109- samsung,picophy-dc-vol-level-adjust: HS DC Voltage Level Adjustment.
110  Adjust the high-speed transmitter DC level voltage.
111  The range is from 0x0 to 0xf, the default value is 0x3.
112  Details can refer to TXVREFTUNE0 bits of USBNC_n_PHY_CFG1.
113
114Example:
115
116	usb@f7ed0000 {
117		compatible = "chipidea,usb2";
118		reg = <0xf7ed0000 0x10000>;
119		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
120		clocks = <&chip CLKID_USB0>;
121		phys = <&usb_phy0>;
122		phy-names = "usb-phy";
123		vbus-supply = <&reg_usb0_vbus>;
124		itc-setting = <0x4>; /* 4 micro-frames */
125		 /* Incremental burst of unspecified length */
126		ahb-burst-config = <0x0>;
127		tx-burst-size-dword = <0x10>; /* 64 bytes */
128		rx-burst-size-dword = <0x10>;
129		extcon = <0>, <&usb_id>;
130		phy-clkgate-delay-us = <400>;
131		mux-controls = <&usb_switch>;
132		mux-control-names = "usb_switch";
133	};
134
135Example for HSIC:
136
137	usb@2184400 {
138		compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
139		reg = <0x02184400 0x200>;
140		interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
141		clocks = <&clks IMX6QDL_CLK_USBOH3>;
142		fsl,usbphy = <&usbphynop1>;
143		fsl,usbmisc = <&usbmisc 2>;
144		phy_type = "hsic";
145		dr_mode = "host";
146		ahb-burst-config = <0x0>;
147		tx-burst-size-dword = <0x10>;
148		rx-burst-size-dword = <0x10>;
149		pinctrl-names = "idle", "active";
150		pinctrl-0 = <&pinctrl_usbh2_idle>;
151		pinctrl-1 = <&pinctrl_usbh2_active>;
152		#address-cells = <1>;
153		#size-cells = <0>;
154
155		usbnet: ethernet@1 {
156			compatible = "usb424,9730";
157			reg = <1>;
158		};
159	};
160