1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
4  * Copyright (c) 2020 Western Digital Corporation or its affiliates.
5  */
6 #ifndef CLOCK_K210_CLK_H
7 #define CLOCK_K210_CLK_H
8 
9 /*
10  * Kendryte K210 SoC clock identifiers (arbitrary values).
11  */
12 #define K210_CLK_CPU	0
13 #define K210_CLK_SRAM0	1
14 #define K210_CLK_SRAM1	2
15 #define K210_CLK_AI	3
16 #define K210_CLK_DMA	4
17 #define K210_CLK_FFT	5
18 #define K210_CLK_ROM	6
19 #define K210_CLK_DVP	7
20 #define K210_CLK_APB0	8
21 #define K210_CLK_APB1	9
22 #define K210_CLK_APB2	10
23 #define K210_CLK_I2S0	11
24 #define K210_CLK_I2S1	12
25 #define K210_CLK_I2S2	13
26 #define K210_CLK_I2S0_M	14
27 #define K210_CLK_I2S1_M	15
28 #define K210_CLK_I2S2_M	16
29 #define K210_CLK_WDT0	17
30 #define K210_CLK_WDT1	18
31 #define K210_CLK_SPI0	19
32 #define K210_CLK_SPI1	20
33 #define K210_CLK_SPI2	21
34 #define K210_CLK_I2C0	22
35 #define K210_CLK_I2C1	23
36 #define K210_CLK_I2C2	24
37 #define K210_CLK_SPI3	25
38 #define K210_CLK_TIMER0	26
39 #define K210_CLK_TIMER1	27
40 #define K210_CLK_TIMER2	28
41 #define K210_CLK_GPIO	29
42 #define K210_CLK_UART1	30
43 #define K210_CLK_UART2	31
44 #define K210_CLK_UART3	32
45 #define K210_CLK_FPIOA	33
46 #define K210_CLK_SHA	34
47 #define K210_CLK_AES	35
48 #define K210_CLK_OTP	36
49 #define K210_CLK_RTC	37
50 
51 #define K210_NUM_CLKS	38
52 
53 #endif /* CLOCK_K210_CLK_H */
54