1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2 /*
3  * Copyright (C) 2016, The Linux Foundation. All rights reserved.
4  * Copyright (C) 2016-2021, AngeloGioacchino Del Regno
5  *                     <angelogioacchino.delregno@somainline.org>
6  */
7 
8 #ifndef _DT_BINDINGS_CLK_MSM_GCC_8976_H
9 #define _DT_BINDINGS_CLK_MSM_GCC_8976_H
10 
11 #define GPLL0					0
12 #define GPLL2					1
13 #define GPLL3					2
14 #define GPLL4					3
15 #define GPLL6					4
16 #define GPLL0_CLK_SRC				5
17 #define GPLL2_CLK_SRC				6
18 #define GPLL3_CLK_SRC				7
19 #define GPLL4_CLK_SRC				8
20 #define GPLL6_CLK_SRC				9
21 #define GCC_BLSP1_QUP1_SPI_APPS_CLK		10
22 #define GCC_BLSP1_QUP1_I2C_APPS_CLK		11
23 #define GCC_BLSP1_QUP2_I2C_APPS_CLK		12
24 #define GCC_BLSP1_QUP2_SPI_APPS_CLK		13
25 #define GCC_BLSP1_QUP3_I2C_APPS_CLK		14
26 #define GCC_BLSP1_QUP3_SPI_APPS_CLK		15
27 #define GCC_BLSP1_QUP4_I2C_APPS_CLK		16
28 #define GCC_BLSP1_QUP4_SPI_APPS_CLK		17
29 #define GCC_BLSP1_UART1_APPS_CLK		18
30 #define GCC_BLSP1_UART2_APPS_CLK		19
31 #define GCC_BLSP2_QUP1_I2C_APPS_CLK		20
32 #define GCC_BLSP2_QUP1_SPI_APPS_CLK		21
33 #define GCC_BLSP2_QUP2_I2C_APPS_CLK		22
34 #define GCC_BLSP2_QUP2_SPI_APPS_CLK		23
35 #define GCC_BLSP2_QUP3_I2C_APPS_CLK		24
36 #define GCC_BLSP2_QUP3_SPI_APPS_CLK		25
37 #define GCC_BLSP2_QUP4_I2C_APPS_CLK		26
38 #define GCC_BLSP2_QUP4_SPI_APPS_CLK		27
39 #define GCC_BLSP2_UART1_APPS_CLK		28
40 #define GCC_BLSP2_UART2_APPS_CLK		29
41 #define GCC_CAMSS_CCI_AHB_CLK			30
42 #define GCC_CAMSS_CCI_CLK			31
43 #define GCC_CAMSS_CPP_AHB_CLK			32
44 #define GCC_CAMSS_CPP_AXI_CLK			33
45 #define GCC_CAMSS_CPP_CLK			34
46 #define GCC_CAMSS_CSI0_AHB_CLK			35
47 #define GCC_CAMSS_CSI0_CLK			36
48 #define GCC_CAMSS_CSI0PHY_CLK			37
49 #define GCC_CAMSS_CSI0PIX_CLK			38
50 #define GCC_CAMSS_CSI0RDI_CLK			39
51 #define GCC_CAMSS_CSI1_AHB_CLK			40
52 #define GCC_CAMSS_CSI1_CLK			41
53 #define GCC_CAMSS_CSI1PHY_CLK			42
54 #define GCC_CAMSS_CSI1PIX_CLK			43
55 #define GCC_CAMSS_CSI1RDI_CLK			44
56 #define GCC_CAMSS_CSI2_AHB_CLK			45
57 #define GCC_CAMSS_CSI2_CLK			46
58 #define GCC_CAMSS_CSI2PHY_CLK			47
59 #define GCC_CAMSS_CSI2PIX_CLK			48
60 #define GCC_CAMSS_CSI2RDI_CLK			49
61 #define GCC_CAMSS_CSI_VFE0_CLK			50
62 #define GCC_CAMSS_CSI_VFE1_CLK			51
63 #define GCC_CAMSS_GP0_CLK			52
64 #define GCC_CAMSS_GP1_CLK			53
65 #define GCC_CAMSS_ISPIF_AHB_CLK			54
66 #define GCC_CAMSS_JPEG0_CLK			55
67 #define GCC_CAMSS_JPEG_AHB_CLK			56
68 #define GCC_CAMSS_JPEG_AXI_CLK			57
69 #define GCC_CAMSS_MCLK0_CLK			58
70 #define GCC_CAMSS_MCLK1_CLK			59
71 #define GCC_CAMSS_MCLK2_CLK			60
72 #define GCC_CAMSS_MICRO_AHB_CLK			61
73 #define GCC_CAMSS_CSI0PHYTIMER_CLK		62
74 #define GCC_CAMSS_CSI1PHYTIMER_CLK		63
75 #define GCC_CAMSS_AHB_CLK			64
76 #define GCC_CAMSS_TOP_AHB_CLK			65
77 #define GCC_CAMSS_VFE0_CLK			66
78 #define GCC_CAMSS_VFE_AHB_CLK			67
79 #define GCC_CAMSS_VFE_AXI_CLK			68
80 #define GCC_CAMSS_VFE1_AHB_CLK			69
81 #define GCC_CAMSS_VFE1_AXI_CLK			70
82 #define GCC_CAMSS_VFE1_CLK			71
83 #define GCC_DCC_CLK				72
84 #define GCC_GP1_CLK				73
85 #define GCC_GP2_CLK				74
86 #define GCC_GP3_CLK				75
87 #define GCC_MDSS_AHB_CLK			76
88 #define GCC_MDSS_AXI_CLK			77
89 #define GCC_MDSS_ESC0_CLK			78
90 #define GCC_MDSS_ESC1_CLK			79
91 #define GCC_MDSS_MDP_CLK			80
92 #define GCC_MDSS_VSYNC_CLK			81
93 #define GCC_MSS_CFG_AHB_CLK			82
94 #define GCC_MSS_Q6_BIMC_AXI_CLK			83
95 #define GCC_PDM2_CLK				84
96 #define GCC_PRNG_AHB_CLK			85
97 #define GCC_PDM_AHB_CLK				86
98 #define GCC_RBCPR_GFX_AHB_CLK			87
99 #define GCC_RBCPR_GFX_CLK			88
100 #define GCC_SDCC1_AHB_CLK			89
101 #define GCC_SDCC1_APPS_CLK			90
102 #define GCC_SDCC1_ICE_CORE_CLK			91
103 #define GCC_SDCC2_AHB_CLK			92
104 #define GCC_SDCC2_APPS_CLK			93
105 #define GCC_SDCC3_AHB_CLK			94
106 #define GCC_SDCC3_APPS_CLK			95
107 #define GCC_USB2A_PHY_SLEEP_CLK			96
108 #define GCC_USB_HS_PHY_CFG_AHB_CLK		97
109 #define GCC_USB_FS_AHB_CLK			98
110 #define GCC_USB_FS_IC_CLK			99
111 #define GCC_USB_FS_SYSTEM_CLK			100
112 #define GCC_USB_HS_AHB_CLK			101
113 #define GCC_USB_HS_SYSTEM_CLK			102
114 #define GCC_VENUS0_AHB_CLK			103
115 #define GCC_VENUS0_AXI_CLK			104
116 #define GCC_VENUS0_CORE0_VCODEC0_CLK		105
117 #define GCC_VENUS0_CORE1_VCODEC0_CLK		106
118 #define GCC_VENUS0_VCODEC0_CLK			107
119 #define GCC_APSS_AHB_CLK			108
120 #define GCC_APSS_AXI_CLK			109
121 #define GCC_BLSP1_AHB_CLK			110
122 #define GCC_BLSP2_AHB_CLK			111
123 #define GCC_BOOT_ROM_AHB_CLK			112
124 #define GCC_CRYPTO_AHB_CLK			113
125 #define GCC_CRYPTO_AXI_CLK			114
126 #define GCC_CRYPTO_CLK				115
127 #define GCC_CPP_TBU_CLK				116
128 #define GCC_APSS_TCU_CLK			117
129 #define GCC_JPEG_TBU_CLK			118
130 #define GCC_MDP_RT_TBU_CLK			119
131 #define GCC_MDP_TBU_CLK				120
132 #define GCC_SMMU_CFG_CLK			121
133 #define GCC_VENUS_1_TBU_CLK			122
134 #define GCC_VENUS_TBU_CLK			123
135 #define GCC_VFE1_TBU_CLK			124
136 #define GCC_VFE_TBU_CLK				125
137 #define GCC_APS_0_CLK				126
138 #define GCC_APS_1_CLK				127
139 #define APS_0_CLK_SRC				128
140 #define APS_1_CLK_SRC				129
141 #define APSS_AHB_CLK_SRC			130
142 #define BLSP1_QUP1_I2C_APPS_CLK_SRC		131
143 #define BLSP1_QUP1_SPI_APPS_CLK_SRC		132
144 #define BLSP1_QUP2_I2C_APPS_CLK_SRC		133
145 #define BLSP1_QUP2_SPI_APPS_CLK_SRC		134
146 #define BLSP1_QUP3_I2C_APPS_CLK_SRC		135
147 #define BLSP1_QUP3_SPI_APPS_CLK_SRC		136
148 #define BLSP1_QUP4_I2C_APPS_CLK_SRC		137
149 #define BLSP1_QUP4_SPI_APPS_CLK_SRC		138
150 #define BLSP1_UART1_APPS_CLK_SRC		139
151 #define BLSP1_UART2_APPS_CLK_SRC		140
152 #define BLSP2_QUP1_I2C_APPS_CLK_SRC		141
153 #define BLSP2_QUP1_SPI_APPS_CLK_SRC		142
154 #define BLSP2_QUP2_I2C_APPS_CLK_SRC		143
155 #define BLSP2_QUP2_SPI_APPS_CLK_SRC		144
156 #define BLSP2_QUP3_I2C_APPS_CLK_SRC		145
157 #define BLSP2_QUP3_SPI_APPS_CLK_SRC		146
158 #define BLSP2_QUP4_I2C_APPS_CLK_SRC		147
159 #define BLSP2_QUP4_SPI_APPS_CLK_SRC		148
160 #define BLSP2_UART1_APPS_CLK_SRC		149
161 #define BLSP2_UART2_APPS_CLK_SRC		150
162 #define CCI_CLK_SRC				151
163 #define CPP_CLK_SRC				152
164 #define CSI0_CLK_SRC				153
165 #define CSI1_CLK_SRC				154
166 #define CSI2_CLK_SRC				155
167 #define CAMSS_GP0_CLK_SRC			156
168 #define CAMSS_GP1_CLK_SRC			157
169 #define JPEG0_CLK_SRC				158
170 #define MCLK0_CLK_SRC				159
171 #define MCLK1_CLK_SRC				160
172 #define MCLK2_CLK_SRC				161
173 #define CSI0PHYTIMER_CLK_SRC			162
174 #define CSI1PHYTIMER_CLK_SRC			163
175 #define CAMSS_TOP_AHB_CLK_SRC			164
176 #define VFE0_CLK_SRC				165
177 #define VFE1_CLK_SRC				166
178 #define CRYPTO_CLK_SRC				167
179 #define GP1_CLK_SRC				168
180 #define GP2_CLK_SRC				169
181 #define GP3_CLK_SRC				170
182 #define ESC0_CLK_SRC				171
183 #define ESC1_CLK_SRC				172
184 #define MDP_CLK_SRC				173
185 #define VSYNC_CLK_SRC				174
186 #define PDM2_CLK_SRC				175
187 #define RBCPR_GFX_CLK_SRC			176
188 #define SDCC1_APPS_CLK_SRC			177
189 #define SDCC1_ICE_CORE_CLK_SRC			178
190 #define SDCC2_APPS_CLK_SRC			179
191 #define SDCC3_APPS_CLK_SRC			180
192 #define USB_FS_IC_CLK_SRC			181
193 #define USB_FS_SYSTEM_CLK_SRC			182
194 #define USB_HS_SYSTEM_CLK_SRC			183
195 #define VCODEC0_CLK_SRC				184
196 #define GCC_MDSS_BYTE0_CLK_SRC			185
197 #define GCC_MDSS_BYTE1_CLK_SRC			186
198 #define GCC_MDSS_BYTE0_CLK			187
199 #define GCC_MDSS_BYTE1_CLK			188
200 #define GCC_MDSS_PCLK0_CLK_SRC			189
201 #define GCC_MDSS_PCLK1_CLK_SRC			190
202 #define GCC_MDSS_PCLK0_CLK			191
203 #define GCC_MDSS_PCLK1_CLK			192
204 #define GCC_GFX3D_CLK_SRC			193
205 #define GCC_GFX3D_OXILI_CLK			194
206 #define GCC_GFX3D_BIMC_CLK			195
207 #define GCC_GFX3D_OXILI_AHB_CLK			196
208 #define GCC_GFX3D_OXILI_AON_CLK			197
209 #define GCC_GFX3D_OXILI_GMEM_CLK		198
210 #define GCC_GFX3D_OXILI_TIMER_CLK		199
211 #define GCC_GFX3D_TBU0_CLK			200
212 #define GCC_GFX3D_TBU1_CLK			201
213 #define GCC_GFX3D_TCU_CLK			202
214 #define GCC_GFX3D_GTCU_AHB_CLK			203
215 
216 /* GCC block resets */
217 #define RST_CAMSS_MICRO_BCR			0
218 #define RST_USB_HS_BCR				1
219 #define RST_QUSB2_PHY_BCR			2
220 #define RST_USB2_HS_PHY_ONLY_BCR		3
221 #define RST_USB_HS_PHY_CFG_AHB_BCR		4
222 #define RST_USB_FS_BCR				5
223 #define RST_CAMSS_CSI1PIX_BCR			6
224 #define RST_CAMSS_CSI_VFE1_BCR			7
225 #define RST_CAMSS_VFE1_BCR			8
226 #define RST_CAMSS_CPP_BCR			9
227 #define RST_MSS_BCR				10
228 
229 /* GDSCs */
230 #define VENUS_GDSC				0
231 #define VENUS_CORE0_GDSC			1
232 #define VENUS_CORE1_GDSC			2
233 #define MDSS_GDSC				3
234 #define JPEG_GDSC				4
235 #define VFE0_GDSC				5
236 #define VFE1_GDSC				6
237 #define CPP_GDSC				7
238 #define OXILI_GX_GDSC				8
239 #define OXILI_CX_GDSC				9
240 
241 #endif /* _DT_BINDINGS_CLK_MSM_GCC_8976_H */
242