1c66ec88fSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0-or-later */ 2c66ec88fSEmmanuel Vadot /* 3c66ec88fSEmmanuel Vadot * Copyright (c) 2015 Rockchip Electronics Co. Ltd. 4c66ec88fSEmmanuel Vadot * Author: Xing Zheng <zhengxing@rock-chips.com> 5c66ec88fSEmmanuel Vadot */ 6c66ec88fSEmmanuel Vadot 7c66ec88fSEmmanuel Vadot #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H 8c66ec88fSEmmanuel Vadot #define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H 9c66ec88fSEmmanuel Vadot 10c66ec88fSEmmanuel Vadot /* core clocks */ 11c66ec88fSEmmanuel Vadot #define PLL_APLL 1 12c66ec88fSEmmanuel Vadot #define PLL_DPLL 2 13c66ec88fSEmmanuel Vadot #define PLL_GPLL 3 14c66ec88fSEmmanuel Vadot #define ARMCLK 4 15c66ec88fSEmmanuel Vadot 16c66ec88fSEmmanuel Vadot /* sclk gates (special clocks) */ 17c66ec88fSEmmanuel Vadot #define SCLK_GPU 64 18c66ec88fSEmmanuel Vadot #define SCLK_SPI 65 19c66ec88fSEmmanuel Vadot #define SCLK_SDMMC 68 20c66ec88fSEmmanuel Vadot #define SCLK_SDIO 69 21c66ec88fSEmmanuel Vadot #define SCLK_EMMC 71 22c66ec88fSEmmanuel Vadot #define SCLK_NANDC 76 23c66ec88fSEmmanuel Vadot #define SCLK_UART0 77 24c66ec88fSEmmanuel Vadot #define SCLK_UART1 78 25c66ec88fSEmmanuel Vadot #define SCLK_UART2 79 26c66ec88fSEmmanuel Vadot #define SCLK_I2S 82 27c66ec88fSEmmanuel Vadot #define SCLK_SPDIF 83 28c66ec88fSEmmanuel Vadot #define SCLK_TIMER0 85 29c66ec88fSEmmanuel Vadot #define SCLK_TIMER1 86 30c66ec88fSEmmanuel Vadot #define SCLK_TIMER2 87 31c66ec88fSEmmanuel Vadot #define SCLK_TIMER3 88 32c66ec88fSEmmanuel Vadot #define SCLK_OTGPHY0 93 33c66ec88fSEmmanuel Vadot #define SCLK_LCDC 100 34c66ec88fSEmmanuel Vadot #define SCLK_HDMI 109 35c66ec88fSEmmanuel Vadot #define SCLK_HEVC 111 36c66ec88fSEmmanuel Vadot #define SCLK_I2S_OUT 113 37c66ec88fSEmmanuel Vadot #define SCLK_SDMMC_DRV 114 38c66ec88fSEmmanuel Vadot #define SCLK_SDIO_DRV 115 39c66ec88fSEmmanuel Vadot #define SCLK_EMMC_DRV 117 40c66ec88fSEmmanuel Vadot #define SCLK_SDMMC_SAMPLE 118 41c66ec88fSEmmanuel Vadot #define SCLK_SDIO_SAMPLE 119 42c66ec88fSEmmanuel Vadot #define SCLK_EMMC_SAMPLE 121 43c66ec88fSEmmanuel Vadot #define SCLK_PVTM_CORE 123 44c66ec88fSEmmanuel Vadot #define SCLK_PVTM_GPU 124 45c66ec88fSEmmanuel Vadot #define SCLK_PVTM_VIDEO 125 46c66ec88fSEmmanuel Vadot #define SCLK_MAC 151 47c66ec88fSEmmanuel Vadot #define SCLK_MACREF 152 48c66ec88fSEmmanuel Vadot #define SCLK_MACPLL 153 49c66ec88fSEmmanuel Vadot #define SCLK_SFC 160 50c66ec88fSEmmanuel Vadot 51c66ec88fSEmmanuel Vadot /* aclk gates */ 52c66ec88fSEmmanuel Vadot #define ACLK_DMAC2 194 53c66ec88fSEmmanuel Vadot #define ACLK_LCDC 197 54c66ec88fSEmmanuel Vadot #define ACLK_VIO 203 55c66ec88fSEmmanuel Vadot #define ACLK_VCODEC 208 56c66ec88fSEmmanuel Vadot #define ACLK_CPU 209 57c66ec88fSEmmanuel Vadot #define ACLK_PERI 210 58c66ec88fSEmmanuel Vadot 59c66ec88fSEmmanuel Vadot /* pclk gates */ 60c66ec88fSEmmanuel Vadot #define PCLK_GPIO0 320 61c66ec88fSEmmanuel Vadot #define PCLK_GPIO1 321 62c66ec88fSEmmanuel Vadot #define PCLK_GPIO2 322 63c66ec88fSEmmanuel Vadot #define PCLK_GRF 329 64c66ec88fSEmmanuel Vadot #define PCLK_I2C0 332 65c66ec88fSEmmanuel Vadot #define PCLK_I2C1 333 66c66ec88fSEmmanuel Vadot #define PCLK_I2C2 334 67c66ec88fSEmmanuel Vadot #define PCLK_SPI 338 68c66ec88fSEmmanuel Vadot #define PCLK_UART0 341 69c66ec88fSEmmanuel Vadot #define PCLK_UART1 342 70c66ec88fSEmmanuel Vadot #define PCLK_UART2 343 71c66ec88fSEmmanuel Vadot #define PCLK_PWM 350 72c66ec88fSEmmanuel Vadot #define PCLK_TIMER 353 73c66ec88fSEmmanuel Vadot #define PCLK_HDMI 360 74c66ec88fSEmmanuel Vadot #define PCLK_CPU 362 75c66ec88fSEmmanuel Vadot #define PCLK_PERI 363 76c66ec88fSEmmanuel Vadot #define PCLK_DDRUPCTL 364 77c66ec88fSEmmanuel Vadot #define PCLK_WDT 368 78c66ec88fSEmmanuel Vadot #define PCLK_ACODEC 369 79c66ec88fSEmmanuel Vadot 80c66ec88fSEmmanuel Vadot /* hclk gates */ 81c66ec88fSEmmanuel Vadot #define HCLK_OTG0 449 82c66ec88fSEmmanuel Vadot #define HCLK_OTG1 450 83c66ec88fSEmmanuel Vadot #define HCLK_NANDC 453 84*354d7675SEmmanuel Vadot #define HCLK_SFC 454 85c66ec88fSEmmanuel Vadot #define HCLK_SDMMC 456 86c66ec88fSEmmanuel Vadot #define HCLK_SDIO 457 87c66ec88fSEmmanuel Vadot #define HCLK_EMMC 459 88c66ec88fSEmmanuel Vadot #define HCLK_MAC 460 89c66ec88fSEmmanuel Vadot #define HCLK_I2S 462 90c66ec88fSEmmanuel Vadot #define HCLK_LCDC 465 91c66ec88fSEmmanuel Vadot #define HCLK_ROM 467 92c66ec88fSEmmanuel Vadot #define HCLK_VIO_BUS 472 93c66ec88fSEmmanuel Vadot #define HCLK_VCODEC 476 94c66ec88fSEmmanuel Vadot #define HCLK_CPU 477 95c66ec88fSEmmanuel Vadot #define HCLK_PERI 478 96c66ec88fSEmmanuel Vadot 97c66ec88fSEmmanuel Vadot #define CLK_NR_CLKS (HCLK_PERI + 1) 98c66ec88fSEmmanuel Vadot 99c66ec88fSEmmanuel Vadot /* soft-reset indices */ 100c66ec88fSEmmanuel Vadot #define SRST_CORE0 0 101c66ec88fSEmmanuel Vadot #define SRST_CORE1 1 102c66ec88fSEmmanuel Vadot #define SRST_CORE0_DBG 4 103c66ec88fSEmmanuel Vadot #define SRST_CORE1_DBG 5 104c66ec88fSEmmanuel Vadot #define SRST_CORE0_POR 8 105c66ec88fSEmmanuel Vadot #define SRST_CORE1_POR 9 106c66ec88fSEmmanuel Vadot #define SRST_L2C 12 107c66ec88fSEmmanuel Vadot #define SRST_TOPDBG 13 108c66ec88fSEmmanuel Vadot #define SRST_STRC_SYS_A 14 109c66ec88fSEmmanuel Vadot #define SRST_PD_CORE_NIU 15 110c66ec88fSEmmanuel Vadot 111c66ec88fSEmmanuel Vadot #define SRST_TIMER2 16 112c66ec88fSEmmanuel Vadot #define SRST_CPUSYS_H 17 113c66ec88fSEmmanuel Vadot #define SRST_AHB2APB_H 19 114c66ec88fSEmmanuel Vadot #define SRST_TIMER3 20 115c66ec88fSEmmanuel Vadot #define SRST_INTMEM 21 116c66ec88fSEmmanuel Vadot #define SRST_ROM 22 117c66ec88fSEmmanuel Vadot #define SRST_PERI_NIU 23 118c66ec88fSEmmanuel Vadot #define SRST_I2S 24 119c66ec88fSEmmanuel Vadot #define SRST_DDR_PLL 25 120c66ec88fSEmmanuel Vadot #define SRST_GPU_DLL 26 121c66ec88fSEmmanuel Vadot #define SRST_TIMER0 27 122c66ec88fSEmmanuel Vadot #define SRST_TIMER1 28 123c66ec88fSEmmanuel Vadot #define SRST_CORE_DLL 29 124c66ec88fSEmmanuel Vadot #define SRST_EFUSE_P 30 125c66ec88fSEmmanuel Vadot #define SRST_ACODEC_P 31 126c66ec88fSEmmanuel Vadot 127c66ec88fSEmmanuel Vadot #define SRST_GPIO0 32 128c66ec88fSEmmanuel Vadot #define SRST_GPIO1 33 129c66ec88fSEmmanuel Vadot #define SRST_GPIO2 34 130c66ec88fSEmmanuel Vadot #define SRST_UART0 39 131c66ec88fSEmmanuel Vadot #define SRST_UART1 40 132c66ec88fSEmmanuel Vadot #define SRST_UART2 41 133c66ec88fSEmmanuel Vadot #define SRST_I2C0 43 134c66ec88fSEmmanuel Vadot #define SRST_I2C1 44 135c66ec88fSEmmanuel Vadot #define SRST_I2C2 45 136c66ec88fSEmmanuel Vadot #define SRST_SFC 47 137c66ec88fSEmmanuel Vadot 138c66ec88fSEmmanuel Vadot #define SRST_PWM0 48 139c66ec88fSEmmanuel Vadot #define SRST_DAP 51 140c66ec88fSEmmanuel Vadot #define SRST_DAP_SYS 52 141c66ec88fSEmmanuel Vadot #define SRST_GRF 55 142c66ec88fSEmmanuel Vadot #define SRST_PERIPHSYS_A 57 143c66ec88fSEmmanuel Vadot #define SRST_PERIPHSYS_H 58 144c66ec88fSEmmanuel Vadot #define SRST_PERIPHSYS_P 59 145c66ec88fSEmmanuel Vadot #define SRST_CPU_PERI 61 146c66ec88fSEmmanuel Vadot #define SRST_EMEM_PERI 62 147c66ec88fSEmmanuel Vadot #define SRST_USB_PERI 63 148c66ec88fSEmmanuel Vadot 149c66ec88fSEmmanuel Vadot #define SRST_DMA2 64 150c66ec88fSEmmanuel Vadot #define SRST_MAC 66 151c66ec88fSEmmanuel Vadot #define SRST_NANDC 68 152c66ec88fSEmmanuel Vadot #define SRST_USBOTG0 69 153c66ec88fSEmmanuel Vadot #define SRST_OTGC0 71 154c66ec88fSEmmanuel Vadot #define SRST_USBOTG1 72 155c66ec88fSEmmanuel Vadot #define SRST_OTGC1 74 156c66ec88fSEmmanuel Vadot #define SRST_DDRMSCH 79 157c66ec88fSEmmanuel Vadot 158c66ec88fSEmmanuel Vadot #define SRST_MMC0 81 159c66ec88fSEmmanuel Vadot #define SRST_SDIO 82 160c66ec88fSEmmanuel Vadot #define SRST_EMMC 83 161c66ec88fSEmmanuel Vadot #define SRST_SPI0 84 162c66ec88fSEmmanuel Vadot #define SRST_WDT 86 163c66ec88fSEmmanuel Vadot #define SRST_DDRPHY 88 164c66ec88fSEmmanuel Vadot #define SRST_DDRPHY_P 89 165c66ec88fSEmmanuel Vadot #define SRST_DDRCTRL 90 166c66ec88fSEmmanuel Vadot #define SRST_DDRCTRL_P 91 167c66ec88fSEmmanuel Vadot 168c66ec88fSEmmanuel Vadot #define SRST_HDMI_P 96 169c66ec88fSEmmanuel Vadot #define SRST_VIO_BUS_H 99 170c66ec88fSEmmanuel Vadot #define SRST_UTMI0 103 171c66ec88fSEmmanuel Vadot #define SRST_UTMI1 104 172c66ec88fSEmmanuel Vadot #define SRST_USBPOR 105 173c66ec88fSEmmanuel Vadot 174c66ec88fSEmmanuel Vadot #define SRST_VCODEC_A 112 175c66ec88fSEmmanuel Vadot #define SRST_VCODEC_H 113 176c66ec88fSEmmanuel Vadot #define SRST_VIO1_A 114 177c66ec88fSEmmanuel Vadot #define SRST_HEVC 115 178c66ec88fSEmmanuel Vadot #define SRST_VCODEC_NIU_A 116 179c66ec88fSEmmanuel Vadot #define SRST_LCDC1_A 117 180c66ec88fSEmmanuel Vadot #define SRST_LCDC1_H 118 181c66ec88fSEmmanuel Vadot #define SRST_LCDC1_D 119 182c66ec88fSEmmanuel Vadot #define SRST_GPU 120 183c66ec88fSEmmanuel Vadot #define SRST_GPU_NIU_A 122 184c66ec88fSEmmanuel Vadot 185c66ec88fSEmmanuel Vadot #define SRST_DBG_P 131 186c66ec88fSEmmanuel Vadot 187c66ec88fSEmmanuel Vadot #endif 188