1*c66ec88fSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0 */ 2*c66ec88fSEmmanuel Vadot /** @file */ 3*c66ec88fSEmmanuel Vadot 4*c66ec88fSEmmanuel Vadot #ifndef _MACH_T186_CLK_T186_H 5*c66ec88fSEmmanuel Vadot #define _MACH_T186_CLK_T186_H 6*c66ec88fSEmmanuel Vadot 7*c66ec88fSEmmanuel Vadot /** 8*c66ec88fSEmmanuel Vadot * @defgroup clock_ids Clock Identifiers 9*c66ec88fSEmmanuel Vadot * @{ 10*c66ec88fSEmmanuel Vadot * @defgroup extern_input external input clocks 11*c66ec88fSEmmanuel Vadot * @{ 12*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_OSC 13*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_CLK_32K 14*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_DTV_INPUT 15*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SOR0_PAD_CLKOUT 16*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SOR1_PAD_CLKOUT 17*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_I2S1_SYNC_INPUT 18*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_I2S2_SYNC_INPUT 19*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_I2S3_SYNC_INPUT 20*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_I2S4_SYNC_INPUT 21*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_I2S5_SYNC_INPUT 22*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_I2S6_SYNC_INPUT 23*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SPDIFIN_SYNC_INPUT 24*c66ec88fSEmmanuel Vadot * @} 25*c66ec88fSEmmanuel Vadot * 26*c66ec88fSEmmanuel Vadot * @defgroup extern_output external output clocks 27*c66ec88fSEmmanuel Vadot * @{ 28*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_EXTPERIPH1 29*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_EXTPERIPH2 30*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_EXTPERIPH3 31*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_EXTPERIPH4 32*c66ec88fSEmmanuel Vadot * @} 33*c66ec88fSEmmanuel Vadot * 34*c66ec88fSEmmanuel Vadot * @defgroup display_clks display related clocks 35*c66ec88fSEmmanuel Vadot * @{ 36*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_CEC 37*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_DSIC 38*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_DSIC_LP 39*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_DSID 40*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_DSID_LP 41*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_DPAUX1 42*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_DPAUX 43*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_HDA2HDMICODEC 44*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_NVDISPLAY_DISP 45*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_NVDISPLAY_DSC 46*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_NVDISPLAY_P0 47*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_NVDISPLAY_P1 48*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_NVDISPLAY_P2 49*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_NVDISPLAYHUB 50*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SOR_SAFE 51*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SOR0 52*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SOR0_OUT 53*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SOR1 54*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SOR1_OUT 55*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_DSI 56*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_MIPI_CAL 57*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_DSIA_LP 58*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_DSIB 59*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_DSIB_LP 60*c66ec88fSEmmanuel Vadot * @} 61*c66ec88fSEmmanuel Vadot * 62*c66ec88fSEmmanuel Vadot * @defgroup camera_clks camera related clocks 63*c66ec88fSEmmanuel Vadot * @{ 64*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_NVCSI 65*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_NVCSILP 66*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_VI 67*c66ec88fSEmmanuel Vadot * @} 68*c66ec88fSEmmanuel Vadot * 69*c66ec88fSEmmanuel Vadot * @defgroup audio_clks audio related clocks 70*c66ec88fSEmmanuel Vadot * @{ 71*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_ACLK 72*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_ADSP 73*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_ADSPNEON 74*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_AHUB 75*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_APE 76*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_APB2APE 77*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_AUD_MCLK 78*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_DMIC1 79*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_DMIC2 80*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_DMIC3 81*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_DMIC4 82*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_DSPK1 83*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_DSPK2 84*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_HDA 85*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_HDA2CODEC_2X 86*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_I2S1 87*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_I2S2 88*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_I2S3 89*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_I2S4 90*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_I2S5 91*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_I2S6 92*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_MAUD 93*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLL_A_OUT0 94*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SPDIF_DOUBLER 95*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SPDIF_IN 96*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SPDIF_OUT 97*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SYNC_DMIC1 98*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SYNC_DMIC2 99*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SYNC_DMIC3 100*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SYNC_DMIC4 101*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SYNC_DMIC5 102*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SYNC_DSPK1 103*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SYNC_DSPK2 104*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SYNC_I2S1 105*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SYNC_I2S2 106*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SYNC_I2S3 107*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SYNC_I2S4 108*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SYNC_I2S5 109*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SYNC_I2S6 110*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SYNC_SPDIF 111*c66ec88fSEmmanuel Vadot * @} 112*c66ec88fSEmmanuel Vadot * 113*c66ec88fSEmmanuel Vadot * @defgroup uart_clks UART clocks 114*c66ec88fSEmmanuel Vadot * @{ 115*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_AON_UART_FST_MIPI_CAL 116*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_UARTA 117*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_UARTB 118*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_UARTC 119*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_UARTD 120*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_UARTE 121*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_UARTF 122*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_UARTG 123*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_UART_FST_MIPI_CAL 124*c66ec88fSEmmanuel Vadot * @} 125*c66ec88fSEmmanuel Vadot * 126*c66ec88fSEmmanuel Vadot * @defgroup i2c_clks I2C clocks 127*c66ec88fSEmmanuel Vadot * @{ 128*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_AON_I2C_SLOW 129*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_I2C1 130*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_I2C2 131*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_I2C3 132*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_I2C4 133*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_I2C5 134*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_I2C6 135*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_I2C8 136*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_I2C9 137*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_I2C1 138*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_I2C12 139*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_I2C13 140*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_I2C14 141*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_I2C_SLOW 142*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_VI_I2C 143*c66ec88fSEmmanuel Vadot * @} 144*c66ec88fSEmmanuel Vadot * 145*c66ec88fSEmmanuel Vadot * @defgroup spi_clks SPI clocks 146*c66ec88fSEmmanuel Vadot * @{ 147*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SPI1 148*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SPI2 149*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SPI3 150*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SPI4 151*c66ec88fSEmmanuel Vadot * @} 152*c66ec88fSEmmanuel Vadot * 153*c66ec88fSEmmanuel Vadot * @defgroup storage storage related clocks 154*c66ec88fSEmmanuel Vadot * @{ 155*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SATA 156*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SATA_OOB 157*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SATA_IOBIST 158*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SDMMC_LEGACY_TM 159*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SDMMC1 160*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SDMMC2 161*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SDMMC3 162*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SDMMC4 163*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_QSPI 164*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_QSPI_OUT 165*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_UFSDEV_REF 166*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_UFSHC 167*c66ec88fSEmmanuel Vadot * @} 168*c66ec88fSEmmanuel Vadot * 169*c66ec88fSEmmanuel Vadot * @defgroup pwm_clks PWM clocks 170*c66ec88fSEmmanuel Vadot * @{ 171*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PWM1 172*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PWM2 173*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PWM3 174*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PWM4 175*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PWM5 176*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PWM6 177*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PWM7 178*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PWM8 179*c66ec88fSEmmanuel Vadot * @} 180*c66ec88fSEmmanuel Vadot * 181*c66ec88fSEmmanuel Vadot * @defgroup plls PLLs and related clocks 182*c66ec88fSEmmanuel Vadot * @{ 183*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLREFE_OUT_GATED 184*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLREFE_OUT1 185*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLD_OUT1 186*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLP_OUT0 187*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLP_OUT5 188*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLA 189*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLE_PWRSEQ 190*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLA_OUT1 191*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLREFE_REF 192*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_UPHY_PLL0_PWRSEQ 193*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_UPHY_PLL1_PWRSEQ 194*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH 195*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLREFE_PEX 196*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLREFE_IDDQ 197*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLC_OUT_AON 198*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLC_OUT_ISP 199*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLC_OUT_VE 200*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLC4_OUT 201*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLREFE_OUT 202*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLREFE_PLL_REF 203*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLE 204*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLC 205*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLP 206*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLD 207*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLD2 208*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLREFE_VCO 209*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLC2 210*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLC3 211*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLDP 212*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLC4_VCO 213*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLA1 214*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLNVCSI 215*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLDISPHUB 216*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLD3 217*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLBPMPCAM 218*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLAON 219*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLU 220*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLC4_VCO_DIV2 221*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLL_REF 222*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLREFE_OUT1_DIV5 223*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_UTMIP_PLL_PWRSEQ 224*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLL_U_48M 225*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLL_U_480M 226*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLC4_OUT0 227*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLC4_OUT1 228*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLC4_OUT2 229*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLC4_OUT_MUX 230*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_DFLLDISP_DIV 231*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLDISPHUB_DIV 232*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PLLP_DIV8 233*c66ec88fSEmmanuel Vadot * @} 234*c66ec88fSEmmanuel Vadot * 235*c66ec88fSEmmanuel Vadot * @defgroup nafll_clks NAFLL clock sources 236*c66ec88fSEmmanuel Vadot * @{ 237*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_NAFLL_AXI_CBB 238*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_NAFLL_BCPU 239*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_NAFLL_BPMP 240*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_NAFLL_DISP 241*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_NAFLL_GPU 242*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_NAFLL_ISP 243*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_NAFLL_MCPU 244*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_NAFLL_NVDEC 245*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_NAFLL_NVENC 246*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_NAFLL_NVJPG 247*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_NAFLL_SCE 248*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_NAFLL_SE 249*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_NAFLL_TSEC 250*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_NAFLL_TSECB 251*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_NAFLL_VI 252*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_NAFLL_VIC 253*c66ec88fSEmmanuel Vadot * @} 254*c66ec88fSEmmanuel Vadot * 255*c66ec88fSEmmanuel Vadot * @defgroup mphy MPHY related clocks 256*c66ec88fSEmmanuel Vadot * @{ 257*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_MPHY_L0_RX_SYMB 258*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_MPHY_L0_RX_LS_BIT 259*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_MPHY_L0_TX_SYMB 260*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT 261*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_MPHY_L0_RX_ANA 262*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_MPHY_L1_RX_ANA 263*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_MPHY_IOBIST 264*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_MPHY_TX_1MHZ_REF 265*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_MPHY_CORE_PLL_FIXED 266*c66ec88fSEmmanuel Vadot * @} 267*c66ec88fSEmmanuel Vadot * 268*c66ec88fSEmmanuel Vadot * @defgroup eavb EAVB related clocks 269*c66ec88fSEmmanuel Vadot * @{ 270*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_EQOS_AXI 271*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_EQOS_PTP_REF 272*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_EQOS_RX 273*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_EQOS_RX_INPUT 274*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_EQOS_TX 275*c66ec88fSEmmanuel Vadot * @} 276*c66ec88fSEmmanuel Vadot * 277*c66ec88fSEmmanuel Vadot * @defgroup usb USB related clocks 278*c66ec88fSEmmanuel Vadot * @{ 279*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PEX_USB_PAD0_MGMT 280*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PEX_USB_PAD1_MGMT 281*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_HSIC_TRK 282*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_USB2_TRK 283*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_USB2_HSIC_TRK 284*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_XUSB_CORE_SS 285*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_XUSB_CORE_DEV 286*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_XUSB_FALCON 287*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_XUSB_FS 288*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_XUSB 289*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_XUSB_DEV 290*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_XUSB_HOST 291*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_XUSB_SS 292*c66ec88fSEmmanuel Vadot * @} 293*c66ec88fSEmmanuel Vadot * 294*c66ec88fSEmmanuel Vadot * @defgroup bigblock compute block related clocks 295*c66ec88fSEmmanuel Vadot * @{ 296*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_GPCCLK 297*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_GPC2CLK 298*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_GPU 299*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_HOST1X 300*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_ISP 301*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_NVDEC 302*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_NVENC 303*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_NVJPG 304*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SE 305*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_TSEC 306*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_TSECB 307*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_VIC 308*c66ec88fSEmmanuel Vadot * @} 309*c66ec88fSEmmanuel Vadot * 310*c66ec88fSEmmanuel Vadot * @defgroup can CAN bus related clocks 311*c66ec88fSEmmanuel Vadot * @{ 312*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_CAN1 313*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_CAN1_HOST 314*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_CAN2 315*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_CAN2_HOST 316*c66ec88fSEmmanuel Vadot * @} 317*c66ec88fSEmmanuel Vadot * 318*c66ec88fSEmmanuel Vadot * @defgroup system basic system clocks 319*c66ec88fSEmmanuel Vadot * @{ 320*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_ACTMON 321*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_AON_APB 322*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_AON_CPU_NIC 323*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_AON_NIC 324*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_AXI_CBB 325*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_BPMP_APB 326*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_BPMP_CPU_NIC 327*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_BPMP_NIC_RATE 328*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_CLK_M 329*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_EMC 330*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_MSS_ENCRYPT 331*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SCE_APB 332*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SCE_CPU_NIC 333*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_SCE_NIC 334*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_TSC 335*c66ec88fSEmmanuel Vadot * @} 336*c66ec88fSEmmanuel Vadot * 337*c66ec88fSEmmanuel Vadot * @defgroup pcie_clks PCIe related clocks 338*c66ec88fSEmmanuel Vadot * @{ 339*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_AFI 340*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PCIE 341*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PCIE2_IOBIST 342*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PCIERX0 343*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PCIERX1 344*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PCIERX2 345*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PCIERX3 346*c66ec88fSEmmanuel Vadot * @def TEGRA186_CLK_PCIERX4 347*c66ec88fSEmmanuel Vadot * @} 348*c66ec88fSEmmanuel Vadot */ 349*c66ec88fSEmmanuel Vadot 350*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_FUSE */ 351*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_FUSE 0 352*c66ec88fSEmmanuel Vadot /** 353*c66ec88fSEmmanuel Vadot * @brief It's not what you think 354*c66ec88fSEmmanuel Vadot * @details output of gate CLK_ENB_GPU. This output connects to the GPU 355*c66ec88fSEmmanuel Vadot * pwrclk. @warning: This is almost certainly not the clock you think 356*c66ec88fSEmmanuel Vadot * it is. If you're looking for the clock of the graphics engine, see 357*c66ec88fSEmmanuel Vadot * TEGRA186_GPCCLK 358*c66ec88fSEmmanuel Vadot */ 359*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_GPU 1 360*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_PCIE */ 361*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PCIE 3 362*c66ec88fSEmmanuel Vadot /** @brief output of the divider IPFS_CLK_DIVISOR */ 363*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_AFI 4 364*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_PCIE2_IOBIST */ 365*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PCIE2_IOBIST 5 366*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_PCIERX0*/ 367*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PCIERX0 6 368*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_PCIERX1*/ 369*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PCIERX1 7 370*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_PCIERX2*/ 371*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PCIERX2 8 372*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_PCIERX3*/ 373*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PCIERX3 9 374*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_PCIERX4*/ 375*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PCIERX4 10 376*c66ec88fSEmmanuel Vadot /** @brief output branch of PLL_C for ISP, controlled by gate CLK_ENB_PLLC_OUT_ISP */ 377*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLC_OUT_ISP 11 378*c66ec88fSEmmanuel Vadot /** @brief output branch of PLL_C for VI, controlled by gate CLK_ENB_PLLC_OUT_VE */ 379*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLC_OUT_VE 12 380*c66ec88fSEmmanuel Vadot /** @brief output branch of PLL_C for AON domain, controlled by gate CLK_ENB_PLLC_OUT_AON */ 381*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLC_OUT_AON 13 382*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_SOR_SAFE */ 383*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SOR_SAFE 39 384*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */ 385*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_I2S2 42 386*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */ 387*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_I2S3 43 388*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDF_IN */ 389*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SPDIF_IN 44 390*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_SPDIF_DOUBLER */ 391*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SPDIF_DOUBLER 45 392*c66ec88fSEmmanuel Vadot /** @clkdesc{spi_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_SPI3} */ 393*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SPI3 46 394*c66ec88fSEmmanuel Vadot /** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1} */ 395*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_I2C1 47 396*c66ec88fSEmmanuel Vadot /** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5} */ 397*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_I2C5 48 398*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */ 399*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SPI1 49 400*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */ 401*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_ISP 50 402*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */ 403*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_VI 51 404*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */ 405*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SDMMC1 52 406*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 */ 407*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SDMMC2 53 408*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ 409*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SDMMC4 54 410*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ 411*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_UARTA 55 412*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTB */ 413*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_UARTB 56 414*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */ 415*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_HOST1X 57 416*c66ec88fSEmmanuel Vadot /** 417*c66ec88fSEmmanuel Vadot * @brief controls the EMC clock frequency. 418*c66ec88fSEmmanuel Vadot * @details Doing a clk_set_rate on this clock will select the 419*c66ec88fSEmmanuel Vadot * appropriate clock source, program the source rate and execute a 420*c66ec88fSEmmanuel Vadot * specific sequence to switch to the new clock source for both memory 421*c66ec88fSEmmanuel Vadot * controllers. This can be used to control the balance between memory 422*c66ec88fSEmmanuel Vadot * throughput and memory controller power. 423*c66ec88fSEmmanuel Vadot */ 424*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_EMC 58 425*c66ec88fSEmmanuel Vadot /* @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4 */ 426*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_EXTPERIPH4 73 427*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI4 */ 428*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SPI4 74 429*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */ 430*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_I2C3 75 431*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 */ 432*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SDMMC3 76 433*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTD */ 434*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_UARTD 77 435*c66ec88fSEmmanuel Vadot /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */ 436*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_I2S1 79 437*c66ec88fSEmmanuel Vadot /** output of gate CLK_ENB_DTV */ 438*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_DTV 80 439*c66ec88fSEmmanuel Vadot /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSEC */ 440*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_TSEC 81 441*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_DP2 */ 442*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_DP2 82 443*c66ec88fSEmmanuel Vadot /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */ 444*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_I2S4 84 445*c66ec88fSEmmanuel Vadot /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */ 446*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_I2S5 85 447*c66ec88fSEmmanuel Vadot /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */ 448*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_I2C4 86 449*c66ec88fSEmmanuel Vadot /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */ 450*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_AHUB 87 451*c66ec88fSEmmanuel Vadot /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X */ 452*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_HDA2CODEC_2X 88 453*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 */ 454*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_EXTPERIPH1 89 455*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2 */ 456*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_EXTPERIPH2 90 457*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3 */ 458*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_EXTPERIPH3 91 459*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW */ 460*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_I2C_SLOW 92 461*c66ec88fSEmmanuel Vadot /** @brief output of the SOR1_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */ 462*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SOR1 93 463*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_CEC */ 464*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_CEC 94 465*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_DPAUX1 */ 466*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_DPAUX1 95 467*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_DPAUX */ 468*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_DPAUX 96 469*c66ec88fSEmmanuel Vadot /** @brief output of the SOR0_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */ 470*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SOR0 97 471*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_HDA2HDMICODEC */ 472*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_HDA2HDMICODEC 98 473*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SATA */ 474*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SATA 99 475*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_SATA_OOB */ 476*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SATA_OOB 100 477*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_SATA_IOBIST */ 478*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SATA_IOBIST 101 479*c66ec88fSEmmanuel Vadot /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA */ 480*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_HDA 102 481*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SE */ 482*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SE 103 483*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_APB2APE */ 484*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_APB2APE 104 485*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */ 486*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_APE 105 487*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_IQC1 */ 488*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_IQC1 106 489*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_IQC2 */ 490*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_IQC2 107 491*c66ec88fSEmmanuel Vadot /** divide by 2 version of TEGRA186_CLK_PLLREFE_VCO */ 492*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLREFE_OUT 108 493*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_PLLREFE_PLL_REF */ 494*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLREFE_PLL_REF 109 495*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_PLLC4_OUT */ 496*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLC4_OUT 110 497*c66ec88fSEmmanuel Vadot /** @brief output of mux xusb_core_clk_switch on page 67 of T186_Clocks_IAS.doc */ 498*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_XUSB 111 499*c66ec88fSEmmanuel Vadot /** controls xusb_dev_ce signal on page 66 and 67 of T186_Clocks_IAS.doc */ 500*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_XUSB_DEV 112 501*c66ec88fSEmmanuel Vadot /** controls xusb_host_ce signal on page 67 of T186_Clocks_IAS.doc */ 502*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_XUSB_HOST 113 503*c66ec88fSEmmanuel Vadot /** controls xusb_ss_ce signal on page 67 of T186_Clocks_IAS.doc */ 504*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_XUSB_SS 114 505*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_DSI */ 506*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_DSI 115 507*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_MIPI_CAL */ 508*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_MIPI_CAL 116 509*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP */ 510*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_DSIA_LP 117 511*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_DSIB */ 512*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_DSIB 118 513*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP */ 514*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_DSIB_LP 119 515*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */ 516*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_DMIC1 122 517*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */ 518*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_DMIC2 123 519*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */ 520*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_AUD_MCLK 124 521*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */ 522*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_I2C6 125 523*c66ec88fSEmmanuel Vadot /**output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL */ 524*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_UART_FST_MIPI_CAL 126 525*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */ 526*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_VIC 127 527*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM */ 528*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SDMMC_LEGACY_TM 128 529*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC */ 530*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_NVDEC 129 531*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG */ 532*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_NVJPG 130 533*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVENC */ 534*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_NVENC 131 535*c66ec88fSEmmanuel Vadot /** @brief output of the QSPI_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */ 536*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_QSPI 132 537*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C */ 538*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_VI_I2C 133 539*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_HSIC_TRK */ 540*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_HSIC_TRK 134 541*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_USB2_TRK */ 542*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_USB2_TRK 135 543*c66ec88fSEmmanuel Vadot /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MAUD */ 544*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_MAUD 136 545*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSECB */ 546*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_TSECB 137 547*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_ADSP */ 548*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_ADSP 138 549*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_ADSPNEON */ 550*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_ADSPNEON 139 551*c66ec88fSEmmanuel Vadot /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB */ 552*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_MPHY_L0_RX_SYMB 140 553*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_MPHY_L0_RX_LS_BIT */ 554*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_MPHY_L0_RX_LS_BIT 141 555*c66ec88fSEmmanuel Vadot /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB */ 556*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_MPHY_L0_TX_SYMB 142 557*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_MPHY_L0_TX_LS_3XBIT */ 558*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT 143 559*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_MPHY_L0_RX_ANA */ 560*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_MPHY_L0_RX_ANA 144 561*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_MPHY_L1_RX_ANA */ 562*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_MPHY_L1_RX_ANA 145 563*c66ec88fSEmmanuel Vadot /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST */ 564*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_MPHY_IOBIST 146 565*c66ec88fSEmmanuel Vadot /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF */ 566*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_MPHY_TX_1MHZ_REF 147 567*c66ec88fSEmmanuel Vadot /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED */ 568*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_MPHY_CORE_PLL_FIXED 148 569*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */ 570*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_AXI_CBB 149 571*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */ 572*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_DMIC3 150 573*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */ 574*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_DMIC4 151 575*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */ 576*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_DSPK1 152 577*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */ 578*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_DSPK2 153 579*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */ 580*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_I2S6 154 581*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0 */ 582*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_NVDISPLAY_P0 155 583*c66ec88fSEmmanuel Vadot /** @brief output of the NVDISPLAY_DISP_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP */ 584*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_NVDISPLAY_DISP 156 585*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_NVDISPLAY_DSC */ 586*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_NVDISPLAY_DSC 157 587*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB */ 588*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_NVDISPLAYHUB 158 589*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1 */ 590*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_NVDISPLAY_P1 159 591*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2 */ 592*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_NVDISPLAY_P2 160 593*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH */ 594*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_TACH 166 595*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_EQOS */ 596*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_EQOS_AXI 167 597*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_EQOS_RX */ 598*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_EQOS_RX 168 599*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS */ 600*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_UFSHC 178 601*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF */ 602*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_UFSDEV_REF 179 603*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI */ 604*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_NVCSI 180 605*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP */ 606*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_NVCSILP 181 607*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */ 608*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_I2C7 182 609*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */ 610*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_I2C9 183 611*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C12 */ 612*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_I2C12 184 613*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C13 */ 614*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_I2C13 185 615*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C14 */ 616*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_I2C14 186 617*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */ 618*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PWM1 187 619*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */ 620*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PWM2 188 621*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */ 622*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PWM3 189 623*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */ 624*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PWM5 190 625*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */ 626*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PWM6 191 627*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */ 628*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PWM7 192 629*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */ 630*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PWM8 193 631*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTE */ 632*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_UARTE 194 633*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTF */ 634*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_UARTF 195 635*c66ec88fSEmmanuel Vadot /** @deprecated */ 636*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_DBGAPB 196 637*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC */ 638*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_BPMP_CPU_NIC 197 639*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB */ 640*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_BPMP_APB 199 641*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by TEGRA186_CLK_SOC_ACTMON */ 642*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_ACTMON 201 643*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC */ 644*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_AON_CPU_NIC 208 645*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */ 646*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_CAN1 210 647*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_CAN1_HOST */ 648*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_CAN1_HOST 211 649*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */ 650*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_CAN2 212 651*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_CAN2_HOST */ 652*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_CAN2_HOST 213 653*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB */ 654*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_AON_APB 214 655*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTC */ 656*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_UARTC 215 657*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTG */ 658*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_UARTG 216 659*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL */ 660*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_AON_UART_FST_MIPI_CAL 217 661*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */ 662*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_I2C2 218 663*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */ 664*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_I2C8 219 665*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C10 */ 666*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_I2C10 220 667*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW */ 668*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_AON_I2C_SLOW 221 669*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI2 */ 670*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SPI2 222 671*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5 */ 672*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_DMIC5 223 673*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH */ 674*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_AON_TOUCH 224 675*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */ 676*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PWM4 225 677*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSC. This clock object is read only and is used for all timers in the system. */ 678*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_TSC 226 679*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT */ 680*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_MSS_ENCRYPT 227 681*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC */ 682*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SCE_CPU_NIC 228 683*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB */ 684*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SCE_APB 230 685*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_DSIC */ 686*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_DSIC 231 687*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP */ 688*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_DSIC_LP 232 689*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_DSID */ 690*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_DSID 233 691*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP */ 692*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_DSID_LP 234 693*c66ec88fSEmmanuel Vadot /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP */ 694*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PEX_SATA_USB_RX_BYP 236 695*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT */ 696*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SPDIF_OUT 238 697*c66ec88fSEmmanuel Vadot /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 */ 698*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_EQOS_PTP_REF 239 699*c66ec88fSEmmanuel Vadot /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK */ 700*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_EQOS_TX 240 701*c66ec88fSEmmanuel Vadot /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK */ 702*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_USB2_HSIC_TRK 241 703*c66ec88fSEmmanuel Vadot /** @brief output of mux xusb_ss_clk_switch on page 66 of T186_Clocks_IAS.doc */ 704*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_XUSB_CORE_SS 242 705*c66ec88fSEmmanuel Vadot /** @brief output of mux xusb_core_dev_clk_switch on page 67 of T186_Clocks_IAS.doc */ 706*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_XUSB_CORE_DEV 243 707*c66ec88fSEmmanuel Vadot /** @brief output of mux xusb_core_falcon_clk_switch on page 67 of T186_Clocks_IAS.doc */ 708*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_XUSB_FALCON 244 709*c66ec88fSEmmanuel Vadot /** @brief output of mux xusb_fs_clk_switch on page 66 of T186_Clocks_IAS.doc */ 710*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_XUSB_FS 245 711*c66ec88fSEmmanuel Vadot /** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */ 712*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLL_A_OUT0 246 713*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */ 714*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SYNC_I2S1 247 715*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */ 716*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SYNC_I2S2 248 717*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */ 718*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SYNC_I2S3 249 719*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */ 720*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SYNC_I2S4 250 721*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */ 722*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SYNC_I2S5 251 723*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */ 724*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SYNC_I2S6 252 725*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */ 726*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SYNC_DSPK1 253 727*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */ 728*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SYNC_DSPK2 254 729*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */ 730*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SYNC_DMIC1 255 731*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */ 732*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SYNC_DMIC2 256 733*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */ 734*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SYNC_DMIC3 257 735*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */ 736*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SYNC_DMIC4 259 737*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF */ 738*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SYNC_SPDIF 260 739*c66ec88fSEmmanuel Vadot /** @brief output of gate CLK_ENB_PLLREFE_OUT */ 740*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLREFE_OUT_GATED 261 741*c66ec88fSEmmanuel Vadot /** @brief output of the divider PLLREFE_DIVP in CLK_RST_CONTROLLER_PLLREFE_BASE. PLLREFE has 2 outputs: 742*c66ec88fSEmmanuel Vadot * * VCO/pdiv defined by this clock object 743*c66ec88fSEmmanuel Vadot * * VCO/2 defined by TEGRA186_CLK_PLLREFE_OUT 744*c66ec88fSEmmanuel Vadot */ 745*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLREFE_OUT1 262 746*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLD_OUT1 267 747*c66ec88fSEmmanuel Vadot /** @brief output of the divider PLLP_DIVP in CLK_RST_CONTROLLER_PLLP_BASE */ 748*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLP_OUT0 269 749*c66ec88fSEmmanuel Vadot /** @brief output of the divider CLK_RST_CONTROLLER_PLLP_OUTC */ 750*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLP_OUT5 270 751*c66ec88fSEmmanuel Vadot /** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */ 752*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLA 271 753*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by CLK_RST_CONTROLLER_ACLK_BURST_POLICY divided by the divider controlled by ACLK_CLK_DIVISOR in CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER */ 754*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_ACLK 273 755*c66ec88fSEmmanuel Vadot /** fixed 48MHz clock divided down from TEGRA186_CLK_PLL_U */ 756*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLL_U_48M 274 757*c66ec88fSEmmanuel Vadot /** fixed 480MHz clock divided down from TEGRA186_CLK_PLL_U */ 758*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLL_U_480M 275 759*c66ec88fSEmmanuel Vadot /** @brief output of the divider PLLC4_DIVP in CLK_RST_CONTROLLER_PLLC4_BASE. Output frequency is TEGRA186_CLK_PLLC4_VCO/PLLC4_DIVP */ 760*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLC4_OUT0 276 761*c66ec88fSEmmanuel Vadot /** fixed /3 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/3 */ 762*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLC4_OUT1 277 763*c66ec88fSEmmanuel Vadot /** fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/5 */ 764*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLC4_OUT2 278 765*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by PLLC4_CLK_SEL in CLK_RST_CONTROLLER_PLLC4_MISC1 */ 766*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLC4_OUT_MUX 279 767*c66ec88fSEmmanuel Vadot /** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when DFLLDISP_DIV is selected in NVDISPLAY_DISP_CLK_SRC */ 768*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_DFLLDISP_DIV 284 769*c66ec88fSEmmanuel Vadot /** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when PLLDISPHUB_DIV is selected in NVDISPLAY_DISP_CLK_SRC */ 770*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLDISPHUB_DIV 285 771*c66ec88fSEmmanuel Vadot /** fixed /8 divider which is used as the input for TEGRA186_CLK_SOR_SAFE */ 772*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLP_DIV8 286 773*c66ec88fSEmmanuel Vadot /** @brief output of divider CLK_RST_CONTROLLER_BPMP_NIC_RATE */ 774*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_BPMP_NIC 287 775*c66ec88fSEmmanuel Vadot /** @brief output of the divider CLK_RST_CONTROLLER_PLLA1_OUT1 */ 776*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLL_A_OUT1 288 777*c66ec88fSEmmanuel Vadot /** @deprecated */ 778*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_GPC2CLK 289 779*c66ec88fSEmmanuel Vadot /** A fake clock which must be enabled during KFUSE read operations to ensure adequate VDD_CORE voltage. */ 780*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_KFUSE 293 781*c66ec88fSEmmanuel Vadot /** 782*c66ec88fSEmmanuel Vadot * @brief controls the PLLE hardware sequencer. 783*c66ec88fSEmmanuel Vadot * @details This clock only has enable and disable methods. When the 784*c66ec88fSEmmanuel Vadot * PLLE hw sequencer is enabled, PLLE, will be enabled or disabled by 785*c66ec88fSEmmanuel Vadot * hw based on the control signals from the PCIe, SATA and XUSB 786*c66ec88fSEmmanuel Vadot * clocks. When the PLLE hw sequencer is disabled, the state of PLLE 787*c66ec88fSEmmanuel Vadot * is controlled by sw using clk_enable/clk_disable on 788*c66ec88fSEmmanuel Vadot * TEGRA186_CLK_PLLE. 789*c66ec88fSEmmanuel Vadot */ 790*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLE_PWRSEQ 294 791*c66ec88fSEmmanuel Vadot /** fixed 60MHz clock divided down from, TEGRA186_CLK_PLL_U */ 792*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLREFE_REF 295 793*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by SOR0_CLK_SEL0 and SOR0_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */ 794*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SOR0_OUT 296 795*c66ec88fSEmmanuel Vadot /** @brief output of mux controlled by SOR1_CLK_SEL0 and SOR1_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */ 796*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SOR1_OUT 297 797*c66ec88fSEmmanuel Vadot /** @brief fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLREFE_OUT1/5. Used as input for TEGRA186_CLK_EQOS_AXI */ 798*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLREFE_OUT1_DIV5 298 799*c66ec88fSEmmanuel Vadot /** @brief controls the UTMIP_PLL (aka PLLU) hardware sqeuencer */ 800*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_UTMIP_PLL_PWRSEQ 301 801*c66ec88fSEmmanuel Vadot /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT */ 802*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PEX_USB_PAD0_MGMT 302 803*c66ec88fSEmmanuel Vadot /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT */ 804*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PEX_USB_PAD1_MGMT 303 805*c66ec88fSEmmanuel Vadot /** @brief controls the UPHY_PLL0 hardware sqeuencer */ 806*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_UPHY_PLL0_PWRSEQ 304 807*c66ec88fSEmmanuel Vadot /** @brief controls the UPHY_PLL1 hardware sqeuencer */ 808*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_UPHY_PLL1_PWRSEQ 305 809*c66ec88fSEmmanuel Vadot /** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC so the bypass output even be used when the PLL is disabled */ 810*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH 306 811*c66ec88fSEmmanuel Vadot /** @brief output of the mux controlled by PLLREFE_SEL_CLKIN_PEX in CLK_RST_CONTROLLER_PLLREFE_MISC */ 812*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLREFE_PEX 307 813*c66ec88fSEmmanuel Vadot /** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC to turn on the PLL when enabled */ 814*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLREFE_IDDQ 308 815*c66ec88fSEmmanuel Vadot /** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */ 816*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_QSPI_OUT 309 817*c66ec88fSEmmanuel Vadot /** 818*c66ec88fSEmmanuel Vadot * @brief GPC2CLK-div-2 819*c66ec88fSEmmanuel Vadot * @details fixed /2 divider. Output frequency is 820*c66ec88fSEmmanuel Vadot * TEGRA186_CLK_GPC2CLK/2. The frequency of this clock is the 821*c66ec88fSEmmanuel Vadot * frequency at which the GPU graphics engine runs. */ 822*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_GPCCLK 310 823*c66ec88fSEmmanuel Vadot /** @brief output of divider CLK_RST_CONTROLLER_AON_NIC_RATE */ 824*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_AON_NIC 450 825*c66ec88fSEmmanuel Vadot /** @brief output of divider CLK_RST_CONTROLLER_SCE_NIC_RATE */ 826*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SCE_NIC 451 827*c66ec88fSEmmanuel Vadot /** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */ 828*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLE 512 829*c66ec88fSEmmanuel Vadot /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC_BASE */ 830*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLC 513 831*c66ec88fSEmmanuel Vadot /** Fixed 408MHz PLL for use by peripheral clocks */ 832*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLP 516 833*c66ec88fSEmmanuel Vadot /** @deprecated */ 834*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLL_P TEGRA186_CLK_PLLP 835*c66ec88fSEmmanuel Vadot /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD_BASE for use by DSI */ 836*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLD 518 837*c66ec88fSEmmanuel Vadot /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD2_BASE for use by HDMI or DP */ 838*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLD2 519 839*c66ec88fSEmmanuel Vadot /** 840*c66ec88fSEmmanuel Vadot * @brief PLL controlled by CLK_RST_CONTROLLER_PLLREFE_BASE. 841*c66ec88fSEmmanuel Vadot * @details Note that this clock only controls the VCO output, before 842*c66ec88fSEmmanuel Vadot * the post-divider. See TEGRA186_CLK_PLLREFE_OUT1 for more 843*c66ec88fSEmmanuel Vadot * information. 844*c66ec88fSEmmanuel Vadot */ 845*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLREFE_VCO 520 846*c66ec88fSEmmanuel Vadot /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC2_BASE */ 847*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLC2 521 848*c66ec88fSEmmanuel Vadot /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC3_BASE */ 849*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLC3 522 850*c66ec88fSEmmanuel Vadot /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDP_BASE for use as the DP link clock */ 851*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLDP 523 852*c66ec88fSEmmanuel Vadot /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */ 853*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLC4_VCO 524 854*c66ec88fSEmmanuel Vadot /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLA1_BASE for use by audio clocks */ 855*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLA1 525 856*c66ec88fSEmmanuel Vadot /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVCSI_BASE */ 857*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLNVCSI 526 858*c66ec88fSEmmanuel Vadot /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDISPHUB_BASE */ 859*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLDISPHUB 527 860*c66ec88fSEmmanuel Vadot /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD3_BASE for use by HDMI or DP */ 861*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLD3 528 862*c66ec88fSEmmanuel Vadot /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLBPMPCAM_BASE */ 863*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLBPMPCAM 531 864*c66ec88fSEmmanuel Vadot /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLAON_BASE for use by IP blocks in the AON domain */ 865*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLAON 532 866*c66ec88fSEmmanuel Vadot /** Fixed frequency 960MHz PLL for USB and EAVB */ 867*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLU 533 868*c66ec88fSEmmanuel Vadot /** fixed /2 divider. Output frequency is TEGRA186_CLK_PLLC4_VCO/2 */ 869*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLLC4_VCO_DIV2 535 870*c66ec88fSEmmanuel Vadot /** @brief NAFLL clock source for AXI_CBB */ 871*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_NAFLL_AXI_CBB 564 872*c66ec88fSEmmanuel Vadot /** @brief NAFLL clock source for BPMP */ 873*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_NAFLL_BPMP 565 874*c66ec88fSEmmanuel Vadot /** @brief NAFLL clock source for ISP */ 875*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_NAFLL_ISP 566 876*c66ec88fSEmmanuel Vadot /** @brief NAFLL clock source for NVDEC */ 877*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_NAFLL_NVDEC 567 878*c66ec88fSEmmanuel Vadot /** @brief NAFLL clock source for NVENC */ 879*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_NAFLL_NVENC 568 880*c66ec88fSEmmanuel Vadot /** @brief NAFLL clock source for NVJPG */ 881*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_NAFLL_NVJPG 569 882*c66ec88fSEmmanuel Vadot /** @brief NAFLL clock source for SCE */ 883*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_NAFLL_SCE 570 884*c66ec88fSEmmanuel Vadot /** @brief NAFLL clock source for SE */ 885*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_NAFLL_SE 571 886*c66ec88fSEmmanuel Vadot /** @brief NAFLL clock source for TSEC */ 887*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_NAFLL_TSEC 572 888*c66ec88fSEmmanuel Vadot /** @brief NAFLL clock source for TSECB */ 889*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_NAFLL_TSECB 573 890*c66ec88fSEmmanuel Vadot /** @brief NAFLL clock source for VI */ 891*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_NAFLL_VI 574 892*c66ec88fSEmmanuel Vadot /** @brief NAFLL clock source for VIC */ 893*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_NAFLL_VIC 575 894*c66ec88fSEmmanuel Vadot /** @brief NAFLL clock source for DISP */ 895*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_NAFLL_DISP 576 896*c66ec88fSEmmanuel Vadot /** @brief NAFLL clock source for GPU */ 897*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_NAFLL_GPU 577 898*c66ec88fSEmmanuel Vadot /** @brief NAFLL clock source for M-CPU cluster */ 899*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_NAFLL_MCPU 578 900*c66ec88fSEmmanuel Vadot /** @brief NAFLL clock source for B-CPU cluster */ 901*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_NAFLL_BCPU 579 902*c66ec88fSEmmanuel Vadot /** @brief input from Tegra's CLK_32K_IN pad */ 903*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_CLK_32K 608 904*c66ec88fSEmmanuel Vadot /** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */ 905*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_CLK_M 609 906*c66ec88fSEmmanuel Vadot /** @brief output of divider PLL_REF_DIV in CLK_RST_CONTROLLER_OSC_CTRL */ 907*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_PLL_REF 610 908*c66ec88fSEmmanuel Vadot /** @brief input from Tegra's XTAL_IN */ 909*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_OSC 612 910*c66ec88fSEmmanuel Vadot /** @brief clock recovered from EAVB input */ 911*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_EQOS_RX_INPUT 613 912*c66ec88fSEmmanuel Vadot /** @brief clock recovered from DTV input */ 913*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_DTV_INPUT 614 914*c66ec88fSEmmanuel Vadot /** @brief SOR0 brick output which feeds into SOR0_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0*/ 915*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SOR0_PAD_CLKOUT 615 916*c66ec88fSEmmanuel Vadot /** @brief SOR1 brick output which feeds into SOR1_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1*/ 917*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SOR1_PAD_CLKOUT 616 918*c66ec88fSEmmanuel Vadot /** @brief clock recovered from I2S1 input */ 919*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_I2S1_SYNC_INPUT 617 920*c66ec88fSEmmanuel Vadot /** @brief clock recovered from I2S2 input */ 921*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_I2S2_SYNC_INPUT 618 922*c66ec88fSEmmanuel Vadot /** @brief clock recovered from I2S3 input */ 923*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_I2S3_SYNC_INPUT 619 924*c66ec88fSEmmanuel Vadot /** @brief clock recovered from I2S4 input */ 925*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_I2S4_SYNC_INPUT 620 926*c66ec88fSEmmanuel Vadot /** @brief clock recovered from I2S5 input */ 927*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_I2S5_SYNC_INPUT 621 928*c66ec88fSEmmanuel Vadot /** @brief clock recovered from I2S6 input */ 929*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_I2S6_SYNC_INPUT 622 930*c66ec88fSEmmanuel Vadot /** @brief clock recovered from SPDIFIN input */ 931*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_SPDIFIN_SYNC_INPUT 623 932*c66ec88fSEmmanuel Vadot 933*c66ec88fSEmmanuel Vadot /** 934*c66ec88fSEmmanuel Vadot * @brief subject to change 935*c66ec88fSEmmanuel Vadot * @details maximum clock identifier value plus one. 936*c66ec88fSEmmanuel Vadot */ 937*c66ec88fSEmmanuel Vadot #define TEGRA186_CLK_CLK_MAX 624 938*c66ec88fSEmmanuel Vadot 939*c66ec88fSEmmanuel Vadot /** @} */ 940*c66ec88fSEmmanuel Vadot 941*c66ec88fSEmmanuel Vadot #endif 942