1*c66ec88fSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0-only */ 2*c66ec88fSEmmanuel Vadot /* 3*c66ec88fSEmmanuel Vadot * This header provides macros for at91 dma bindings. 4*c66ec88fSEmmanuel Vadot * 5*c66ec88fSEmmanuel Vadot * Copyright (C) 2013 Ludovic Desroches <ludovic.desroches@atmel.com> 6*c66ec88fSEmmanuel Vadot */ 7*c66ec88fSEmmanuel Vadot 8*c66ec88fSEmmanuel Vadot #ifndef __DT_BINDINGS_AT91_DMA_H__ 9*c66ec88fSEmmanuel Vadot #define __DT_BINDINGS_AT91_DMA_H__ 10*c66ec88fSEmmanuel Vadot 11*c66ec88fSEmmanuel Vadot /* ---------- HDMAC ---------- */ 12*c66ec88fSEmmanuel Vadot 13*c66ec88fSEmmanuel Vadot /* 14*c66ec88fSEmmanuel Vadot * Source and/or destination peripheral ID 15*c66ec88fSEmmanuel Vadot */ 16*c66ec88fSEmmanuel Vadot #define AT91_DMA_CFG_PER_ID_MASK (0xff) 17*c66ec88fSEmmanuel Vadot #define AT91_DMA_CFG_PER_ID(id) (id & AT91_DMA_CFG_PER_ID_MASK) 18*c66ec88fSEmmanuel Vadot 19*c66ec88fSEmmanuel Vadot /* 20*c66ec88fSEmmanuel Vadot * FIFO configuration: it defines when a request is serviced. 21*c66ec88fSEmmanuel Vadot */ 22*c66ec88fSEmmanuel Vadot #define AT91_DMA_CFG_FIFOCFG_OFFSET (8) 23*c66ec88fSEmmanuel Vadot #define AT91_DMA_CFG_FIFOCFG_MASK (0xf << AT91_DMA_CFG_FIFOCFG_OFFSET) 24*c66ec88fSEmmanuel Vadot #define AT91_DMA_CFG_FIFOCFG_HALF (0x0 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* half FIFO (default behavior) */ 25*c66ec88fSEmmanuel Vadot #define AT91_DMA_CFG_FIFOCFG_ALAP (0x1 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* largest defined AHB burst */ 26*c66ec88fSEmmanuel Vadot #define AT91_DMA_CFG_FIFOCFG_ASAP (0x2 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* single AHB access */ 27*c66ec88fSEmmanuel Vadot 28*c66ec88fSEmmanuel Vadot 29*c66ec88fSEmmanuel Vadot /* ---------- XDMAC ---------- */ 30*c66ec88fSEmmanuel Vadot #define AT91_XDMAC_DT_MEM_IF_MASK (0x1) 31*c66ec88fSEmmanuel Vadot #define AT91_XDMAC_DT_MEM_IF_OFFSET (13) 32*c66ec88fSEmmanuel Vadot #define AT91_XDMAC_DT_MEM_IF(mem_if) (((mem_if) & AT91_XDMAC_DT_MEM_IF_MASK) \ 33*c66ec88fSEmmanuel Vadot << AT91_XDMAC_DT_MEM_IF_OFFSET) 34*c66ec88fSEmmanuel Vadot #define AT91_XDMAC_DT_GET_MEM_IF(cfg) (((cfg) >> AT91_XDMAC_DT_MEM_IF_OFFSET) \ 35*c66ec88fSEmmanuel Vadot & AT91_XDMAC_DT_MEM_IF_MASK) 36*c66ec88fSEmmanuel Vadot 37*c66ec88fSEmmanuel Vadot #define AT91_XDMAC_DT_PER_IF_MASK (0x1) 38*c66ec88fSEmmanuel Vadot #define AT91_XDMAC_DT_PER_IF_OFFSET (14) 39*c66ec88fSEmmanuel Vadot #define AT91_XDMAC_DT_PER_IF(per_if) (((per_if) & AT91_XDMAC_DT_PER_IF_MASK) \ 40*c66ec88fSEmmanuel Vadot << AT91_XDMAC_DT_PER_IF_OFFSET) 41*c66ec88fSEmmanuel Vadot #define AT91_XDMAC_DT_GET_PER_IF(cfg) (((cfg) >> AT91_XDMAC_DT_PER_IF_OFFSET) \ 42*c66ec88fSEmmanuel Vadot & AT91_XDMAC_DT_PER_IF_MASK) 43*c66ec88fSEmmanuel Vadot 44*c66ec88fSEmmanuel Vadot #define AT91_XDMAC_DT_PERID_MASK (0x7f) 45*c66ec88fSEmmanuel Vadot #define AT91_XDMAC_DT_PERID_OFFSET (24) 46*c66ec88fSEmmanuel Vadot #define AT91_XDMAC_DT_PERID(perid) (((perid) & AT91_XDMAC_DT_PERID_MASK) \ 47*c66ec88fSEmmanuel Vadot << AT91_XDMAC_DT_PERID_OFFSET) 48*c66ec88fSEmmanuel Vadot #define AT91_XDMAC_DT_GET_PERID(cfg) (((cfg) >> AT91_XDMAC_DT_PERID_OFFSET) \ 49*c66ec88fSEmmanuel Vadot & AT91_XDMAC_DT_PERID_MASK) 50*c66ec88fSEmmanuel Vadot 51*c66ec88fSEmmanuel Vadot #endif /* __DT_BINDINGS_AT91_DMA_H__ */ 52