1c66ec88fSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0-only */ 2c66ec88fSEmmanuel Vadot /* 3c66ec88fSEmmanuel Vadot * Copyright (c) 2015 MediaTek Inc. 4c66ec88fSEmmanuel Vadot * Author: Honghui Zhang <honghui.zhang@mediatek.com> 5c66ec88fSEmmanuel Vadot */ 6c66ec88fSEmmanuel Vadot 7*5def4c47SEmmanuel Vadot #ifndef _DT_BINDINGS_MEMORY_MT2701_LARB_PORT_H_ 8*5def4c47SEmmanuel Vadot #define _DT_BINDINGS_MEMORY_MT2701_LARB_PORT_H_ 9c66ec88fSEmmanuel Vadot 10c66ec88fSEmmanuel Vadot /* 11c66ec88fSEmmanuel Vadot * Mediatek m4u generation 1 such as mt2701 has flat m4u port numbers, 12c66ec88fSEmmanuel Vadot * the first port's id for larb[N] would be the last port's id of larb[N - 1] 13c66ec88fSEmmanuel Vadot * plus one while larb[0]'s first port number is 0. The definition of 14c66ec88fSEmmanuel Vadot * MT2701_M4U_ID_LARBx is following HW register spec. 15c66ec88fSEmmanuel Vadot * But m4u generation 2 like mt8173 have different port number, it use fixed 16c66ec88fSEmmanuel Vadot * offset for each larb, the first port's id for larb[N] would be (N * 32). 17c66ec88fSEmmanuel Vadot */ 18c66ec88fSEmmanuel Vadot #define LARB0_PORT_OFFSET 0 19c66ec88fSEmmanuel Vadot #define LARB1_PORT_OFFSET 11 20c66ec88fSEmmanuel Vadot #define LARB2_PORT_OFFSET 21 21c66ec88fSEmmanuel Vadot #define LARB3_PORT_OFFSET 44 22c66ec88fSEmmanuel Vadot 23c66ec88fSEmmanuel Vadot #define MT2701_M4U_ID_LARB0(port) ((port) + LARB0_PORT_OFFSET) 24c66ec88fSEmmanuel Vadot #define MT2701_M4U_ID_LARB1(port) ((port) + LARB1_PORT_OFFSET) 25c66ec88fSEmmanuel Vadot #define MT2701_M4U_ID_LARB2(port) ((port) + LARB2_PORT_OFFSET) 26c66ec88fSEmmanuel Vadot 27c66ec88fSEmmanuel Vadot /* Port define for larb0 */ 28c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_DISP_OVL_0 MT2701_M4U_ID_LARB0(0) 29c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_DISP_RDMA1 MT2701_M4U_ID_LARB0(1) 30c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_DISP_RDMA MT2701_M4U_ID_LARB0(2) 31c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_DISP_WDMA MT2701_M4U_ID_LARB0(3) 32c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_MM_CMDQ MT2701_M4U_ID_LARB0(4) 33c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_MDP_RDMA MT2701_M4U_ID_LARB0(5) 34c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_MDP_WDMA MT2701_M4U_ID_LARB0(6) 35c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_MDP_ROTO MT2701_M4U_ID_LARB0(7) 36c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_MDP_ROTCO MT2701_M4U_ID_LARB0(8) 37c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_MDP_ROTVO MT2701_M4U_ID_LARB0(9) 38c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_MDP_RDMA1 MT2701_M4U_ID_LARB0(10) 39c66ec88fSEmmanuel Vadot 40c66ec88fSEmmanuel Vadot /* Port define for larb1 */ 41c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_VDEC_MC_EXT MT2701_M4U_ID_LARB1(0) 42c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_VDEC_PP_EXT MT2701_M4U_ID_LARB1(1) 43c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_VDEC_PPWRAP_EXT MT2701_M4U_ID_LARB1(2) 44c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_VDEC_AVC_MV_EXT MT2701_M4U_ID_LARB1(3) 45c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_VDEC_PRED_RD_EXT MT2701_M4U_ID_LARB1(4) 46c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_VDEC_PRED_WR_EXT MT2701_M4U_ID_LARB1(5) 47c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_VDEC_VLD_EXT MT2701_M4U_ID_LARB1(6) 48c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_VDEC_VLD2_EXT MT2701_M4U_ID_LARB1(7) 49c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_VDEC_TILE_EXT MT2701_M4U_ID_LARB1(8) 50c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_VDEC_IMG_RESZ_EXT MT2701_M4U_ID_LARB1(9) 51c66ec88fSEmmanuel Vadot 52c66ec88fSEmmanuel Vadot /* Port define for larb2 */ 53c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_VENC_RCPU MT2701_M4U_ID_LARB2(0) 54c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_VENC_REC_FRM MT2701_M4U_ID_LARB2(1) 55c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_VENC_BSDMA MT2701_M4U_ID_LARB2(2) 56c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_JPGENC_RDMA MT2701_M4U_ID_LARB2(3) 57c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_VENC_LT_RCPU MT2701_M4U_ID_LARB2(4) 58c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_VENC_LT_REC_FRM MT2701_M4U_ID_LARB2(5) 59c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_VENC_LT_BSDMA MT2701_M4U_ID_LARB2(6) 60c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_JPGDEC_BSDMA MT2701_M4U_ID_LARB2(7) 61c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_VENC_SV_COMV MT2701_M4U_ID_LARB2(8) 62c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_VENC_RD_COMV MT2701_M4U_ID_LARB2(9) 63c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_JPGENC_BSDMA MT2701_M4U_ID_LARB2(10) 64c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_VENC_CUR_LUMA MT2701_M4U_ID_LARB2(11) 65c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_VENC_CUR_CHROMA MT2701_M4U_ID_LARB2(12) 66c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_VENC_REF_LUMA MT2701_M4U_ID_LARB2(13) 67c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_VENC_REF_CHROMA MT2701_M4U_ID_LARB2(14) 68c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_IMG_RESZ MT2701_M4U_ID_LARB2(15) 69c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_VENC_LT_SV_COMV MT2701_M4U_ID_LARB2(16) 70c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_VENC_LT_RD_COMV MT2701_M4U_ID_LARB2(17) 71c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_VENC_LT_CUR_LUMA MT2701_M4U_ID_LARB2(18) 72c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_VENC_LT_CUR_CHROMA MT2701_M4U_ID_LARB2(19) 73c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_VENC_LT_REF_LUMA MT2701_M4U_ID_LARB2(20) 74c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_VENC_LT_REF_CHROMA MT2701_M4U_ID_LARB2(21) 75c66ec88fSEmmanuel Vadot #define MT2701_M4U_PORT_JPGDEC_WDMA MT2701_M4U_ID_LARB2(22) 76c66ec88fSEmmanuel Vadot 77c66ec88fSEmmanuel Vadot #endif 78