1c66ec88fSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0-only */ 2c66ec88fSEmmanuel Vadot /* 3c66ec88fSEmmanuel Vadot * Copyright (c) 2015-2016 MediaTek Inc. 4c66ec88fSEmmanuel Vadot * Author: Yong Wu <yong.wu@mediatek.com> 5c66ec88fSEmmanuel Vadot */ 6*5def4c47SEmmanuel Vadot #ifndef _DT_BINDINGS_MEMORY_MT8173_LARB_PORT_H_ 7*5def4c47SEmmanuel Vadot #define _DT_BINDINGS_MEMORY_MT8173_LARB_PORT_H_ 8c66ec88fSEmmanuel Vadot 9*5def4c47SEmmanuel Vadot #include <dt-bindings/memory/mtk-memory-port.h> 10c66ec88fSEmmanuel Vadot 11c66ec88fSEmmanuel Vadot #define M4U_LARB0_ID 0 12c66ec88fSEmmanuel Vadot #define M4U_LARB1_ID 1 13c66ec88fSEmmanuel Vadot #define M4U_LARB2_ID 2 14c66ec88fSEmmanuel Vadot #define M4U_LARB3_ID 3 15c66ec88fSEmmanuel Vadot #define M4U_LARB4_ID 4 16c66ec88fSEmmanuel Vadot #define M4U_LARB5_ID 5 17c66ec88fSEmmanuel Vadot 18c66ec88fSEmmanuel Vadot /* larb0 */ 19c66ec88fSEmmanuel Vadot #define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) 20c66ec88fSEmmanuel Vadot #define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1) 21c66ec88fSEmmanuel Vadot #define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2) 22c66ec88fSEmmanuel Vadot #define M4U_PORT_DISP_OD_R MTK_M4U_ID(M4U_LARB0_ID, 3) 23c66ec88fSEmmanuel Vadot #define M4U_PORT_DISP_OD_W MTK_M4U_ID(M4U_LARB0_ID, 4) 24c66ec88fSEmmanuel Vadot #define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5) 25c66ec88fSEmmanuel Vadot #define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 6) 26c66ec88fSEmmanuel Vadot #define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 7) 27c66ec88fSEmmanuel Vadot 28c66ec88fSEmmanuel Vadot /* larb1 */ 29c66ec88fSEmmanuel Vadot #define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB1_ID, 0) 30c66ec88fSEmmanuel Vadot #define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB1_ID, 1) 31c66ec88fSEmmanuel Vadot #define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB1_ID, 2) 32c66ec88fSEmmanuel Vadot #define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB1_ID, 3) 33c66ec88fSEmmanuel Vadot #define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB1_ID, 4) 34c66ec88fSEmmanuel Vadot #define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB1_ID, 5) 35c66ec88fSEmmanuel Vadot #define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB1_ID, 6) 36c66ec88fSEmmanuel Vadot #define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB1_ID, 7) 37c66ec88fSEmmanuel Vadot #define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB1_ID, 8) 38c66ec88fSEmmanuel Vadot #define M4U_PORT_HW_VDEC_TILE MTK_M4U_ID(M4U_LARB1_ID, 9) 39c66ec88fSEmmanuel Vadot 40c66ec88fSEmmanuel Vadot /* larb2 */ 41c66ec88fSEmmanuel Vadot #define M4U_PORT_IMGO MTK_M4U_ID(M4U_LARB2_ID, 0) 42c66ec88fSEmmanuel Vadot #define M4U_PORT_RRZO MTK_M4U_ID(M4U_LARB2_ID, 1) 43c66ec88fSEmmanuel Vadot #define M4U_PORT_AAO MTK_M4U_ID(M4U_LARB2_ID, 2) 44c66ec88fSEmmanuel Vadot #define M4U_PORT_LCSO MTK_M4U_ID(M4U_LARB2_ID, 3) 45c66ec88fSEmmanuel Vadot #define M4U_PORT_ESFKO MTK_M4U_ID(M4U_LARB2_ID, 4) 46c66ec88fSEmmanuel Vadot #define M4U_PORT_IMGO_D MTK_M4U_ID(M4U_LARB2_ID, 5) 47c66ec88fSEmmanuel Vadot #define M4U_PORT_LSCI MTK_M4U_ID(M4U_LARB2_ID, 6) 48c66ec88fSEmmanuel Vadot #define M4U_PORT_LSCI_D MTK_M4U_ID(M4U_LARB2_ID, 7) 49c66ec88fSEmmanuel Vadot #define M4U_PORT_BPCI MTK_M4U_ID(M4U_LARB2_ID, 8) 50c66ec88fSEmmanuel Vadot #define M4U_PORT_BPCI_D MTK_M4U_ID(M4U_LARB2_ID, 9) 51c66ec88fSEmmanuel Vadot #define M4U_PORT_UFDI MTK_M4U_ID(M4U_LARB2_ID, 10) 52c66ec88fSEmmanuel Vadot #define M4U_PORT_IMGI MTK_M4U_ID(M4U_LARB2_ID, 11) 53c66ec88fSEmmanuel Vadot #define M4U_PORT_IMG2O MTK_M4U_ID(M4U_LARB2_ID, 12) 54c66ec88fSEmmanuel Vadot #define M4U_PORT_IMG3O MTK_M4U_ID(M4U_LARB2_ID, 13) 55c66ec88fSEmmanuel Vadot #define M4U_PORT_VIPI MTK_M4U_ID(M4U_LARB2_ID, 14) 56c66ec88fSEmmanuel Vadot #define M4U_PORT_VIP2I MTK_M4U_ID(M4U_LARB2_ID, 15) 57c66ec88fSEmmanuel Vadot #define M4U_PORT_VIP3I MTK_M4U_ID(M4U_LARB2_ID, 16) 58c66ec88fSEmmanuel Vadot #define M4U_PORT_LCEI MTK_M4U_ID(M4U_LARB2_ID, 17) 59c66ec88fSEmmanuel Vadot #define M4U_PORT_RB MTK_M4U_ID(M4U_LARB2_ID, 18) 60c66ec88fSEmmanuel Vadot #define M4U_PORT_RP MTK_M4U_ID(M4U_LARB2_ID, 19) 61c66ec88fSEmmanuel Vadot #define M4U_PORT_WR MTK_M4U_ID(M4U_LARB2_ID, 20) 62c66ec88fSEmmanuel Vadot 63c66ec88fSEmmanuel Vadot /* larb3 */ 64c66ec88fSEmmanuel Vadot #define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0) 65c66ec88fSEmmanuel Vadot #define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1) 66c66ec88fSEmmanuel Vadot #define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2) 67c66ec88fSEmmanuel Vadot #define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3) 68c66ec88fSEmmanuel Vadot #define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4) 69c66ec88fSEmmanuel Vadot #define M4U_PORT_JPGENC_RDMA MTK_M4U_ID(M4U_LARB3_ID, 5) 70c66ec88fSEmmanuel Vadot #define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 6) 71c66ec88fSEmmanuel Vadot #define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB3_ID, 7) 72c66ec88fSEmmanuel Vadot #define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 8) 73c66ec88fSEmmanuel Vadot #define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 9) 74c66ec88fSEmmanuel Vadot #define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 10) 75c66ec88fSEmmanuel Vadot #define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 11) 76c66ec88fSEmmanuel Vadot #define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 12) 77c66ec88fSEmmanuel Vadot #define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(M4U_LARB3_ID, 13) 78c66ec88fSEmmanuel Vadot #define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(M4U_LARB3_ID, 14) 79c66ec88fSEmmanuel Vadot 80c66ec88fSEmmanuel Vadot /* larb4 */ 81c66ec88fSEmmanuel Vadot #define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB4_ID, 0) 82c66ec88fSEmmanuel Vadot #define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 1) 83c66ec88fSEmmanuel Vadot #define M4U_PORT_DISP_RDMA2 MTK_M4U_ID(M4U_LARB4_ID, 2) 84c66ec88fSEmmanuel Vadot #define M4U_PORT_DISP_WDMA1 MTK_M4U_ID(M4U_LARB4_ID, 3) 85c66ec88fSEmmanuel Vadot #define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 4) 86c66ec88fSEmmanuel Vadot #define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB4_ID, 5) 87c66ec88fSEmmanuel Vadot 88c66ec88fSEmmanuel Vadot /* larb5 */ 89c66ec88fSEmmanuel Vadot #define M4U_PORT_VENC_RCPU_SET2 MTK_M4U_ID(M4U_LARB5_ID, 0) 90c66ec88fSEmmanuel Vadot #define M4U_PORT_VENC_REC_FRM_SET2 MTK_M4U_ID(M4U_LARB5_ID, 1) 91c66ec88fSEmmanuel Vadot #define M4U_PORT_VENC_REF_LUMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 2) 92c66ec88fSEmmanuel Vadot #define M4U_PORT_VENC_REC_CHROMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 3) 93c66ec88fSEmmanuel Vadot #define M4U_PORT_VENC_BSDMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 4) 94c66ec88fSEmmanuel Vadot #define M4U_PORT_VENC_CUR_LUMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 5) 95c66ec88fSEmmanuel Vadot #define M4U_PORT_VENC_CUR_CHROMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 6) 96c66ec88fSEmmanuel Vadot #define M4U_PORT_VENC_RD_COMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 7) 97c66ec88fSEmmanuel Vadot #define M4U_PORT_VENC_SV_COMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 8) 98c66ec88fSEmmanuel Vadot 99c66ec88fSEmmanuel Vadot #endif 100