1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * This header provides constants for SERDES MUX for TI SoCs
4  */
5 
6 #ifndef _DT_BINDINGS_MUX_TI_SERDES
7 #define _DT_BINDINGS_MUX_TI_SERDES
8 
9 /*
10  * These bindings are deprecated, because they do not match the actual
11  * concept of bindings but rather contain pure constants values used only
12  * in DTS board files.
13  * Instead include the header in the DTS source directory.
14  */
15 #warning "These bindings are deprecated. Instead, use the header in the DTS source directory."
16 
17 /* J721E */
18 
19 #define J721E_SERDES0_LANE0_QSGMII_LANE1	0x0
20 #define J721E_SERDES0_LANE0_PCIE0_LANE0		0x1
21 #define J721E_SERDES0_LANE0_USB3_0_SWAP		0x2
22 #define J721E_SERDES0_LANE0_IP4_UNUSED		0x3
23 
24 #define J721E_SERDES0_LANE1_QSGMII_LANE2	0x0
25 #define J721E_SERDES0_LANE1_PCIE0_LANE1		0x1
26 #define J721E_SERDES0_LANE1_USB3_0		0x2
27 #define J721E_SERDES0_LANE1_IP4_UNUSED		0x3
28 
29 #define J721E_SERDES1_LANE0_QSGMII_LANE3	0x0
30 #define J721E_SERDES1_LANE0_PCIE1_LANE0		0x1
31 #define J721E_SERDES1_LANE0_USB3_1_SWAP		0x2
32 #define J721E_SERDES1_LANE0_SGMII_LANE0		0x3
33 
34 #define J721E_SERDES1_LANE1_QSGMII_LANE4	0x0
35 #define J721E_SERDES1_LANE1_PCIE1_LANE1		0x1
36 #define J721E_SERDES1_LANE1_USB3_1		0x2
37 #define J721E_SERDES1_LANE1_SGMII_LANE1		0x3
38 
39 #define J721E_SERDES2_LANE0_IP1_UNUSED		0x0
40 #define J721E_SERDES2_LANE0_PCIE2_LANE0		0x1
41 #define J721E_SERDES2_LANE0_USB3_1_SWAP		0x2
42 #define J721E_SERDES2_LANE0_SGMII_LANE0		0x3
43 
44 #define J721E_SERDES2_LANE1_IP1_UNUSED		0x0
45 #define J721E_SERDES2_LANE1_PCIE2_LANE1		0x1
46 #define J721E_SERDES2_LANE1_USB3_1		0x2
47 #define J721E_SERDES2_LANE1_SGMII_LANE1		0x3
48 
49 #define J721E_SERDES3_LANE0_IP1_UNUSED		0x0
50 #define J721E_SERDES3_LANE0_PCIE3_LANE0		0x1
51 #define J721E_SERDES3_LANE0_USB3_0_SWAP		0x2
52 #define J721E_SERDES3_LANE0_IP4_UNUSED		0x3
53 
54 #define J721E_SERDES3_LANE1_IP1_UNUSED		0x0
55 #define J721E_SERDES3_LANE1_PCIE3_LANE1		0x1
56 #define J721E_SERDES3_LANE1_USB3_0		0x2
57 #define J721E_SERDES3_LANE1_IP4_UNUSED		0x3
58 
59 #define J721E_SERDES4_LANE0_EDP_LANE0		0x0
60 #define J721E_SERDES4_LANE0_IP2_UNUSED		0x1
61 #define J721E_SERDES4_LANE0_QSGMII_LANE5	0x2
62 #define J721E_SERDES4_LANE0_IP4_UNUSED		0x3
63 
64 #define J721E_SERDES4_LANE1_EDP_LANE1		0x0
65 #define J721E_SERDES4_LANE1_IP2_UNUSED		0x1
66 #define J721E_SERDES4_LANE1_QSGMII_LANE6	0x2
67 #define J721E_SERDES4_LANE1_IP4_UNUSED		0x3
68 
69 #define J721E_SERDES4_LANE2_EDP_LANE2		0x0
70 #define J721E_SERDES4_LANE2_IP2_UNUSED		0x1
71 #define J721E_SERDES4_LANE2_QSGMII_LANE7	0x2
72 #define J721E_SERDES4_LANE2_IP4_UNUSED		0x3
73 
74 #define J721E_SERDES4_LANE3_EDP_LANE3		0x0
75 #define J721E_SERDES4_LANE3_IP2_UNUSED		0x1
76 #define J721E_SERDES4_LANE3_QSGMII_LANE8	0x2
77 #define J721E_SERDES4_LANE3_IP4_UNUSED		0x3
78 
79 /* J7200 */
80 
81 #define J7200_SERDES0_LANE0_QSGMII_LANE3	0x0
82 #define J7200_SERDES0_LANE0_PCIE1_LANE0		0x1
83 #define J7200_SERDES0_LANE0_IP3_UNUSED		0x2
84 #define J7200_SERDES0_LANE0_IP4_UNUSED		0x3
85 
86 #define J7200_SERDES0_LANE1_QSGMII_LANE4	0x0
87 #define J7200_SERDES0_LANE1_PCIE1_LANE1		0x1
88 #define J7200_SERDES0_LANE1_IP3_UNUSED		0x2
89 #define J7200_SERDES0_LANE1_IP4_UNUSED		0x3
90 
91 #define J7200_SERDES0_LANE2_QSGMII_LANE1	0x0
92 #define J7200_SERDES0_LANE2_PCIE1_LANE2		0x1
93 #define J7200_SERDES0_LANE2_IP3_UNUSED		0x2
94 #define J7200_SERDES0_LANE2_IP4_UNUSED		0x3
95 
96 #define J7200_SERDES0_LANE3_QSGMII_LANE2	0x0
97 #define J7200_SERDES0_LANE3_PCIE1_LANE3		0x1
98 #define J7200_SERDES0_LANE3_USB			0x2
99 #define J7200_SERDES0_LANE3_IP4_UNUSED		0x3
100 
101 /* AM64 */
102 
103 #define AM64_SERDES0_LANE0_PCIE0		0x0
104 #define AM64_SERDES0_LANE0_USB			0x1
105 
106 /* J721S2 */
107 
108 #define J721S2_SERDES0_LANE0_EDP_LANE0		0x0
109 #define J721S2_SERDES0_LANE0_PCIE1_LANE0	0x1
110 #define J721S2_SERDES0_LANE0_IP3_UNUSED		0x2
111 #define J721S2_SERDES0_LANE0_IP4_UNUSED		0x3
112 
113 #define J721S2_SERDES0_LANE1_EDP_LANE1		0x0
114 #define J721S2_SERDES0_LANE1_PCIE1_LANE1	0x1
115 #define J721S2_SERDES0_LANE1_USB		0x2
116 #define J721S2_SERDES0_LANE1_IP4_UNUSED		0x3
117 
118 #define J721S2_SERDES0_LANE2_EDP_LANE2		0x0
119 #define J721S2_SERDES0_LANE2_PCIE1_LANE2	0x1
120 #define J721S2_SERDES0_LANE2_IP3_UNUSED		0x2
121 #define J721S2_SERDES0_LANE2_IP4_UNUSED		0x3
122 
123 #define J721S2_SERDES0_LANE3_EDP_LANE3		0x0
124 #define J721S2_SERDES0_LANE3_PCIE1_LANE3	0x1
125 #define J721S2_SERDES0_LANE3_USB		0x2
126 #define J721S2_SERDES0_LANE3_IP4_UNUSED		0x3
127 
128 /* J784S4 */
129 
130 #define J784S4_SERDES0_LANE0_IP1_UNUSED		0x0
131 #define J784S4_SERDES0_LANE0_PCIE1_LANE0	0x1
132 #define J784S4_SERDES0_LANE0_IP3_UNUSED		0x2
133 #define J784S4_SERDES0_LANE0_IP4_UNUSED		0x3
134 
135 #define J784S4_SERDES0_LANE1_IP1_UNUSED		0x0
136 #define J784S4_SERDES0_LANE1_PCIE1_LANE1	0x1
137 #define J784S4_SERDES0_LANE1_IP3_UNUSED		0x2
138 #define J784S4_SERDES0_LANE1_IP4_UNUSED		0x3
139 
140 #define J784S4_SERDES0_LANE2_PCIE3_LANE0	0x0
141 #define J784S4_SERDES0_LANE2_PCIE1_LANE2	0x1
142 #define J784S4_SERDES0_LANE2_IP3_UNUSED		0x2
143 #define J784S4_SERDES0_LANE2_IP4_UNUSED		0x3
144 
145 #define J784S4_SERDES0_LANE3_PCIE3_LANE1	0x0
146 #define J784S4_SERDES0_LANE3_PCIE1_LANE3	0x1
147 #define J784S4_SERDES0_LANE3_USB		0x2
148 #define J784S4_SERDES0_LANE3_IP4_UNUSED		0x3
149 
150 #define J784S4_SERDES1_LANE0_QSGMII_LANE3	0x0
151 #define J784S4_SERDES1_LANE0_PCIE0_LANE0	0x1
152 #define J784S4_SERDES1_LANE0_IP3_UNUSED		0x2
153 #define J784S4_SERDES1_LANE0_IP4_UNUSED		0x3
154 
155 #define J784S4_SERDES1_LANE1_QSGMII_LANE4	0x0
156 #define J784S4_SERDES1_LANE1_PCIE0_LANE1	0x1
157 #define J784S4_SERDES1_LANE1_IP3_UNUSED		0x2
158 #define J784S4_SERDES1_LANE1_IP4_UNUSED		0x3
159 
160 #define J784S4_SERDES1_LANE2_QSGMII_LANE1	0x0
161 #define J784S4_SERDES1_LANE2_PCIE0_LANE2	0x1
162 #define J784S4_SERDES1_LANE2_PCIE2_LANE0	0x2
163 #define J784S4_SERDES1_LANE2_IP4_UNUSED		0x3
164 
165 #define J784S4_SERDES1_LANE3_QSGMII_LANE2	0x0
166 #define J784S4_SERDES1_LANE3_PCIE0_LANE3	0x1
167 #define J784S4_SERDES1_LANE3_PCIE2_LANE1	0x2
168 #define J784S4_SERDES1_LANE3_IP4_UNUSED		0x3
169 
170 #define J784S4_SERDES2_LANE0_QSGMII_LANE5	0x0
171 #define J784S4_SERDES2_LANE0_IP2_UNUSED		0x1
172 #define J784S4_SERDES2_LANE0_IP3_UNUSED		0x2
173 #define J784S4_SERDES2_LANE0_IP4_UNUSED		0x3
174 
175 #define J784S4_SERDES2_LANE1_QSGMII_LANE6	0x0
176 #define J784S4_SERDES2_LANE1_IP2_UNUSED		0x1
177 #define J784S4_SERDES2_LANE1_IP3_UNUSED		0x2
178 #define J784S4_SERDES2_LANE1_IP4_UNUSED		0x3
179 
180 #define J784S4_SERDES2_LANE2_QSGMII_LANE7	0x0
181 #define J784S4_SERDES2_LANE2_QSGMII_LANE1	0x1
182 #define J784S4_SERDES2_LANE2_IP3_UNUSED		0x2
183 #define J784S4_SERDES2_LANE2_IP4_UNUSED		0x3
184 
185 #define J784S4_SERDES2_LANE3_QSGMII_LANE8	0x0
186 #define J784S4_SERDES2_LANE3_QSGMII_LANE2	0x1
187 #define J784S4_SERDES2_LANE3_IP3_UNUSED		0x2
188 #define J784S4_SERDES2_LANE3_IP4_UNUSED		0x3
189 
190 #endif /* _DT_BINDINGS_MUX_TI_SERDES */
191