1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Support for peripherals on the AXS10x mainboard
4 *
5 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
6 */
7
8/ {
9	aliases {
10		ethernet = &gmac;
11	};
12
13	axs10x_mb {
14		compatible = "simple-bus";
15		#address-cells = <1>;
16		#size-cells = <1>;
17		ranges = <0x00000000 0x0 0xe0000000 0x10000000>;
18		interrupt-parent = <&mb_intc>;
19
20		creg_rst: reset-controller@11220 {
21			compatible = "snps,axs10x-reset";
22			#reset-cells = <1>;
23			reg = <0x11220 0x4>;
24		};
25
26		i2sclk: i2sclk@100a0 {
27			compatible = "snps,axs10x-i2s-pll-clock";
28			reg = <0x100a0 0x10>;
29			clocks = <&i2spll_clk>;
30			#clock-cells = <0>;
31		};
32
33		clocks {
34			i2spll_clk: i2spll_clk {
35				compatible = "fixed-clock";
36				clock-frequency = <27000000>;
37				#clock-cells = <0>;
38			};
39
40			i2cclk: i2cclk {
41				compatible = "fixed-clock";
42				clock-frequency = <50000000>;
43				#clock-cells = <0>;
44			};
45
46			apbclk: apbclk {
47				compatible = "fixed-clock";
48				clock-frequency = <50000000>;
49				#clock-cells = <0>;
50			};
51
52			mmcclk: mmcclk {
53				compatible = "fixed-clock";
54				/*
55				 * DW sdio controller has external ciu clock divider
56				 * controlled via register in SDIO IP. It divides
57				 * sdio_ref_clk (which comes from CGU) by 16 for
58				 * default. So default mmcclk clock (which comes
59				 * to sdk_in) is 25000000 Hz.
60				 */
61				clock-frequency = <25000000>;
62				#clock-cells = <0>;
63			};
64		};
65
66		pguclk: pguclk@10080 {
67			compatible = "snps,axs10x-pgu-pll-clock";
68			reg = <0x10080 0x10>, <0x110 0x10>;
69			#clock-cells = <0>;
70			clocks = <&input_clk>;
71		};
72
73		gmac: ethernet@18000 {
74			#interrupt-cells = <1>;
75			compatible = "snps,dwmac";
76			reg = < 0x18000 0x2000 >;
77			interrupts = < 4 >;
78			interrupt-names = "macirq";
79			phy-mode = "rgmii";
80			snps,pbl = < 32 >;
81			snps,multicast-filter-bins = <256>;
82			clocks = <&apbclk>;
83			clock-names = "stmmaceth";
84			max-speed = <100>;
85			resets = <&creg_rst 5>;
86			reset-names = "stmmaceth";
87			mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
88		};
89
90		ehci@40000 {
91			compatible = "generic-ehci";
92			reg = < 0x40000 0x100 >;
93			interrupts = < 8 >;
94		};
95
96		ohci@60000 {
97			compatible = "generic-ohci";
98			reg = < 0x60000 0x100 >;
99			interrupts = < 8 >;
100		};
101
102		/*
103		 * According to DW Mobile Storage databook it is required
104		 * to use  "Hold Register" if card is enumerated in SDR12 or
105		 * SDR25 modes.
106		 *
107		 * Utilization of "Hold Register" is already implemented via
108		 * dw_mci_pltfm_prepare_command() which in its turn gets
109		 * used through dw_mci_drv_data->prepare_command call-back.
110		 * This call-back is used in Altera Socfpga platform and so
111		 * we may reuse it saying that we're compatible with their
112		 * "altr,socfpga-dw-mshc".
113		 *
114		 * Most probably "Hold Register" utilization is platform-
115		 * independent requirement which means that single unified
116		 * "snps,dw-mshc" should be enough for all users of DW MMC once
117		 * dw_mci_pltfm_prepare_command() is used in generic platform
118		 * code.
119		 */
120		mmc@15000 {
121			compatible = "altr,socfpga-dw-mshc";
122			reg = < 0x15000 0x400 >;
123			fifo-depth = < 16 >;
124			card-detect-delay = < 200 >;
125			clocks = <&apbclk>, <&mmcclk>;
126			clock-names = "biu", "ciu";
127			interrupts = < 7 >;
128			bus-width = < 4 >;
129		};
130
131		uart@20000 {
132			compatible = "snps,dw-apb-uart";
133			reg = <0x20000 0x100>;
134			clock-frequency = <33333333>;
135			interrupts = <17>;
136			baud = <115200>;
137			reg-shift = <2>;
138			reg-io-width = <4>;
139		};
140
141		uart@21000 {
142			compatible = "snps,dw-apb-uart";
143			reg = <0x21000 0x100>;
144			clock-frequency = <33333333>;
145			interrupts = <18>;
146			baud = <115200>;
147			reg-shift = <2>;
148			reg-io-width = <4>;
149		};
150
151		/* UART muxed with USB data port (ttyS3) */
152		uart@22000 {
153			compatible = "snps,dw-apb-uart";
154			reg = <0x22000 0x100>;
155			clock-frequency = <33333333>;
156			interrupts = <19>;
157			baud = <115200>;
158			reg-shift = <2>;
159			reg-io-width = <4>;
160		};
161
162		i2c@1d000 {
163			compatible = "snps,designware-i2c";
164			reg = <0x1d000 0x100>;
165			clock-frequency = <400000>;
166			clocks = <&i2cclk>;
167			interrupts = <14>;
168		};
169
170		i2s: i2s@1e000 {
171			compatible = "snps,designware-i2s";
172			reg = <0x1e000 0x100>;
173			clocks = <&i2sclk 0>;
174			clock-names = "i2sclk";
175			interrupts = <15>;
176			#sound-dai-cells = <0>;
177		};
178
179		i2c@1f000 {
180			compatible = "snps,designware-i2c";
181			#address-cells = <1>;
182			#size-cells = <0>;
183			reg = <0x1f000 0x100>;
184			clock-frequency = <400000>;
185			clocks = <&i2cclk>;
186			interrupts = <16>;
187
188			adv7511:adv7511@39{
189				compatible="adi,adv7511";
190				reg = <0x39>;
191				interrupts = <23>;
192				adi,input-depth = <8>;
193				adi,input-colorspace = "rgb";
194				adi,input-clock = "1x";
195				adi,clock-delay = <0x03>;
196				#sound-dai-cells = <0>;
197
198				ports {
199					#address-cells = <1>;
200					#size-cells = <0>;
201
202					/* RGB/YUV input */
203					port@0 {
204						reg = <0>;
205						adv7511_input:endpoint {
206						remote-endpoint = <&pgu_output>;
207						};
208					};
209
210					/* HDMI output */
211					port@1 {
212						reg = <1>;
213						adv7511_output: endpoint {
214							remote-endpoint = <&hdmi_connector_in>;
215						};
216					};
217				};
218			};
219
220			eeprom@54{
221				compatible = "atmel,24c01";
222				reg = <0x54>;
223				pagesize = <0x8>;
224			};
225
226			eeprom@57{
227				compatible = "atmel,24c04";
228				reg = <0x57>;
229				pagesize = <0x8>;
230			};
231		};
232
233		hdmi0: connector {
234			compatible = "hdmi-connector";
235			type = "a";
236			port {
237				hdmi_connector_in: endpoint {
238					remote-endpoint = <&adv7511_output>;
239				};
240			};
241		};
242
243		gpio0:gpio@13000 {
244			compatible = "snps,dw-apb-gpio";
245			reg = <0x13000 0x1000>;
246			#address-cells = <1>;
247			#size-cells = <0>;
248
249			gpio0_banka: gpio-controller@0 {
250				compatible = "snps,dw-apb-gpio-port";
251				gpio-controller;
252				#gpio-cells = <2>;
253				snps,nr-gpios = <32>;
254				reg = <0>;
255			};
256
257			gpio0_bankb: gpio-controller@1 {
258				compatible = "snps,dw-apb-gpio-port";
259				gpio-controller;
260				#gpio-cells = <2>;
261				snps,nr-gpios = <8>;
262				reg = <1>;
263			};
264
265			gpio0_bankc: gpio-controller@2 {
266				compatible = "snps,dw-apb-gpio-port";
267				gpio-controller;
268				#gpio-cells = <2>;
269				snps,nr-gpios = <8>;
270				reg = <2>;
271			};
272		};
273
274		gpio1:gpio@14000 {
275			compatible = "snps,dw-apb-gpio";
276			reg = <0x14000 0x1000>;
277			#address-cells = <1>;
278			#size-cells = <0>;
279
280			gpio1_banka: gpio-controller@0 {
281				compatible = "snps,dw-apb-gpio-port";
282				gpio-controller;
283				#gpio-cells = <2>;
284				snps,nr-gpios = <30>;
285				reg = <0>;
286			};
287
288			gpio1_bankb: gpio-controller@1 {
289				compatible = "snps,dw-apb-gpio-port";
290				gpio-controller;
291				#gpio-cells = <2>;
292				snps,nr-gpios = <10>;
293				reg = <1>;
294			};
295
296			gpio1_bankc: gpio-controller@2 {
297				compatible = "snps,dw-apb-gpio-port";
298				gpio-controller;
299				#gpio-cells = <2>;
300				snps,nr-gpios = <8>;
301				reg = <2>;
302			};
303		};
304
305		pgu@17000 {
306			compatible = "snps,arcpgu";
307			reg = <0x17000 0x400>;
308			clocks = <&pguclk>;
309			clock-names = "pxlclk";
310			memory-region = <&frame_buffer>;
311			port {
312				pgu_output: endpoint {
313					remote-endpoint = <&adv7511_input>;
314				};
315			};
316		};
317
318		sound_playback {
319			compatible = "simple-audio-card";
320			simple-audio-card,name = "AXS10x HDMI Audio";
321			simple-audio-card,format = "i2s";
322			simple-audio-card,cpu {
323				sound-dai = <&i2s>;
324			};
325			simple-audio-card,codec {
326				sound-dai = <&adv7511>;
327			};
328		};
329	};
330};
331