1*f126890aSEmmanuel Vadot/* 2*f126890aSEmmanuel Vadot * Copyright 2016 Linaro Ltd 3*f126890aSEmmanuel Vadot * 4*f126890aSEmmanuel Vadot * Permission is hereby granted, free of charge, to any person obtaining a copy 5*f126890aSEmmanuel Vadot * of this software and associated documentation files (the "Software"), to deal 6*f126890aSEmmanuel Vadot * in the Software without restriction, including without limitation the rights 7*f126890aSEmmanuel Vadot * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8*f126890aSEmmanuel Vadot * copies of the Software, and to permit persons to whom the Software is 9*f126890aSEmmanuel Vadot * furnished to do so, subject to the following conditions: 10*f126890aSEmmanuel Vadot * 11*f126890aSEmmanuel Vadot * The above copyright notice and this permission notice shall be included in 12*f126890aSEmmanuel Vadot * all copies or substantial portions of the Software. 13*f126890aSEmmanuel Vadot * 14*f126890aSEmmanuel Vadot * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*f126890aSEmmanuel Vadot * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*f126890aSEmmanuel Vadot * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*f126890aSEmmanuel Vadot * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18*f126890aSEmmanuel Vadot * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19*f126890aSEmmanuel Vadot * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 20*f126890aSEmmanuel Vadot * THE SOFTWARE. 21*f126890aSEmmanuel Vadot */ 22*f126890aSEmmanuel Vadot 23*f126890aSEmmanuel Vadot#include <dt-bindings/interrupt-controller/irq.h> 24*f126890aSEmmanuel Vadot#include <dt-bindings/gpio/gpio.h> 25*f126890aSEmmanuel Vadot#include "arm-realview-eb.dtsi" 26*f126890aSEmmanuel Vadot 27*f126890aSEmmanuel Vadot/* 28*f126890aSEmmanuel Vadot * This is the common include file for all MPCore variants of the 29*f126890aSEmmanuel Vadot * Evaluation Baseboard, i.e. ARM11MPCore, ARM11MPCore Revision B 30*f126890aSEmmanuel Vadot * and Cortex-A9 MPCore. 31*f126890aSEmmanuel Vadot */ 32*f126890aSEmmanuel Vadot/ { 33*f126890aSEmmanuel Vadot soc { 34*f126890aSEmmanuel Vadot #address-cells = <1>; 35*f126890aSEmmanuel Vadot #size-cells = <1>; 36*f126890aSEmmanuel Vadot compatible = "arm,realview-eb-soc", "simple-bus"; 37*f126890aSEmmanuel Vadot regmap = <&syscon>; 38*f126890aSEmmanuel Vadot ranges; 39*f126890aSEmmanuel Vadot 40*f126890aSEmmanuel Vadot /* Primary interrupt controller in the test chip */ 41*f126890aSEmmanuel Vadot intc: interrupt-controller@1f000100 { 42*f126890aSEmmanuel Vadot compatible = "arm,eb11mp-gic"; 43*f126890aSEmmanuel Vadot #interrupt-cells = <3>; 44*f126890aSEmmanuel Vadot #address-cells = <1>; 45*f126890aSEmmanuel Vadot interrupt-controller; 46*f126890aSEmmanuel Vadot reg = <0x1f001000 0x1000>, 47*f126890aSEmmanuel Vadot <0x1f000100 0x100>; 48*f126890aSEmmanuel Vadot }; 49*f126890aSEmmanuel Vadot 50*f126890aSEmmanuel Vadot /* Secondary interrupt controller on the FPGA */ 51*f126890aSEmmanuel Vadot intc_second: interrupt-controller@10040000 { 52*f126890aSEmmanuel Vadot compatible = "arm,pl390"; 53*f126890aSEmmanuel Vadot #interrupt-cells = <3>; 54*f126890aSEmmanuel Vadot #address-cells = <1>; 55*f126890aSEmmanuel Vadot interrupt-controller; 56*f126890aSEmmanuel Vadot reg = <0x10041000 0x1000>, 57*f126890aSEmmanuel Vadot <0x10040000 0x100>; 58*f126890aSEmmanuel Vadot interrupt-parent = <&intc>; 59*f126890aSEmmanuel Vadot interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; 60*f126890aSEmmanuel Vadot }; 61*f126890aSEmmanuel Vadot 62*f126890aSEmmanuel Vadot L2: cache-controller { 63*f126890aSEmmanuel Vadot compatible = "arm,l220-cache"; 64*f126890aSEmmanuel Vadot reg = <0x1f002000 0x1000>; 65*f126890aSEmmanuel Vadot interrupt-parent = <&intc>; 66*f126890aSEmmanuel Vadot interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, 67*f126890aSEmmanuel Vadot <0 30 IRQ_TYPE_LEVEL_HIGH>, 68*f126890aSEmmanuel Vadot <0 31 IRQ_TYPE_LEVEL_HIGH>; 69*f126890aSEmmanuel Vadot cache-unified; 70*f126890aSEmmanuel Vadot cache-level = <2>; 71*f126890aSEmmanuel Vadot /* 72*f126890aSEmmanuel Vadot * Override default cache size, sets and 73*f126890aSEmmanuel Vadot * associativity as these may be erroneously set 74*f126890aSEmmanuel Vadot * up by boot loader(s), probably for safety 75*f126890aSEmmanuel Vadot * since th outer sync operation can cause the 76*f126890aSEmmanuel Vadot * cache to hang unless disabled. 77*f126890aSEmmanuel Vadot */ 78*f126890aSEmmanuel Vadot cache-size = <1048576>; // 1MB 79*f126890aSEmmanuel Vadot cache-sets = <4096>; 80*f126890aSEmmanuel Vadot cache-line-size = <32>; 81*f126890aSEmmanuel Vadot arm,shared-override; 82*f126890aSEmmanuel Vadot arm,parity-enable; 83*f126890aSEmmanuel Vadot arm,outer-sync-disable; 84*f126890aSEmmanuel Vadot }; 85*f126890aSEmmanuel Vadot 86*f126890aSEmmanuel Vadot scu: scu@1f000000 { 87*f126890aSEmmanuel Vadot compatible = "arm,arm11mp-scu"; 88*f126890aSEmmanuel Vadot reg = <0x1f000000 0x100>; 89*f126890aSEmmanuel Vadot }; 90*f126890aSEmmanuel Vadot 91*f126890aSEmmanuel Vadot twd_timer: timer@1f000600 { 92*f126890aSEmmanuel Vadot compatible = "arm,arm11mp-twd-timer"; 93*f126890aSEmmanuel Vadot reg = <0x1f000600 0x20>; 94*f126890aSEmmanuel Vadot interrupt-parent = <&intc>; 95*f126890aSEmmanuel Vadot interrupts = <1 13 0xf04>; 96*f126890aSEmmanuel Vadot }; 97*f126890aSEmmanuel Vadot 98*f126890aSEmmanuel Vadot twd_wdog: watchdog@1f000620 { 99*f126890aSEmmanuel Vadot compatible = "arm,arm11mp-twd-wdt"; 100*f126890aSEmmanuel Vadot reg = <0x1f000620 0x20>; 101*f126890aSEmmanuel Vadot interrupt-parent = <&intc>; 102*f126890aSEmmanuel Vadot interrupts = <1 14 0xf04>; 103*f126890aSEmmanuel Vadot }; 104*f126890aSEmmanuel Vadot 105*f126890aSEmmanuel Vadot /* PMU with one IRQ line per core */ 106*f126890aSEmmanuel Vadot pmu: pmu@0 { 107*f126890aSEmmanuel Vadot compatible = "arm,arm11mpcore-pmu"; 108*f126890aSEmmanuel Vadot interrupt-parent = <&intc>; 109*f126890aSEmmanuel Vadot interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>, 110*f126890aSEmmanuel Vadot <0 18 IRQ_TYPE_LEVEL_HIGH>, 111*f126890aSEmmanuel Vadot <0 19 IRQ_TYPE_LEVEL_HIGH>, 112*f126890aSEmmanuel Vadot <0 20 IRQ_TYPE_LEVEL_HIGH>; 113*f126890aSEmmanuel Vadot }; 114*f126890aSEmmanuel Vadot }; 115*f126890aSEmmanuel Vadot}; 116*f126890aSEmmanuel Vadot 117*f126890aSEmmanuel Vadot/* 118*f126890aSEmmanuel Vadot * This adapts all the peripherals to the interrupt routing 119*f126890aSEmmanuel Vadot * to the GIC on the core tile. 120*f126890aSEmmanuel Vadot */ 121*f126890aSEmmanuel Vadot 122*f126890aSEmmanuel Vadotðernet { 123*f126890aSEmmanuel Vadot interrupt-parent = <&intc>; 124*f126890aSEmmanuel Vadot interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; 125*f126890aSEmmanuel Vadot}; 126*f126890aSEmmanuel Vadot 127*f126890aSEmmanuel Vadot&usb { 128*f126890aSEmmanuel Vadot interrupt-parent = <&intc>; 129*f126890aSEmmanuel Vadot interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; 130*f126890aSEmmanuel Vadot}; 131*f126890aSEmmanuel Vadot 132*f126890aSEmmanuel Vadot&aaci { 133*f126890aSEmmanuel Vadot interrupt-parent = <&intc>; 134*f126890aSEmmanuel Vadot interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; 135*f126890aSEmmanuel Vadot}; 136*f126890aSEmmanuel Vadot 137*f126890aSEmmanuel Vadot&mmc { 138*f126890aSEmmanuel Vadot interrupt-parent = <&intc>; 139*f126890aSEmmanuel Vadot interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>, 140*f126890aSEmmanuel Vadot <0 15 IRQ_TYPE_LEVEL_HIGH>; 141*f126890aSEmmanuel Vadot}; 142*f126890aSEmmanuel Vadot 143*f126890aSEmmanuel Vadot&kmi0 { 144*f126890aSEmmanuel Vadot interrupt-parent = <&intc>; 145*f126890aSEmmanuel Vadot interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; 146*f126890aSEmmanuel Vadot}; 147*f126890aSEmmanuel Vadot 148*f126890aSEmmanuel Vadot&kmi1 { 149*f126890aSEmmanuel Vadot interrupt-parent = <&intc>; 150*f126890aSEmmanuel Vadot interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; 151*f126890aSEmmanuel Vadot}; 152*f126890aSEmmanuel Vadot 153*f126890aSEmmanuel Vadot&serial0 { 154*f126890aSEmmanuel Vadot interrupt-parent = <&intc>; 155*f126890aSEmmanuel Vadot interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; 156*f126890aSEmmanuel Vadot}; 157*f126890aSEmmanuel Vadot 158*f126890aSEmmanuel Vadot&serial1 { 159*f126890aSEmmanuel Vadot interrupt-parent = <&intc>; 160*f126890aSEmmanuel Vadot interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; 161*f126890aSEmmanuel Vadot}; 162*f126890aSEmmanuel Vadot 163*f126890aSEmmanuel Vadot&timer01 { 164*f126890aSEmmanuel Vadot interrupt-parent = <&intc>; 165*f126890aSEmmanuel Vadot interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>; 166*f126890aSEmmanuel Vadot}; 167*f126890aSEmmanuel Vadot 168*f126890aSEmmanuel Vadot&timer23 { 169*f126890aSEmmanuel Vadot interrupt-parent = <&intc>; 170*f126890aSEmmanuel Vadot interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; 171*f126890aSEmmanuel Vadot}; 172*f126890aSEmmanuel Vadot 173*f126890aSEmmanuel Vadot&rtc { 174*f126890aSEmmanuel Vadot interrupt-parent = <&intc>; 175*f126890aSEmmanuel Vadot interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; 176*f126890aSEmmanuel Vadot}; 177*f126890aSEmmanuel Vadot 178*f126890aSEmmanuel Vadot/* 179*f126890aSEmmanuel Vadot * On revision A, these peripherals does not have their IRQ lines 180*f126890aSEmmanuel Vadot * routed to the core tile, but they can be reached on the secondary 181*f126890aSEmmanuel Vadot * GIC. 182*f126890aSEmmanuel Vadot */ 183*f126890aSEmmanuel Vadot&gpio0 { 184*f126890aSEmmanuel Vadot interrupt-parent = <&intc_second>; 185*f126890aSEmmanuel Vadot interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; 186*f126890aSEmmanuel Vadot}; 187*f126890aSEmmanuel Vadot 188*f126890aSEmmanuel Vadot&gpio1 { 189*f126890aSEmmanuel Vadot interrupt-parent = <&intc_second>; 190*f126890aSEmmanuel Vadot interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; 191*f126890aSEmmanuel Vadot}; 192*f126890aSEmmanuel Vadot 193*f126890aSEmmanuel Vadot&gpio2 { 194*f126890aSEmmanuel Vadot interrupt-parent = <&intc_second>; 195*f126890aSEmmanuel Vadot interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; 196*f126890aSEmmanuel Vadot}; 197*f126890aSEmmanuel Vadot 198*f126890aSEmmanuel Vadot&serial2 { 199*f126890aSEmmanuel Vadot interrupt-parent = <&intc_second>; 200*f126890aSEmmanuel Vadot interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; 201*f126890aSEmmanuel Vadot status = "okay"; 202*f126890aSEmmanuel Vadot}; 203*f126890aSEmmanuel Vadot 204*f126890aSEmmanuel Vadot&serial3 { 205*f126890aSEmmanuel Vadot interrupt-parent = <&intc_second>; 206*f126890aSEmmanuel Vadot interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; 207*f126890aSEmmanuel Vadot status = "okay"; 208*f126890aSEmmanuel Vadot}; 209*f126890aSEmmanuel Vadot 210*f126890aSEmmanuel Vadot&ssp { 211*f126890aSEmmanuel Vadot interrupt-parent = <&intc_second>; 212*f126890aSEmmanuel Vadot interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; 213*f126890aSEmmanuel Vadot status = "okay"; 214*f126890aSEmmanuel Vadot}; 215*f126890aSEmmanuel Vadot 216*f126890aSEmmanuel Vadot&wdog { 217*f126890aSEmmanuel Vadot interrupt-parent = <&intc_second>; 218*f126890aSEmmanuel Vadot interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; 219*f126890aSEmmanuel Vadot status = "okay"; 220*f126890aSEmmanuel Vadot}; 221