1*f126890aSEmmanuel Vadot// SPDX-License-Identifier: GPL-2.0 2*f126890aSEmmanuel Vadot/* 3*f126890aSEmmanuel Vadot * Device Tree for the ARM Integrator/AP platform 4*f126890aSEmmanuel Vadot */ 5*f126890aSEmmanuel Vadot 6*f126890aSEmmanuel Vadot/dts-v1/; 7*f126890aSEmmanuel Vadot#include "integrator.dtsi" 8*f126890aSEmmanuel Vadot#include <dt-bindings/gpio/gpio.h> 9*f126890aSEmmanuel Vadot#include <dt-bindings/input/input.h> 10*f126890aSEmmanuel Vadot 11*f126890aSEmmanuel Vadot/ { 12*f126890aSEmmanuel Vadot model = "ARM Integrator/AP"; 13*f126890aSEmmanuel Vadot compatible = "arm,integrator-ap"; 14*f126890aSEmmanuel Vadot 15*f126890aSEmmanuel Vadot cpus { 16*f126890aSEmmanuel Vadot #address-cells = <1>; 17*f126890aSEmmanuel Vadot #size-cells = <0>; 18*f126890aSEmmanuel Vadot 19*f126890aSEmmanuel Vadot cpu@0 { 20*f126890aSEmmanuel Vadot device_type = "cpu"; 21*f126890aSEmmanuel Vadot /* 22*f126890aSEmmanuel Vadot * Since the board has pluggable CPU modules, we 23*f126890aSEmmanuel Vadot * cannot define a proper compatible here. Let the 24*f126890aSEmmanuel Vadot * boot loader fill in the apropriate compatible 25*f126890aSEmmanuel Vadot * string if necessary. 26*f126890aSEmmanuel Vadot */ 27*f126890aSEmmanuel Vadot /* compatible = "arm,arm926ej-s"; */ 28*f126890aSEmmanuel Vadot reg = <0>; 29*f126890aSEmmanuel Vadot /* 30*f126890aSEmmanuel Vadot * The documentation in ARM DUI 0138E page 3-12 states 31*f126890aSEmmanuel Vadot * that the maximum frequency for this clock is 200 MHz 32*f126890aSEmmanuel Vadot * but painful trial-and-error has proved to me that it 33*f126890aSEmmanuel Vadot * is actually just hanging the system above 71 MHz. 34*f126890aSEmmanuel Vadot * Sad but true. 35*f126890aSEmmanuel Vadot */ 36*f126890aSEmmanuel Vadot /* kHz uV */ 37*f126890aSEmmanuel Vadot operating-points = <71000 0 38*f126890aSEmmanuel Vadot 66000 0 39*f126890aSEmmanuel Vadot 60000 0 40*f126890aSEmmanuel Vadot 48000 0 41*f126890aSEmmanuel Vadot 36000 0 42*f126890aSEmmanuel Vadot 24000 0 43*f126890aSEmmanuel Vadot 12000 0>; 44*f126890aSEmmanuel Vadot clocks = <&cmosc>; 45*f126890aSEmmanuel Vadot clock-names = "cpu"; 46*f126890aSEmmanuel Vadot clock-latency = <1000000>; /* 1 ms */ 47*f126890aSEmmanuel Vadot }; 48*f126890aSEmmanuel Vadot }; 49*f126890aSEmmanuel Vadot 50*f126890aSEmmanuel Vadot aliases { 51*f126890aSEmmanuel Vadot arm,timer-primary = &timer2; 52*f126890aSEmmanuel Vadot arm,timer-secondary = &timer1; 53*f126890aSEmmanuel Vadot }; 54*f126890aSEmmanuel Vadot 55*f126890aSEmmanuel Vadot chosen { 56*f126890aSEmmanuel Vadot bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk"; 57*f126890aSEmmanuel Vadot }; 58*f126890aSEmmanuel Vadot 59*f126890aSEmmanuel Vadot /* 24 MHz chrystal on the Integrator/AP development board */ 60*f126890aSEmmanuel Vadot xtal24mhz: xtal24mhz@24M { 61*f126890aSEmmanuel Vadot #clock-cells = <0>; 62*f126890aSEmmanuel Vadot compatible = "fixed-clock"; 63*f126890aSEmmanuel Vadot clock-frequency = <24000000>; 64*f126890aSEmmanuel Vadot }; 65*f126890aSEmmanuel Vadot 66*f126890aSEmmanuel Vadot pclk: pclk@0 { 67*f126890aSEmmanuel Vadot #clock-cells = <0>; 68*f126890aSEmmanuel Vadot compatible = "fixed-factor-clock"; 69*f126890aSEmmanuel Vadot clock-div = <1>; 70*f126890aSEmmanuel Vadot clock-mult = <1>; 71*f126890aSEmmanuel Vadot clocks = <&xtal24mhz>; 72*f126890aSEmmanuel Vadot }; 73*f126890aSEmmanuel Vadot 74*f126890aSEmmanuel Vadot /* The UART clock is 14.74 MHz divided by an ICS525 */ 75*f126890aSEmmanuel Vadot uartclk: uartclk@14.74M { 76*f126890aSEmmanuel Vadot #clock-cells = <0>; 77*f126890aSEmmanuel Vadot compatible = "fixed-clock"; 78*f126890aSEmmanuel Vadot clock-frequency = <14745600>; 79*f126890aSEmmanuel Vadot clocks = <&xtal24mhz>; 80*f126890aSEmmanuel Vadot }; 81*f126890aSEmmanuel Vadot 82*f126890aSEmmanuel Vadot core-module@10000000 { 83*f126890aSEmmanuel Vadot /* 24 MHz chrystal on the core module */ 84*f126890aSEmmanuel Vadot cm24mhz: cm24mhz@24M { 85*f126890aSEmmanuel Vadot #clock-cells = <0>; 86*f126890aSEmmanuel Vadot compatible = "fixed-clock"; 87*f126890aSEmmanuel Vadot clock-frequency = <24000000>; 88*f126890aSEmmanuel Vadot }; 89*f126890aSEmmanuel Vadot 90*f126890aSEmmanuel Vadot /* Oscillator on the core module, clocks the CPU core */ 91*f126890aSEmmanuel Vadot cmosc: clock-controller@8 { 92*f126890aSEmmanuel Vadot compatible = "arm,syscon-icst525-integratorap-cm"; 93*f126890aSEmmanuel Vadot reg = <0x08 0x04>; 94*f126890aSEmmanuel Vadot #clock-cells = <0>; 95*f126890aSEmmanuel Vadot lock-offset = <0x14>; 96*f126890aSEmmanuel Vadot vco-offset = <0x08>; 97*f126890aSEmmanuel Vadot clocks = <&cm24mhz>; 98*f126890aSEmmanuel Vadot }; 99*f126890aSEmmanuel Vadot 100*f126890aSEmmanuel Vadot /* Auxilary oscillator on the core module, 32.369MHz at boot */ 101*f126890aSEmmanuel Vadot auxosc: clock-controller@1c { 102*f126890aSEmmanuel Vadot compatible = "arm,syscon-icst525"; 103*f126890aSEmmanuel Vadot reg = <0x1c 0x04>; 104*f126890aSEmmanuel Vadot #clock-cells = <0>; 105*f126890aSEmmanuel Vadot lock-offset = <0x14>; 106*f126890aSEmmanuel Vadot vco-offset = <0x1c>; 107*f126890aSEmmanuel Vadot clocks = <&cm24mhz>; 108*f126890aSEmmanuel Vadot }; 109*f126890aSEmmanuel Vadot }; 110*f126890aSEmmanuel Vadot 111*f126890aSEmmanuel Vadot syscon { 112*f126890aSEmmanuel Vadot compatible = "arm,integrator-ap-syscon", "syscon"; 113*f126890aSEmmanuel Vadot reg = <0x11000000 0x100>; 114*f126890aSEmmanuel Vadot ranges = <0x0 0x11000000 0x100>; 115*f126890aSEmmanuel Vadot #size-cells = <1>; 116*f126890aSEmmanuel Vadot #address-cells = <1>; 117*f126890aSEmmanuel Vadot 118*f126890aSEmmanuel Vadot /* 119*f126890aSEmmanuel Vadot * SYSCLK clocks PCIv3 bridge, system controller and the 120*f126890aSEmmanuel Vadot * logic modules. 121*f126890aSEmmanuel Vadot */ 122*f126890aSEmmanuel Vadot sysclk: clock-controller@4 { 123*f126890aSEmmanuel Vadot compatible = "arm,syscon-icst525-integratorap-sys"; 124*f126890aSEmmanuel Vadot reg = <0x04 0x04>; 125*f126890aSEmmanuel Vadot #clock-cells = <0>; 126*f126890aSEmmanuel Vadot lock-offset = <0x1c>; 127*f126890aSEmmanuel Vadot vco-offset = <0x04>; 128*f126890aSEmmanuel Vadot clocks = <&xtal24mhz>; 129*f126890aSEmmanuel Vadot }; 130*f126890aSEmmanuel Vadot 131*f126890aSEmmanuel Vadot /* One-bit control for the PCI bus clock (33 or 25 MHz) */ 132*f126890aSEmmanuel Vadot pciclk: clock-controller@4,8 { 133*f126890aSEmmanuel Vadot compatible = "arm,syscon-icst525-integratorap-pci"; 134*f126890aSEmmanuel Vadot reg = <0x04 0x04>; 135*f126890aSEmmanuel Vadot #clock-cells = <0>; 136*f126890aSEmmanuel Vadot lock-offset = <0x1c>; 137*f126890aSEmmanuel Vadot vco-offset = <0x04>; 138*f126890aSEmmanuel Vadot clocks = <&xtal24mhz>; 139*f126890aSEmmanuel Vadot }; 140*f126890aSEmmanuel Vadot }; 141*f126890aSEmmanuel Vadot 142*f126890aSEmmanuel Vadot timer0: timer@13000000 { 143*f126890aSEmmanuel Vadot compatible = "arm,integrator-timer"; 144*f126890aSEmmanuel Vadot clocks = <&xtal24mhz>; 145*f126890aSEmmanuel Vadot }; 146*f126890aSEmmanuel Vadot 147*f126890aSEmmanuel Vadot timer1: timer@13000100 { 148*f126890aSEmmanuel Vadot compatible = "arm,integrator-timer"; 149*f126890aSEmmanuel Vadot clocks = <&xtal24mhz>; 150*f126890aSEmmanuel Vadot }; 151*f126890aSEmmanuel Vadot 152*f126890aSEmmanuel Vadot timer2: timer@13000200 { 153*f126890aSEmmanuel Vadot compatible = "arm,integrator-timer"; 154*f126890aSEmmanuel Vadot clocks = <&xtal24mhz>; 155*f126890aSEmmanuel Vadot }; 156*f126890aSEmmanuel Vadot 157*f126890aSEmmanuel Vadot pic: pic@14000000 { 158*f126890aSEmmanuel Vadot valid-mask = <0x003fffff>; 159*f126890aSEmmanuel Vadot }; 160*f126890aSEmmanuel Vadot 161*f126890aSEmmanuel Vadot pci: pci@62000000 { 162*f126890aSEmmanuel Vadot compatible = "arm,integrator-ap-pci", "v3,v360epc-pci"; 163*f126890aSEmmanuel Vadot device_type = "pci"; 164*f126890aSEmmanuel Vadot #interrupt-cells = <1>; 165*f126890aSEmmanuel Vadot #size-cells = <2>; 166*f126890aSEmmanuel Vadot #address-cells = <3>; 167*f126890aSEmmanuel Vadot /* Bridge registers and config access space */ 168*f126890aSEmmanuel Vadot reg = <0x62000000 0x10000>, <0x61000000 0x01000000>; 169*f126890aSEmmanuel Vadot interrupt-parent = <&pic>; 170*f126890aSEmmanuel Vadot interrupts = <17>; /* Bus error IRQ */ 171*f126890aSEmmanuel Vadot clocks = <&pciclk>; 172*f126890aSEmmanuel Vadot bus-range = <0x00 0xff>; 173*f126890aSEmmanuel Vadot ranges = <0x01000000 0 0x0000000 /* I/O space @00000000 */ 174*f126890aSEmmanuel Vadot 0x60000000 0 0x00010000 /* 64 KB @ LB 60000000 */ 175*f126890aSEmmanuel Vadot 0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */ 176*f126890aSEmmanuel Vadot 0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */ 177*f126890aSEmmanuel Vadot 0x42000000 0 0x50000000 /* prefetchable memory @50000000 */ 178*f126890aSEmmanuel Vadot 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */ 179*f126890aSEmmanuel Vadot dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */ 180*f126890aSEmmanuel Vadot 0x20000000 0 0x20000000 /* 512 MB @ LB 20000000 1:1 */ 181*f126890aSEmmanuel Vadot 0x02000000 0 0x80000000 /* Core module alias memory */ 182*f126890aSEmmanuel Vadot 0x80000000 0 0x40000000>; /* 1GB @ LB 80000000 */ 183*f126890aSEmmanuel Vadot interrupt-map-mask = <0xf800 0 0 0x7>; 184*f126890aSEmmanuel Vadot interrupt-map = < 185*f126890aSEmmanuel Vadot /* IDSEL 9 */ 186*f126890aSEmmanuel Vadot 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */ 187*f126890aSEmmanuel Vadot 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */ 188*f126890aSEmmanuel Vadot 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */ 189*f126890aSEmmanuel Vadot 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */ 190*f126890aSEmmanuel Vadot /* IDSEL 10 */ 191*f126890aSEmmanuel Vadot 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */ 192*f126890aSEmmanuel Vadot 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */ 193*f126890aSEmmanuel Vadot 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */ 194*f126890aSEmmanuel Vadot 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */ 195*f126890aSEmmanuel Vadot /* IDSEL 11 */ 196*f126890aSEmmanuel Vadot 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */ 197*f126890aSEmmanuel Vadot 0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */ 198*f126890aSEmmanuel Vadot 0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */ 199*f126890aSEmmanuel Vadot 0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */ 200*f126890aSEmmanuel Vadot /* IDSEL 12 */ 201*f126890aSEmmanuel Vadot 0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */ 202*f126890aSEmmanuel Vadot 0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */ 203*f126890aSEmmanuel Vadot 0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */ 204*f126890aSEmmanuel Vadot 0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */ 205*f126890aSEmmanuel Vadot >; 206*f126890aSEmmanuel Vadot }; 207*f126890aSEmmanuel Vadot 208*f126890aSEmmanuel Vadot fpga { 209*f126890aSEmmanuel Vadot /* 210*f126890aSEmmanuel Vadot * The Integator/AP predates the idea to have magic numbers 211*f126890aSEmmanuel Vadot * identifying the PrimeCell in hardware, thus we have to 212*f126890aSEmmanuel Vadot * supply these from the device tree. 213*f126890aSEmmanuel Vadot */ 214*f126890aSEmmanuel Vadot rtc: rtc@15000000 { 215*f126890aSEmmanuel Vadot compatible = "arm,pl030", "arm,primecell"; 216*f126890aSEmmanuel Vadot arm,primecell-periphid = <0x00041030>; 217*f126890aSEmmanuel Vadot clocks = <&pclk>; 218*f126890aSEmmanuel Vadot clock-names = "apb_pclk"; 219*f126890aSEmmanuel Vadot }; 220*f126890aSEmmanuel Vadot 221*f126890aSEmmanuel Vadot uart0: serial@16000000 { 222*f126890aSEmmanuel Vadot compatible = "arm,pl010", "arm,primecell"; 223*f126890aSEmmanuel Vadot arm,primecell-periphid = <0x00041010>; 224*f126890aSEmmanuel Vadot clocks = <&uartclk>, <&pclk>; 225*f126890aSEmmanuel Vadot clock-names = "uartclk", "apb_pclk"; 226*f126890aSEmmanuel Vadot }; 227*f126890aSEmmanuel Vadot 228*f126890aSEmmanuel Vadot uart1: serial@17000000 { 229*f126890aSEmmanuel Vadot compatible = "arm,pl010", "arm,primecell"; 230*f126890aSEmmanuel Vadot arm,primecell-periphid = <0x00041010>; 231*f126890aSEmmanuel Vadot clocks = <&uartclk>, <&pclk>; 232*f126890aSEmmanuel Vadot clock-names = "uartclk", "apb_pclk"; 233*f126890aSEmmanuel Vadot }; 234*f126890aSEmmanuel Vadot 235*f126890aSEmmanuel Vadot kmi0: kmi@18000000 { 236*f126890aSEmmanuel Vadot compatible = "arm,pl050", "arm,primecell"; 237*f126890aSEmmanuel Vadot arm,primecell-periphid = <0x00041050>; 238*f126890aSEmmanuel Vadot clocks = <&xtal24mhz>, <&pclk>; 239*f126890aSEmmanuel Vadot clock-names = "KMIREFCLK", "apb_pclk"; 240*f126890aSEmmanuel Vadot }; 241*f126890aSEmmanuel Vadot 242*f126890aSEmmanuel Vadot kmi1: kmi@19000000 { 243*f126890aSEmmanuel Vadot compatible = "arm,pl050", "arm,primecell"; 244*f126890aSEmmanuel Vadot arm,primecell-periphid = <0x00041050>; 245*f126890aSEmmanuel Vadot clocks = <&xtal24mhz>, <&pclk>; 246*f126890aSEmmanuel Vadot clock-names = "KMIREFCLK", "apb_pclk"; 247*f126890aSEmmanuel Vadot }; 248*f126890aSEmmanuel Vadot }; 249*f126890aSEmmanuel Vadot 250*f126890aSEmmanuel Vadot /* 251*f126890aSEmmanuel Vadot * Logic module bus, we support up to 4 logical modules 252*f126890aSEmmanuel Vadot * They appear at 0xc0000000, 0xd0000000, 0xe0000000 and 0xf0000000 253*f126890aSEmmanuel Vadot * and use interrupts 9, 10, 11 and 12 respectively. 254*f126890aSEmmanuel Vadot */ 255*f126890aSEmmanuel Vadot bus@c0000000 { 256*f126890aSEmmanuel Vadot compatible = "arm,integrator-ap-lm"; 257*f126890aSEmmanuel Vadot #address-cells = <1>; 258*f126890aSEmmanuel Vadot #size-cells = <1>; 259*f126890aSEmmanuel Vadot ranges = <0xc0000000 0xc0000000 0x40000000>; 260*f126890aSEmmanuel Vadot dma-ranges; 261*f126890aSEmmanuel Vadot 262*f126890aSEmmanuel Vadot lm0: bus@c0000000 { 263*f126890aSEmmanuel Vadot compatible = "simple-bus"; 264*f126890aSEmmanuel Vadot ranges = <0x00000000 0xc0000000 0x10000000>; 265*f126890aSEmmanuel Vadot dma-ranges = <0x00000000 0xc0000000 0x10000000>; 266*f126890aSEmmanuel Vadot reg = <0xc0000000 0x10000000>; 267*f126890aSEmmanuel Vadot #address-cells = <1>; 268*f126890aSEmmanuel Vadot #size-cells = <1>; 269*f126890aSEmmanuel Vadot }; 270*f126890aSEmmanuel Vadot lm1: bus@d0000000 { 271*f126890aSEmmanuel Vadot compatible = "simple-bus"; 272*f126890aSEmmanuel Vadot ranges = <0x00000000 0xd0000000 0x10000000>; 273*f126890aSEmmanuel Vadot dma-ranges = <0x00000000 0xd0000000 0x10000000>; 274*f126890aSEmmanuel Vadot reg = <0xd0000000 0x10000000>; 275*f126890aSEmmanuel Vadot #address-cells = <1>; 276*f126890aSEmmanuel Vadot #size-cells = <1>; 277*f126890aSEmmanuel Vadot }; 278*f126890aSEmmanuel Vadot lm2: bus@e0000000 { 279*f126890aSEmmanuel Vadot compatible = "simple-bus"; 280*f126890aSEmmanuel Vadot ranges = <0x00000000 0xe0000000 0x10000000>; 281*f126890aSEmmanuel Vadot dma-ranges = <0x00000000 0xe0000000 0x10000000>; 282*f126890aSEmmanuel Vadot reg = <0xe0000000 0x10000000>; 283*f126890aSEmmanuel Vadot #address-cells = <1>; 284*f126890aSEmmanuel Vadot #size-cells = <1>; 285*f126890aSEmmanuel Vadot }; 286*f126890aSEmmanuel Vadot lm3: bus@f0000000 { 287*f126890aSEmmanuel Vadot compatible = "simple-bus"; 288*f126890aSEmmanuel Vadot ranges = <0x00000000 0xf0000000 0x10000000>; 289*f126890aSEmmanuel Vadot dma-ranges = <0x00000000 0xf0000000 0x10000000>; 290*f126890aSEmmanuel Vadot reg = <0xf0000000 0x10000000>; 291*f126890aSEmmanuel Vadot #address-cells = <1>; 292*f126890aSEmmanuel Vadot #size-cells = <1>; 293*f126890aSEmmanuel Vadot }; 294*f126890aSEmmanuel Vadot }; 295*f126890aSEmmanuel Vadot}; 296