1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2022 Broadcom Ltd.
4 */
5
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/interrupt-controller/irq.h>
8
9/ {
10	compatible = "brcm,bcm6846", "brcm,bcmbca";
11	#address-cells = <1>;
12	#size-cells = <1>;
13
14	interrupt-parent = <&gic>;
15
16	cpus {
17		#address-cells = <1>;
18		#size-cells = <0>;
19
20		CA7_0: cpu@0 {
21			device_type = "cpu";
22			compatible = "arm,cortex-a7";
23			reg = <0x0>;
24			next-level-cache = <&L2_0>;
25			enable-method = "psci";
26		};
27
28		CA7_1: cpu@1 {
29			device_type = "cpu";
30			compatible = "arm,cortex-a7";
31			reg = <0x1>;
32			next-level-cache = <&L2_0>;
33			enable-method = "psci";
34		};
35
36		L2_0: l2-cache0 {
37			compatible = "cache";
38			cache-level = <2>;
39			cache-unified;
40		};
41	};
42
43	timer {
44		compatible = "arm,armv7-timer";
45		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
46			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
47			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
48			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
49		arm,cpu-registers-not-fw-configured;
50	};
51
52	pmu: pmu {
53		compatible = "arm,cortex-a7-pmu";
54		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
55			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
56		interrupt-affinity = <&CA7_0>, <&CA7_1>;
57	};
58
59	clocks: clocks {
60		periph_clk: periph-clk {
61			compatible = "fixed-clock";
62			#clock-cells = <0>;
63			clock-frequency = <200000000>;
64		};
65
66		hsspi_pll: hsspi-pll {
67			compatible = "fixed-clock";
68			#clock-cells = <0>;
69			clock-frequency = <400000000>;
70		};
71	};
72
73	psci {
74		compatible = "arm,psci-0.2";
75		method = "smc";
76	};
77
78	axi@81000000 {
79		compatible = "simple-bus";
80		#address-cells = <1>;
81		#size-cells = <1>;
82		ranges = <0 0x81000000 0x8000>;
83
84		gic: interrupt-controller@1000 {
85			compatible = "arm,cortex-a7-gic";
86			#interrupt-cells = <3>;
87			interrupt-controller;
88			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
89			reg = <0x1000 0x1000>,
90				<0x2000 0x2000>,
91				<0x4000 0x2000>,
92				<0x6000 0x2000>;
93		};
94	};
95
96	bus@ff800000 {
97		compatible = "simple-bus";
98		#address-cells = <1>;
99		#size-cells = <1>;
100		ranges = <0 0xff800000 0x800000>;
101
102		uart0: serial@640 {
103			compatible = "brcm,bcm6345-uart";
104			reg = <0x640 0x1b>;
105			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
106			clocks = <&periph_clk>;
107			clock-names = "refclk";
108			status = "disabled";
109		};
110
111		hsspi: spi@1000 {
112			#address-cells = <1>;
113			#size-cells = <0>;
114			compatible = "brcm,bcm6846-hsspi", "brcm,bcmbca-hsspi-v1.0";
115			reg = <0x1000 0x600>;
116			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
117			clocks = <&hsspi_pll &hsspi_pll>;
118			clock-names = "hsspi", "pll";
119			num-cs = <8>;
120			status = "disabled";
121		};
122	};
123};
124