1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2022 Broadcom Ltd.
4 */
5
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/interrupt-controller/irq.h>
8
9/ {
10	compatible = "brcm,bcm6878", "brcm,bcmbca";
11	#address-cells = <1>;
12	#size-cells = <1>;
13
14	interrupt-parent = <&gic>;
15
16	cpus {
17		#address-cells = <1>;
18		#size-cells = <0>;
19
20		CA7_0: cpu@0 {
21			device_type = "cpu";
22			compatible = "arm,cortex-a7";
23			reg = <0x0>;
24			next-level-cache = <&L2_0>;
25			enable-method = "psci";
26		};
27
28		CA7_1: cpu@1 {
29			device_type = "cpu";
30			compatible = "arm,cortex-a7";
31			reg = <0x1>;
32			next-level-cache = <&L2_0>;
33			enable-method = "psci";
34		};
35
36		L2_0: l2-cache0 {
37			compatible = "cache";
38			cache-level = <2>;
39			cache-unified;
40		};
41	};
42
43	timer {
44		compatible = "arm,armv7-timer";
45		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
46			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
47			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
48			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
49		arm,cpu-registers-not-fw-configured;
50	};
51
52	pmu: pmu {
53		compatible = "arm,cortex-a7-pmu";
54		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
55			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
56		interrupt-affinity = <&CA7_0>, <&CA7_1>;
57	};
58
59	clocks: clocks {
60		periph_clk: periph-clk {
61			compatible = "fixed-clock";
62			#clock-cells = <0>;
63			clock-frequency = <200000000>;
64		};
65
66		uart_clk: uart-clk {
67			compatible = "fixed-factor-clock";
68			#clock-cells = <0>;
69			clocks = <&periph_clk>;
70			clock-div = <4>;
71			clock-mult = <1>;
72		};
73
74		hsspi_pll: hsspi-pll {
75			compatible = "fixed-clock";
76			#clock-cells = <0>;
77			clock-frequency = <200000000>;
78		};
79	};
80
81	psci {
82		compatible = "arm,psci-0.2";
83		method = "smc";
84	};
85
86	axi@81000000 {
87		compatible = "simple-bus";
88		#address-cells = <1>;
89		#size-cells = <1>;
90		ranges = <0 0x81000000 0x8000>;
91
92		gic: interrupt-controller@1000 {
93			compatible = "arm,cortex-a7-gic";
94			#interrupt-cells = <3>;
95			interrupt-controller;
96			reg = <0x1000 0x1000>,
97				<0x2000 0x2000>,
98				<0x4000 0x2000>,
99				<0x6000 0x2000>;
100			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
101					IRQ_TYPE_LEVEL_HIGH)>;
102		};
103	};
104
105	bus@ff800000 {
106		compatible = "simple-bus";
107		#address-cells = <1>;
108		#size-cells = <1>;
109		ranges = <0 0xff800000 0x800000>;
110
111		hsspi: spi@1000 {
112			#address-cells = <1>;
113			#size-cells = <0>;
114			compatible = "brcm,bcm6878-hsspi", "brcm,bcmbca-hsspi-v1.0";
115			reg = <0x1000 0x600>;
116			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
117			clocks = <&hsspi_pll &hsspi_pll>;
118			clock-names = "hsspi", "pll";
119			num-cs = <8>;
120			status = "disabled";
121		};
122
123		uart0: serial@12000 {
124			compatible = "arm,pl011", "arm,primecell";
125			reg = <0x12000 0x1000>;
126			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
127			clocks = <&uart_clk>, <&uart_clk>;
128			clock-names = "uartclk", "apb_pclk";
129			status = "disabled";
130		};
131	};
132};
133