1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: Erin.Lo <erin.lo@mediatek.com>
5 *
6 */
7
8#include <dt-bindings/clock/mt2701-clk.h>
9#include <dt-bindings/phy/phy.h>
10#include <dt-bindings/power/mt2701-power.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/memory/mt2701-larb-port.h>
14#include <dt-bindings/reset/mt2701-resets.h>
15#include "mt2701-pinfunc.h"
16
17/ {
18	#address-cells = <2>;
19	#size-cells = <2>;
20	compatible = "mediatek,mt2701";
21	interrupt-parent = <&cirq>;
22
23	cpus {
24		#address-cells = <1>;
25		#size-cells = <0>;
26		enable-method = "mediatek,mt81xx-tz-smp";
27
28		cpu@0 {
29			device_type = "cpu";
30			compatible = "arm,cortex-a7";
31			reg = <0x0>;
32		};
33		cpu@1 {
34			device_type = "cpu";
35			compatible = "arm,cortex-a7";
36			reg = <0x1>;
37		};
38		cpu@2 {
39			device_type = "cpu";
40			compatible = "arm,cortex-a7";
41			reg = <0x2>;
42		};
43		cpu@3 {
44			device_type = "cpu";
45			compatible = "arm,cortex-a7";
46			reg = <0x3>;
47		};
48	};
49
50	reserved-memory {
51		#address-cells = <2>;
52		#size-cells = <2>;
53		ranges;
54
55		trustzone-bootinfo@80002000 {
56			compatible = "mediatek,trustzone-bootinfo";
57			reg = <0 0x80002000 0 0x1000>;
58		};
59	};
60
61	system_clk: dummy13m {
62		compatible = "fixed-clock";
63		clock-frequency = <13000000>;
64		#clock-cells = <0>;
65	};
66
67	rtc_clk: dummy32k {
68		compatible = "fixed-clock";
69		clock-frequency = <32000>;
70		#clock-cells = <0>;
71	};
72
73	clk26m: oscillator@0 {
74		compatible = "fixed-clock";
75		#clock-cells = <0>;
76		clock-frequency = <26000000>;
77		clock-output-names = "clk26m";
78	};
79
80	rtc32k: oscillator@1 {
81		compatible = "fixed-clock";
82		#clock-cells = <0>;
83		clock-frequency = <32000>;
84		clock-output-names = "rtc32k";
85	};
86
87	thermal-zones {
88		cpu_thermal: cpu_thermal {
89			polling-delay-passive = <1000>; /* milliseconds */
90			polling-delay = <1000>; /* milliseconds */
91
92			thermal-sensors = <&thermal 0>;
93			sustainable-power = <1000>;
94
95			trips {
96				threshold: trip-point@0 {
97					temperature = <68000>;
98					hysteresis = <2000>;
99					type = "passive";
100				};
101
102				target: trip-point@1 {
103					temperature = <85000>;
104					hysteresis = <2000>;
105					type = "passive";
106				};
107
108				cpu_crit: cpu_crit@0 {
109					temperature = <115000>;
110					hysteresis = <2000>;
111					type = "critical";
112				};
113			};
114		};
115	};
116
117	timer {
118		compatible = "arm,armv7-timer";
119		interrupt-parent = <&gic>;
120		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
121			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
122			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
123			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
124	};
125
126	topckgen: syscon@10000000 {
127		compatible = "mediatek,mt2701-topckgen", "syscon";
128		reg = <0 0x10000000 0 0x1000>;
129		#clock-cells = <1>;
130	};
131
132	infracfg: syscon@10001000 {
133		compatible = "mediatek,mt2701-infracfg", "syscon";
134		reg = <0 0x10001000 0 0x1000>;
135		#clock-cells = <1>;
136		#reset-cells = <1>;
137	};
138
139	pericfg: syscon@10003000 {
140		compatible = "mediatek,mt2701-pericfg", "syscon";
141		reg = <0 0x10003000 0 0x1000>;
142		#clock-cells = <1>;
143		#reset-cells = <1>;
144	};
145
146	syscfg_pctl_a: syscfg@10005000 {
147		compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
148		reg = <0 0x10005000 0 0x1000>;
149	};
150
151	scpsys: power-controller@10006000 {
152		compatible = "mediatek,mt2701-scpsys", "syscon";
153		#power-domain-cells = <1>;
154		reg = <0 0x10006000 0 0x1000>;
155		infracfg = <&infracfg>;
156		clocks = <&topckgen CLK_TOP_MM_SEL>,
157			 <&topckgen CLK_TOP_MFG_SEL>,
158			 <&topckgen CLK_TOP_ETHIF_SEL>;
159		clock-names = "mm", "mfg", "ethif";
160	};
161
162	watchdog: watchdog@10007000 {
163		compatible = "mediatek,mt2701-wdt",
164			     "mediatek,mt6589-wdt";
165		reg = <0 0x10007000 0 0x100>;
166	};
167
168	timer: timer@10008000 {
169		compatible = "mediatek,mt2701-timer",
170			     "mediatek,mt6577-timer";
171		reg = <0 0x10008000 0 0x80>;
172		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
173		clocks = <&system_clk>, <&rtc_clk>;
174		clock-names = "system-clk", "rtc-clk";
175	};
176
177	pio: pinctrl@1000b000 {
178		compatible = "mediatek,mt2701-pinctrl";
179		reg = <0 0x1000b000 0 0x1000>;
180		mediatek,pctl-regmap = <&syscfg_pctl_a>;
181		gpio-controller;
182		#gpio-cells = <2>;
183		interrupt-controller;
184		#interrupt-cells = <2>;
185		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
186			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
187	};
188
189	smi_common: smi@1000c000 {
190		compatible = "mediatek,mt2701-smi-common";
191		reg = <0 0x1000c000 0 0x1000>;
192		clocks = <&infracfg CLK_INFRA_SMI>,
193			 <&mmsys CLK_MM_SMI_COMMON>,
194			 <&infracfg CLK_INFRA_SMI>;
195		clock-names = "apb", "smi", "async";
196		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
197	};
198
199	sysirq: interrupt-controller@10200100 {
200		compatible = "mediatek,mt2701-sysirq",
201			     "mediatek,mt6577-sysirq";
202		interrupt-controller;
203		#interrupt-cells = <3>;
204		interrupt-parent = <&gic>;
205		reg = <0 0x10200100 0 0x1c>;
206	};
207
208	cirq: interrupt-controller@10204000 {
209		compatible = "mediatek,mt2701-cirq",
210			     "mediatek,mtk-cirq";
211		interrupt-controller;
212		#interrupt-cells = <3>;
213		interrupt-parent = <&sysirq>;
214		reg = <0 0x10204000 0 0x400>;
215		mediatek,ext-irq-range = <32 200>;
216	};
217
218	iommu: mmsys_iommu@10205000 {
219		compatible = "mediatek,mt2701-m4u";
220		reg = <0 0x10205000 0 0x1000>;
221		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
222		clocks = <&infracfg CLK_INFRA_M4U>;
223		clock-names = "bclk";
224		mediatek,larbs = <&larb0 &larb1 &larb2>;
225		#iommu-cells = <1>;
226	};
227
228	apmixedsys: syscon@10209000 {
229		compatible = "mediatek,mt2701-apmixedsys", "syscon";
230		reg = <0 0x10209000 0 0x1000>;
231		#clock-cells = <1>;
232	};
233
234	gic: interrupt-controller@10211000 {
235		compatible = "arm,cortex-a7-gic";
236		interrupt-controller;
237		#interrupt-cells = <3>;
238		interrupt-parent = <&gic>;
239		reg = <0 0x10211000 0 0x1000>,
240		      <0 0x10212000 0 0x2000>,
241		      <0 0x10214000 0 0x2000>,
242		      <0 0x10216000 0 0x2000>;
243	};
244
245	auxadc: adc@11001000 {
246		compatible = "mediatek,mt2701-auxadc";
247		reg = <0 0x11001000 0 0x1000>;
248		clocks = <&pericfg CLK_PERI_AUXADC>;
249		clock-names = "main";
250		#io-channel-cells = <1>;
251		status = "disabled";
252	};
253
254	uart0: serial@11002000 {
255		compatible = "mediatek,mt2701-uart",
256			     "mediatek,mt6577-uart";
257		reg = <0 0x11002000 0 0x400>;
258		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
259		clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
260		clock-names = "baud", "bus";
261		status = "disabled";
262	};
263
264	uart1: serial@11003000 {
265		compatible = "mediatek,mt2701-uart",
266			     "mediatek,mt6577-uart";
267		reg = <0 0x11003000 0 0x400>;
268		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
269		clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
270		clock-names = "baud", "bus";
271		status = "disabled";
272	};
273
274	uart2: serial@11004000 {
275		compatible = "mediatek,mt2701-uart",
276			     "mediatek,mt6577-uart";
277		reg = <0 0x11004000 0 0x400>;
278		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
279		clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
280		clock-names = "baud", "bus";
281		status = "disabled";
282	};
283
284	uart3: serial@11005000 {
285		compatible = "mediatek,mt2701-uart",
286			     "mediatek,mt6577-uart";
287		reg = <0 0x11005000 0 0x400>;
288		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
289		clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
290		clock-names = "baud", "bus";
291		status = "disabled";
292	};
293
294	i2c0: i2c@11007000 {
295		compatible = "mediatek,mt2701-i2c",
296			     "mediatek,mt6577-i2c";
297		reg = <0 0x11007000 0 0x70>,
298		      <0 0x11000200 0 0x80>;
299		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
300		clock-div = <16>;
301		clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>;
302		clock-names = "main", "dma";
303		#address-cells = <1>;
304		#size-cells = <0>;
305		status = "disabled";
306	};
307
308	i2c1: i2c@11008000 {
309		compatible = "mediatek,mt2701-i2c",
310			     "mediatek,mt6577-i2c";
311		reg = <0 0x11008000 0 0x70>,
312		      <0 0x11000280 0 0x80>;
313		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
314		clock-div = <16>;
315		clocks = <&pericfg CLK_PERI_I2C1>, <&pericfg CLK_PERI_AP_DMA>;
316		clock-names = "main", "dma";
317		#address-cells = <1>;
318		#size-cells = <0>;
319		status = "disabled";
320	};
321
322	i2c2: i2c@11009000 {
323		compatible = "mediatek,mt2701-i2c",
324			     "mediatek,mt6577-i2c";
325		reg = <0 0x11009000 0 0x70>,
326		      <0 0x11000300 0 0x80>;
327		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
328		clock-div = <16>;
329		clocks = <&pericfg CLK_PERI_I2C2>, <&pericfg CLK_PERI_AP_DMA>;
330		clock-names = "main", "dma";
331		#address-cells = <1>;
332		#size-cells = <0>;
333		status = "disabled";
334	};
335
336	spi0: spi@1100a000 {
337		compatible = "mediatek,mt2701-spi";
338		#address-cells = <1>;
339		#size-cells = <0>;
340		reg = <0 0x1100a000 0 0x100>;
341		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
342		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
343			 <&topckgen CLK_TOP_SPI0_SEL>,
344			 <&pericfg CLK_PERI_SPI0>;
345		clock-names = "parent-clk", "sel-clk", "spi-clk";
346		status = "disabled";
347	};
348
349	thermal: thermal@1100b000 {
350		#thermal-sensor-cells = <0>;
351		compatible = "mediatek,mt2701-thermal";
352		reg = <0 0x1100b000 0 0x1000>;
353		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;
354		clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
355		clock-names = "therm", "auxadc";
356		resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
357		reset-names = "therm";
358		mediatek,auxadc = <&auxadc>;
359		mediatek,apmixedsys = <&apmixedsys>;
360	};
361
362	nandc: nand-controller@1100d000 {
363		compatible = "mediatek,mt2701-nfc";
364		reg = <0 0x1100d000 0 0x1000>;
365		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
366		clocks = <&pericfg CLK_PERI_NFI>,
367			 <&pericfg CLK_PERI_NFI_PAD>;
368		clock-names = "nfi_clk", "pad_clk";
369		status = "disabled";
370		ecc-engine = <&bch>;
371		#address-cells = <1>;
372		#size-cells = <0>;
373	};
374
375	bch: ecc@1100e000 {
376		compatible = "mediatek,mt2701-ecc";
377		reg = <0 0x1100e000 0 0x1000>;
378		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
379		clocks = <&pericfg CLK_PERI_NFI_ECC>;
380		clock-names = "nfiecc_clk";
381		status = "disabled";
382	};
383
384	nor_flash: spi@11014000 {
385		compatible = "mediatek,mt2701-nor",
386			     "mediatek,mt8173-nor";
387		reg = <0 0x11014000 0 0xe0>;
388		clocks = <&pericfg CLK_PERI_FLASH>,
389			 <&topckgen CLK_TOP_FLASH_SEL>;
390		clock-names = "spi", "sf";
391		#address-cells = <1>;
392		#size-cells = <0>;
393		status = "disabled";
394	};
395
396	spi1: spi@11016000 {
397		compatible = "mediatek,mt2701-spi";
398		#address-cells = <1>;
399		#size-cells = <0>;
400		reg = <0 0x11016000 0 0x100>;
401		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
402		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
403			 <&topckgen CLK_TOP_SPI1_SEL>,
404			 <&pericfg CLK_PERI_SPI1>;
405		clock-names = "parent-clk", "sel-clk", "spi-clk";
406		status = "disabled";
407	};
408
409	spi2: spi@11017000 {
410		compatible = "mediatek,mt2701-spi";
411		#address-cells = <1>;
412		#size-cells = <0>;
413		reg = <0 0x11017000 0 0x1000>;
414		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
415		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
416			 <&topckgen CLK_TOP_SPI2_SEL>,
417			 <&pericfg CLK_PERI_SPI2>;
418		clock-names = "parent-clk", "sel-clk", "spi-clk";
419		status = "disabled";
420	};
421
422	audsys: clock-controller@11220000 {
423		compatible = "mediatek,mt2701-audsys", "syscon";
424		reg = <0 0x11220000 0 0x2000>;
425		#clock-cells = <1>;
426
427		afe: audio-controller {
428			compatible = "mediatek,mt2701-audio";
429			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
430				      <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
431			interrupt-names = "afe", "asys";
432			power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
433
434			clocks = <&infracfg CLK_INFRA_AUDIO>,
435				 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
436				 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
437				 <&topckgen CLK_TOP_AUD_48K_TIMING>,
438				 <&topckgen CLK_TOP_AUD_44K_TIMING>,
439				 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
440				 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
441				 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
442				 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
443				 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
444				 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
445				 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
446				 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
447				 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
448				 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
449				 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
450				 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
451				 <&audsys CLK_AUD_I2SO1>,
452				 <&audsys CLK_AUD_I2SO2>,
453				 <&audsys CLK_AUD_I2SO3>,
454				 <&audsys CLK_AUD_I2SO4>,
455				 <&audsys CLK_AUD_I2SIN1>,
456				 <&audsys CLK_AUD_I2SIN2>,
457				 <&audsys CLK_AUD_I2SIN3>,
458				 <&audsys CLK_AUD_I2SIN4>,
459				 <&audsys CLK_AUD_ASRCO1>,
460				 <&audsys CLK_AUD_ASRCO2>,
461				 <&audsys CLK_AUD_ASRCO3>,
462				 <&audsys CLK_AUD_ASRCO4>,
463				 <&audsys CLK_AUD_AFE>,
464				 <&audsys CLK_AUD_AFE_CONN>,
465				 <&audsys CLK_AUD_A1SYS>,
466				 <&audsys CLK_AUD_A2SYS>,
467				 <&audsys CLK_AUD_AFE_MRGIF>;
468
469			clock-names = "infra_sys_audio_clk",
470				      "top_audio_mux1_sel",
471				      "top_audio_mux2_sel",
472				      "top_audio_a1sys_hp",
473				      "top_audio_a2sys_hp",
474				      "i2s0_src_sel",
475				      "i2s1_src_sel",
476				      "i2s2_src_sel",
477				      "i2s3_src_sel",
478				      "i2s0_src_div",
479				      "i2s1_src_div",
480				      "i2s2_src_div",
481				      "i2s3_src_div",
482				      "i2s0_mclk_en",
483				      "i2s1_mclk_en",
484				      "i2s2_mclk_en",
485				      "i2s3_mclk_en",
486				      "i2so0_hop_ck",
487				      "i2so1_hop_ck",
488				      "i2so2_hop_ck",
489				      "i2so3_hop_ck",
490				      "i2si0_hop_ck",
491				      "i2si1_hop_ck",
492				      "i2si2_hop_ck",
493				      "i2si3_hop_ck",
494				      "asrc0_out_ck",
495				      "asrc1_out_ck",
496				      "asrc2_out_ck",
497				      "asrc3_out_ck",
498				      "audio_afe_pd",
499				      "audio_afe_conn_pd",
500				      "audio_a1sys_pd",
501				      "audio_a2sys_pd",
502				      "audio_mrgif_pd";
503
504			assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
505					  <&topckgen CLK_TOP_AUD_MUX2_SEL>,
506					  <&topckgen CLK_TOP_AUD_MUX1_DIV>,
507					  <&topckgen CLK_TOP_AUD_MUX2_DIV>;
508			assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
509						 <&topckgen CLK_TOP_AUD2PLL_90M>;
510			assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
511		};
512	};
513
514	mmsys: syscon@14000000 {
515		compatible = "mediatek,mt2701-mmsys", "syscon";
516		reg = <0 0x14000000 0 0x1000>;
517		#clock-cells = <1>;
518	};
519
520	bls: pwm@1400a000 {
521		compatible = "mediatek,mt2701-disp-pwm";
522		reg = <0 0x1400a000 0 0x1000>;
523		#pwm-cells = <2>;
524		clocks = <&mmsys CLK_MM_MDP_BLS_26M>, <&mmsys CLK_MM_DISP_BLS>;
525		clock-names = "main", "mm";
526		status = "disabled";
527	};
528
529	larb0: larb@14010000 {
530		compatible = "mediatek,mt2701-smi-larb";
531		reg = <0 0x14010000 0 0x1000>;
532		mediatek,smi = <&smi_common>;
533		mediatek,larb-id = <0>;
534		clocks = <&mmsys CLK_MM_SMI_LARB0>,
535			 <&mmsys CLK_MM_SMI_LARB0>;
536		clock-names = "apb", "smi";
537		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
538	};
539
540	imgsys: syscon@15000000 {
541		compatible = "mediatek,mt2701-imgsys", "syscon";
542		reg = <0 0x15000000 0 0x1000>;
543		#clock-cells = <1>;
544	};
545
546	larb2: larb@15001000 {
547		compatible = "mediatek,mt2701-smi-larb";
548		reg = <0 0x15001000 0 0x1000>;
549		mediatek,smi = <&smi_common>;
550		mediatek,larb-id = <2>;
551		clocks = <&imgsys CLK_IMG_SMI_COMM>,
552			 <&imgsys CLK_IMG_SMI_COMM>;
553		clock-names = "apb", "smi";
554		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
555	};
556
557	jpegdec: jpegdec@15004000 {
558		compatible = "mediatek,mt2701-jpgdec";
559		reg = <0 0x15004000 0 0x1000>;
560		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
561		clocks = <&imgsys CLK_IMG_JPGDEC_SMI>,
562			  <&imgsys CLK_IMG_JPGDEC>;
563		clock-names = "jpgdec-smi",
564			      "jpgdec";
565		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
566		iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
567			 <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
568	};
569
570	jpegenc: jpegenc@1500a000 {
571		compatible = "mediatek,mt2701-jpgenc",
572			     "mediatek,mtk-jpgenc";
573		reg = <0 0x1500a000 0 0x1000>;
574		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;
575		clocks = <&imgsys CLK_IMG_VENC>;
576		clock-names = "jpgenc";
577		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
578		iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>,
579			 <&iommu MT2701_M4U_PORT_JPGENC_BSDMA>;
580	};
581
582	vdecsys: syscon@16000000 {
583		compatible = "mediatek,mt2701-vdecsys", "syscon";
584		reg = <0 0x16000000 0 0x1000>;
585		#clock-cells = <1>;
586	};
587
588	larb1: larb@16010000 {
589		compatible = "mediatek,mt2701-smi-larb";
590		reg = <0 0x16010000 0 0x1000>;
591		mediatek,smi = <&smi_common>;
592		mediatek,larb-id = <1>;
593		clocks = <&vdecsys CLK_VDEC_CKGEN>,
594			 <&vdecsys CLK_VDEC_LARB>;
595		clock-names = "apb", "smi";
596		power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
597	};
598
599	hifsys: syscon@1a000000 {
600		compatible = "mediatek,mt2701-hifsys", "syscon";
601		reg = <0 0x1a000000 0 0x1000>;
602		#clock-cells = <1>;
603		#reset-cells = <1>;
604	};
605
606	usb0: usb@1a1c0000 {
607		compatible = "mediatek,mt2701-xhci", "mediatek,mtk-xhci";
608		reg = <0 0x1a1c0000 0 0x1000>,
609		      <0 0x1a1c4700 0 0x0100>;
610		reg-names = "mac", "ippc";
611		interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
612		clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
613			 <&topckgen CLK_TOP_ETHIF_SEL>;
614		clock-names = "sys_ck", "ref_ck";
615		power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
616		phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
617		status = "disabled";
618	};
619
620	u3phy0: t-phy@1a1c4000 {
621		compatible = "mediatek,mt2701-tphy",
622			     "mediatek,generic-tphy-v1";
623		reg = <0 0x1a1c4000 0 0x0700>;
624		#address-cells = <2>;
625		#size-cells = <2>;
626		ranges;
627		status = "disabled";
628
629		u2port0: usb-phy@1a1c4800 {
630			reg = <0 0x1a1c4800 0 0x0100>;
631			clocks = <&topckgen CLK_TOP_USB_PHY48M>;
632			clock-names = "ref";
633			#phy-cells = <1>;
634			status = "okay";
635		};
636
637		u3port0: usb-phy@1a1c4900 {
638			reg = <0 0x1a1c4900 0 0x0700>;
639			clocks = <&clk26m>;
640			clock-names = "ref";
641			#phy-cells = <1>;
642			status = "okay";
643		};
644	};
645
646	usb1: usb@1a240000 {
647		compatible = "mediatek,mt2701-xhci", "mediatek,mtk-xhci";
648		reg = <0 0x1a240000 0 0x1000>,
649		      <0 0x1a244700 0 0x0100>;
650		reg-names = "mac", "ippc";
651		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
652		clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
653			 <&topckgen CLK_TOP_ETHIF_SEL>;
654		clock-names = "sys_ck", "ref_ck";
655		power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
656		phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
657		status = "disabled";
658	};
659
660	u3phy1: t-phy@1a244000 {
661		compatible = "mediatek,mt2701-tphy",
662			     "mediatek,generic-tphy-v1";
663		reg = <0 0x1a244000 0 0x0700>;
664		#address-cells = <2>;
665		#size-cells = <2>;
666		ranges;
667		status = "disabled";
668
669		u2port1: usb-phy@1a244800 {
670			reg = <0 0x1a244800 0 0x0100>;
671			clocks = <&topckgen CLK_TOP_USB_PHY48M>;
672			clock-names = "ref";
673			#phy-cells = <1>;
674			status = "okay";
675		};
676
677		u3port1: usb-phy@1a244900 {
678			reg = <0 0x1a244900 0 0x0700>;
679			clocks = <&clk26m>;
680			clock-names = "ref";
681			#phy-cells = <1>;
682			status = "okay";
683		};
684	};
685
686	usb2: usb@11200000 {
687		compatible = "mediatek,mt2701-musb",
688			     "mediatek,mtk-musb";
689		reg = <0 0x11200000 0 0x1000>;
690		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
691		interrupt-names = "mc";
692		phys = <&u2port2 PHY_TYPE_USB2>;
693		dr_mode = "otg";
694		clocks = <&pericfg CLK_PERI_USB0>,
695			 <&pericfg CLK_PERI_USB0_MCU>,
696			 <&pericfg CLK_PERI_USB_SLV>;
697		clock-names = "main","mcu","univpll";
698		power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
699		status = "disabled";
700	};
701
702	u2phy0: t-phy@11210000 {
703		compatible = "mediatek,mt2701-tphy",
704			     "mediatek,generic-tphy-v1";
705		reg = <0 0x11210000 0 0x0800>;
706		#address-cells = <2>;
707		#size-cells = <2>;
708		ranges;
709		status = "okay";
710
711		u2port2: usb-phy@1a1c4800 {
712			reg = <0 0x11210800 0 0x0100>;
713			clocks = <&topckgen CLK_TOP_USB_PHY48M>;
714			clock-names = "ref";
715			#phy-cells = <1>;
716			status = "okay";
717		};
718	};
719
720	ethsys: syscon@1b000000 {
721		compatible = "mediatek,mt2701-ethsys", "syscon";
722		reg = <0 0x1b000000 0 0x1000>;
723		#clock-cells = <1>;
724		#reset-cells = <1>;
725	};
726
727	eth: ethernet@1b100000 {
728		compatible = "mediatek,mt2701-eth", "syscon";
729		reg = <0 0x1b100000 0 0x20000>;
730		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
731			     <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
732			     <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
733		clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
734			 <&ethsys CLK_ETHSYS_ESW>,
735			 <&ethsys CLK_ETHSYS_GP1>,
736			 <&ethsys CLK_ETHSYS_GP2>,
737			 <&apmixedsys CLK_APMIXED_TRGPLL>;
738		clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
739		resets = <&ethsys MT2701_ETHSYS_FE_RST>,
740			 <&ethsys MT2701_ETHSYS_GMAC_RST>,
741			 <&ethsys MT2701_ETHSYS_PPE_RST>;
742		reset-names = "fe", "gmac", "ppe";
743		power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
744		mediatek,ethsys = <&ethsys>;
745		mediatek,pctl = <&syscfg_pctl_a>;
746		#address-cells = <1>;
747		#size-cells = <0>;
748		status = "disabled";
749	};
750
751	bdpsys: syscon@1c000000 {
752		compatible = "mediatek,mt2701-bdpsys", "syscon";
753		reg = <0 0x1c000000 0 0x1000>;
754		#clock-cells = <1>;
755	};
756};
757