1f126890aSEmmanuel Vadot// SPDX-License-Identifier: GPL-2.0 2f126890aSEmmanuel Vadot#include "tegra30.dtsi" 3f126890aSEmmanuel Vadot 4f126890aSEmmanuel Vadot/* 5f126890aSEmmanuel Vadot * Toradex Apalis T30 Module Device Tree 6f126890aSEmmanuel Vadot * Compatible for Revisions 1GB: V1.0A; 2GB: V1.0B, V1.0C, V1.0E 7f126890aSEmmanuel Vadot */ 8f126890aSEmmanuel Vadot/ { 9f126890aSEmmanuel Vadot memory@80000000 { 10f126890aSEmmanuel Vadot reg = <0x80000000 0x40000000>; 11f126890aSEmmanuel Vadot }; 12f126890aSEmmanuel Vadot 13f126890aSEmmanuel Vadot pcie@3000 { 14f126890aSEmmanuel Vadot status = "okay"; 15f126890aSEmmanuel Vadot avdd-pexa-supply = <&vdd2_reg>; 16f126890aSEmmanuel Vadot avdd-pexb-supply = <&vdd2_reg>; 17f126890aSEmmanuel Vadot avdd-pex-pll-supply = <&vdd2_reg>; 18f126890aSEmmanuel Vadot avdd-plle-supply = <&ldo6_reg>; 19f126890aSEmmanuel Vadot hvdd-pex-supply = <®_module_3v3>; 20f126890aSEmmanuel Vadot vddio-pex-ctl-supply = <®_module_3v3>; 21f126890aSEmmanuel Vadot vdd-pexa-supply = <&vdd2_reg>; 22f126890aSEmmanuel Vadot vdd-pexb-supply = <&vdd2_reg>; 23f126890aSEmmanuel Vadot 24f126890aSEmmanuel Vadot /* Apalis type specific */ 25f126890aSEmmanuel Vadot pci@1,0 { 26f126890aSEmmanuel Vadot nvidia,num-lanes = <4>; 27f126890aSEmmanuel Vadot }; 28f126890aSEmmanuel Vadot 29f126890aSEmmanuel Vadot /* Apalis PCIe */ 30f126890aSEmmanuel Vadot pci@2,0 { 31f126890aSEmmanuel Vadot nvidia,num-lanes = <1>; 32f126890aSEmmanuel Vadot }; 33f126890aSEmmanuel Vadot 34f126890aSEmmanuel Vadot /* I210/I211 Gigabit Ethernet Controller (on-module) */ 35f126890aSEmmanuel Vadot pci@3,0 { 36f126890aSEmmanuel Vadot status = "okay"; 37f126890aSEmmanuel Vadot nvidia,num-lanes = <1>; 38f126890aSEmmanuel Vadot 39f126890aSEmmanuel Vadot ethernet@0,0 { 40f126890aSEmmanuel Vadot reg = <0 0 0 0 0>; 41f126890aSEmmanuel Vadot local-mac-address = [00 00 00 00 00 00]; 42f126890aSEmmanuel Vadot }; 43f126890aSEmmanuel Vadot }; 44f126890aSEmmanuel Vadot }; 45f126890aSEmmanuel Vadot 46f126890aSEmmanuel Vadot host1x@50000000 { 47f126890aSEmmanuel Vadot hdmi@54280000 { 48f126890aSEmmanuel Vadot nvidia,ddc-i2c-bus = <&hdmi_ddc>; 49f126890aSEmmanuel Vadot nvidia,hpd-gpio = 50f126890aSEmmanuel Vadot <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; 51f126890aSEmmanuel Vadot pll-supply = <®_1v8_avdd_hdmi_pll>; 52f126890aSEmmanuel Vadot vdd-supply = <®_3v3_avdd_hdmi>; 53f126890aSEmmanuel Vadot }; 54f126890aSEmmanuel Vadot }; 55f126890aSEmmanuel Vadot 56f126890aSEmmanuel Vadot pinmux@70000868 { 57f126890aSEmmanuel Vadot pinctrl-names = "default"; 58f126890aSEmmanuel Vadot pinctrl-0 = <&state_default>; 59f126890aSEmmanuel Vadot 60f126890aSEmmanuel Vadot state_default: pinmux { 61f126890aSEmmanuel Vadot /* Analogue Audio (On-module) */ 62f126890aSEmmanuel Vadot clk1-out-pw4 { 63f126890aSEmmanuel Vadot nvidia,pins = "clk1_out_pw4"; 64f126890aSEmmanuel Vadot nvidia,function = "extperiph1"; 65f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 66f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 67f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 68f126890aSEmmanuel Vadot }; 69f126890aSEmmanuel Vadot dap3-fs-pp0 { 70f126890aSEmmanuel Vadot nvidia,pins = "dap3_fs_pp0", 71f126890aSEmmanuel Vadot "dap3_sclk_pp3", 72f126890aSEmmanuel Vadot "dap3_din_pp1", 73f126890aSEmmanuel Vadot "dap3_dout_pp2"; 74f126890aSEmmanuel Vadot nvidia,function = "i2s2"; 75f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 76f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 77f126890aSEmmanuel Vadot }; 78f126890aSEmmanuel Vadot 79f126890aSEmmanuel Vadot /* Apalis BKL1_ON */ 80f126890aSEmmanuel Vadot pv2 { 81f126890aSEmmanuel Vadot nvidia,pins = "pv2"; 82f126890aSEmmanuel Vadot nvidia,function = "rsvd4"; 83f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 84f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 85f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 86f126890aSEmmanuel Vadot }; 87f126890aSEmmanuel Vadot 88f126890aSEmmanuel Vadot /* Apalis BKL1_PWM */ 89f126890aSEmmanuel Vadot uart3-rts-n-pc0 { 90f126890aSEmmanuel Vadot nvidia,pins = "uart3_rts_n_pc0"; 91f126890aSEmmanuel Vadot nvidia,function = "pwm0"; 92f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 93f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 94f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 95f126890aSEmmanuel Vadot }; 96f126890aSEmmanuel Vadot /* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */ 97f126890aSEmmanuel Vadot uart3-cts-n-pa1 { 98f126890aSEmmanuel Vadot nvidia,pins = "uart3_cts_n_pa1"; 99f126890aSEmmanuel Vadot nvidia,function = "rsvd2"; 100f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 101f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 102f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 103f126890aSEmmanuel Vadot }; 104f126890aSEmmanuel Vadot 105f126890aSEmmanuel Vadot /* Apalis CAN1 on SPI6 */ 106f126890aSEmmanuel Vadot spi2-cs0-n-px3 { 107f126890aSEmmanuel Vadot nvidia,pins = "spi2_cs0_n_px3", 108f126890aSEmmanuel Vadot "spi2_miso_px1", 109f126890aSEmmanuel Vadot "spi2_mosi_px0", 110f126890aSEmmanuel Vadot "spi2_sck_px2"; 111f126890aSEmmanuel Vadot nvidia,function = "spi6"; 112f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 113f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 114f126890aSEmmanuel Vadot }; 115f126890aSEmmanuel Vadot /* CAN_INT1 */ 116f126890aSEmmanuel Vadot spi2-cs1-n-pw2 { 117f126890aSEmmanuel Vadot nvidia,pins = "spi2_cs1_n_pw2"; 118f126890aSEmmanuel Vadot nvidia,function = "spi3"; 119f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 120f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 121f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 122f126890aSEmmanuel Vadot }; 123f126890aSEmmanuel Vadot 124f126890aSEmmanuel Vadot /* Apalis CAN2 on SPI4 */ 125f126890aSEmmanuel Vadot gmi-a16-pj7 { 126f126890aSEmmanuel Vadot nvidia,pins = "gmi_a16_pj7", 127f126890aSEmmanuel Vadot "gmi_a17_pb0", 128f126890aSEmmanuel Vadot "gmi_a18_pb1", 129f126890aSEmmanuel Vadot "gmi_a19_pk7"; 130f126890aSEmmanuel Vadot nvidia,function = "spi4"; 131f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 132f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 133f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 134f126890aSEmmanuel Vadot }; 135f126890aSEmmanuel Vadot /* CAN_INT2 */ 136f126890aSEmmanuel Vadot spi2-cs2-n-pw3 { 137f126890aSEmmanuel Vadot nvidia,pins = "spi2_cs2_n_pw3"; 138f126890aSEmmanuel Vadot nvidia,function = "spi3"; 139f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 140f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 141f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 142f126890aSEmmanuel Vadot }; 143f126890aSEmmanuel Vadot 144f126890aSEmmanuel Vadot /* Apalis Digital Audio */ 145f126890aSEmmanuel Vadot clk1-req-pee2 { 146f126890aSEmmanuel Vadot nvidia,pins = "clk1_req_pee2"; 147f126890aSEmmanuel Vadot nvidia,function = "hda"; 148f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 149f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 150f126890aSEmmanuel Vadot }; 151f126890aSEmmanuel Vadot clk2-out-pw5 { 152f126890aSEmmanuel Vadot nvidia,pins = "clk2_out_pw5"; 153f126890aSEmmanuel Vadot nvidia,function = "extperiph2"; 154f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 155f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 156f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 157f126890aSEmmanuel Vadot }; 158f126890aSEmmanuel Vadot dap1-fs-pn0 { 159f126890aSEmmanuel Vadot nvidia,pins = "dap1_fs_pn0", 160f126890aSEmmanuel Vadot "dap1_din_pn1", 161f126890aSEmmanuel Vadot "dap1_dout_pn2", 162f126890aSEmmanuel Vadot "dap1_sclk_pn3"; 163f126890aSEmmanuel Vadot nvidia,function = "hda"; 164f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 165f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 166f126890aSEmmanuel Vadot }; 167f126890aSEmmanuel Vadot 168f126890aSEmmanuel Vadot /* Apalis GPIO */ 169f126890aSEmmanuel Vadot kb-col0-pq0 { 170f126890aSEmmanuel Vadot nvidia,pins = "kb_col0_pq0", 171f126890aSEmmanuel Vadot "kb_col1_pq1", 172f126890aSEmmanuel Vadot "kb_row10_ps2", 173f126890aSEmmanuel Vadot "kb_row11_ps3", 174f126890aSEmmanuel Vadot "kb_row12_ps4", 175f126890aSEmmanuel Vadot "kb_row13_ps5", 176f126890aSEmmanuel Vadot "kb_row14_ps6", 177f126890aSEmmanuel Vadot "kb_row15_ps7"; 178f126890aSEmmanuel Vadot nvidia,function = "kbc"; 179f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 180f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 181f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 182f126890aSEmmanuel Vadot }; 183f126890aSEmmanuel Vadot /* Multiplexed and therefore disabled */ 184f126890aSEmmanuel Vadot owr { 185f126890aSEmmanuel Vadot nvidia,pins = "owr"; 186f126890aSEmmanuel Vadot nvidia,function = "rsvd3"; 187f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 188f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_ENABLE>; 189f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 190f126890aSEmmanuel Vadot }; 191f126890aSEmmanuel Vadot 192f126890aSEmmanuel Vadot /* Apalis HDMI1 */ 193f126890aSEmmanuel Vadot hdmi-cec-pee3 { 194f126890aSEmmanuel Vadot nvidia,pins = "hdmi_cec_pee3"; 195f126890aSEmmanuel Vadot nvidia,function = "cec"; 196f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 197f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 198f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 199f126890aSEmmanuel Vadot nvidia,open-drain = <TEGRA_PIN_DISABLE>; 200f126890aSEmmanuel Vadot }; 201f126890aSEmmanuel Vadot hdmi-int-pn7 { 202f126890aSEmmanuel Vadot nvidia,pins = "hdmi_int_pn7"; 203f126890aSEmmanuel Vadot nvidia,function = "hdmi"; 204f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 205f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_ENABLE>; 206f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 207f126890aSEmmanuel Vadot }; 208f126890aSEmmanuel Vadot 209f126890aSEmmanuel Vadot /* Apalis I2C1 */ 210f126890aSEmmanuel Vadot gen1-i2c-scl-pc4 { 211f126890aSEmmanuel Vadot nvidia,pins = "gen1_i2c_scl_pc4", 212f126890aSEmmanuel Vadot "gen1_i2c_sda_pc5"; 213f126890aSEmmanuel Vadot nvidia,function = "i2c1"; 214f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 215f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 216f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 217f126890aSEmmanuel Vadot nvidia,open-drain = <TEGRA_PIN_ENABLE>; 218f126890aSEmmanuel Vadot }; 219f126890aSEmmanuel Vadot 220f126890aSEmmanuel Vadot /* Apalis I2C2 (DDC) */ 221f126890aSEmmanuel Vadot ddc-scl-pv4 { 222f126890aSEmmanuel Vadot nvidia,pins = "ddc_scl_pv4", 223f126890aSEmmanuel Vadot "ddc_sda_pv5"; 224f126890aSEmmanuel Vadot nvidia,function = "i2c4"; 225f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 226f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 227f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 228f126890aSEmmanuel Vadot }; 229f126890aSEmmanuel Vadot 230f126890aSEmmanuel Vadot /* Apalis I2C3 (CAM) */ 231f126890aSEmmanuel Vadot cam-i2c-scl-pbb1 { 232f126890aSEmmanuel Vadot nvidia,pins = "cam_i2c_scl_pbb1", 233f126890aSEmmanuel Vadot "cam_i2c_sda_pbb2"; 234f126890aSEmmanuel Vadot nvidia,function = "i2c3"; 235f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 236f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 237f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 238f126890aSEmmanuel Vadot nvidia,open-drain = <TEGRA_PIN_ENABLE>; 239f126890aSEmmanuel Vadot }; 240f126890aSEmmanuel Vadot 241f126890aSEmmanuel Vadot /* Apalis LCD1 */ 242f126890aSEmmanuel Vadot lcd-d0-pe0 { 243f126890aSEmmanuel Vadot nvidia,pins = "lcd_d0_pe0", 244f126890aSEmmanuel Vadot "lcd_d1_pe1", 245f126890aSEmmanuel Vadot "lcd_d2_pe2", 246f126890aSEmmanuel Vadot "lcd_d3_pe3", 247f126890aSEmmanuel Vadot "lcd_d4_pe4", 248f126890aSEmmanuel Vadot "lcd_d5_pe5", 249f126890aSEmmanuel Vadot "lcd_d6_pe6", 250f126890aSEmmanuel Vadot "lcd_d7_pe7", 251f126890aSEmmanuel Vadot "lcd_d8_pf0", 252f126890aSEmmanuel Vadot "lcd_d9_pf1", 253f126890aSEmmanuel Vadot "lcd_d10_pf2", 254f126890aSEmmanuel Vadot "lcd_d11_pf3", 255f126890aSEmmanuel Vadot "lcd_d12_pf4", 256f126890aSEmmanuel Vadot "lcd_d13_pf5", 257f126890aSEmmanuel Vadot "lcd_d14_pf6", 258f126890aSEmmanuel Vadot "lcd_d15_pf7", 259f126890aSEmmanuel Vadot "lcd_d16_pm0", 260f126890aSEmmanuel Vadot "lcd_d17_pm1", 261f126890aSEmmanuel Vadot "lcd_d18_pm2", 262f126890aSEmmanuel Vadot "lcd_d19_pm3", 263f126890aSEmmanuel Vadot "lcd_d20_pm4", 264f126890aSEmmanuel Vadot "lcd_d21_pm5", 265f126890aSEmmanuel Vadot "lcd_d22_pm6", 266f126890aSEmmanuel Vadot "lcd_d23_pm7", 267f126890aSEmmanuel Vadot "lcd_de_pj1", 268f126890aSEmmanuel Vadot "lcd_hsync_pj3", 269f126890aSEmmanuel Vadot "lcd_pclk_pb3", 270f126890aSEmmanuel Vadot "lcd_vsync_pj4"; 271f126890aSEmmanuel Vadot nvidia,function = "displaya"; 272f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 273f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 274f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 275f126890aSEmmanuel Vadot }; 276f126890aSEmmanuel Vadot 277f126890aSEmmanuel Vadot /* Apalis MMC1 */ 278f126890aSEmmanuel Vadot sdmmc3-clk-pa6 { 279f126890aSEmmanuel Vadot nvidia,pins = "sdmmc3_clk_pa6"; 280f126890aSEmmanuel Vadot nvidia,function = "sdmmc3"; 281f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 282f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 283f126890aSEmmanuel Vadot }; 284f126890aSEmmanuel Vadot sdmmc3-dat0-pb7 { 285f126890aSEmmanuel Vadot nvidia,pins = "sdmmc3_cmd_pa7", 286f126890aSEmmanuel Vadot "sdmmc3_dat0_pb7", 287f126890aSEmmanuel Vadot "sdmmc3_dat1_pb6", 288f126890aSEmmanuel Vadot "sdmmc3_dat2_pb5", 289f126890aSEmmanuel Vadot "sdmmc3_dat3_pb4", 290f126890aSEmmanuel Vadot "sdmmc3_dat4_pd1", 291f126890aSEmmanuel Vadot "sdmmc3_dat5_pd0", 292f126890aSEmmanuel Vadot "sdmmc3_dat6_pd3", 293f126890aSEmmanuel Vadot "sdmmc3_dat7_pd4"; 294f126890aSEmmanuel Vadot nvidia,function = "sdmmc3"; 295f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 296f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 297f126890aSEmmanuel Vadot }; 298f126890aSEmmanuel Vadot /* Apalis MMC1_CD# */ 299f126890aSEmmanuel Vadot pv3 { 300f126890aSEmmanuel Vadot nvidia,pins = "pv3"; 301f126890aSEmmanuel Vadot nvidia,function = "rsvd2"; 302f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 303f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 304f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 305f126890aSEmmanuel Vadot }; 306f126890aSEmmanuel Vadot 307f126890aSEmmanuel Vadot /* Apalis Parallel Camera */ 308f126890aSEmmanuel Vadot cam-mclk-pcc0 { 309f126890aSEmmanuel Vadot nvidia,pins = "cam_mclk_pcc0"; 310f126890aSEmmanuel Vadot nvidia,function = "vi_alt3"; 311f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 312f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 313f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 314f126890aSEmmanuel Vadot }; 315f126890aSEmmanuel Vadot vi-vsync-pd6 { 316f126890aSEmmanuel Vadot nvidia,pins = "vi_d0_pt4", 317f126890aSEmmanuel Vadot "vi_d1_pd5", 318f126890aSEmmanuel Vadot "vi_d2_pl0", 319f126890aSEmmanuel Vadot "vi_d3_pl1", 320f126890aSEmmanuel Vadot "vi_d4_pl2", 321f126890aSEmmanuel Vadot "vi_d5_pl3", 322f126890aSEmmanuel Vadot "vi_d6_pl4", 323f126890aSEmmanuel Vadot "vi_d7_pl5", 324f126890aSEmmanuel Vadot "vi_d8_pl6", 325f126890aSEmmanuel Vadot "vi_d9_pl7", 326f126890aSEmmanuel Vadot "vi_d10_pt2", 327f126890aSEmmanuel Vadot "vi_d11_pt3", 328f126890aSEmmanuel Vadot "vi_hsync_pd7", 329f126890aSEmmanuel Vadot "vi_pclk_pt0", 330f126890aSEmmanuel Vadot "vi_vsync_pd6"; 331f126890aSEmmanuel Vadot nvidia,function = "vi"; 332f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 333f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 334f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 335f126890aSEmmanuel Vadot }; 336f126890aSEmmanuel Vadot /* Multiplexed and therefore disabled */ 337f126890aSEmmanuel Vadot kb-col2-pq2 { 338f126890aSEmmanuel Vadot nvidia,pins = "kb_col2_pq2", 339f126890aSEmmanuel Vadot "kb_col3_pq3", 340f126890aSEmmanuel Vadot "kb_col4_pq4", 341f126890aSEmmanuel Vadot "kb_row4_pr4"; 342f126890aSEmmanuel Vadot nvidia,function = "rsvd4"; 343f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 344f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_ENABLE>; 345f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 346f126890aSEmmanuel Vadot }; 347f126890aSEmmanuel Vadot kb-row0-pr0 { 348f126890aSEmmanuel Vadot nvidia,pins = "kb_row0_pr0", 349f126890aSEmmanuel Vadot "kb_row1_pr1", 350f126890aSEmmanuel Vadot "kb_row2_pr2", 351f126890aSEmmanuel Vadot "kb_row3_pr3"; 352f126890aSEmmanuel Vadot nvidia,function = "rsvd3"; 353f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 354f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_ENABLE>; 355f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 356f126890aSEmmanuel Vadot }; 357f126890aSEmmanuel Vadot kb-row5-pr5 { 358f126890aSEmmanuel Vadot nvidia,pins = "kb_row5_pr5", 359f126890aSEmmanuel Vadot "kb_row6_pr6", 360f126890aSEmmanuel Vadot "kb_row7_pr7"; 361f126890aSEmmanuel Vadot nvidia,function = "kbc"; 362f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 363f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_ENABLE>; 364f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 365f126890aSEmmanuel Vadot }; 366f126890aSEmmanuel Vadot /* 367f126890aSEmmanuel Vadot * VI level-shifter direction 368f126890aSEmmanuel Vadot * (pull-down => default direction input) 369f126890aSEmmanuel Vadot */ 370f126890aSEmmanuel Vadot vi-mclk-pt1 { 371f126890aSEmmanuel Vadot nvidia,pins = "vi_mclk_pt1"; 372f126890aSEmmanuel Vadot nvidia,function = "vi_alt3"; 373f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 374f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_ENABLE>; 375f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 376f126890aSEmmanuel Vadot }; 377f126890aSEmmanuel Vadot 378f126890aSEmmanuel Vadot /* Apalis PWM1 */ 379f126890aSEmmanuel Vadot pu6 { 380f126890aSEmmanuel Vadot nvidia,pins = "pu6"; 381f126890aSEmmanuel Vadot nvidia,function = "pwm3"; 382f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 383f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 384f126890aSEmmanuel Vadot }; 385f126890aSEmmanuel Vadot 386f126890aSEmmanuel Vadot /* Apalis PWM2 */ 387f126890aSEmmanuel Vadot pu5 { 388f126890aSEmmanuel Vadot nvidia,pins = "pu5"; 389f126890aSEmmanuel Vadot nvidia,function = "pwm2"; 390f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 391f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 392f126890aSEmmanuel Vadot }; 393f126890aSEmmanuel Vadot 394f126890aSEmmanuel Vadot /* Apalis PWM3 */ 395f126890aSEmmanuel Vadot pu4 { 396f126890aSEmmanuel Vadot nvidia,pins = "pu4"; 397f126890aSEmmanuel Vadot nvidia,function = "pwm1"; 398f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 399f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 400f126890aSEmmanuel Vadot }; 401f126890aSEmmanuel Vadot 402f126890aSEmmanuel Vadot /* Apalis PWM4 */ 403f126890aSEmmanuel Vadot pu3 { 404f126890aSEmmanuel Vadot nvidia,pins = "pu3"; 405f126890aSEmmanuel Vadot nvidia,function = "pwm0"; 406f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 407f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 408f126890aSEmmanuel Vadot }; 409f126890aSEmmanuel Vadot 410f126890aSEmmanuel Vadot /* Apalis RESET_MOCI# */ 411f126890aSEmmanuel Vadot gmi-rst-n-pi4 { 412f126890aSEmmanuel Vadot nvidia,pins = "gmi_rst_n_pi4"; 413f126890aSEmmanuel Vadot nvidia,function = "gmi"; 414f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 415f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 416f126890aSEmmanuel Vadot }; 417f126890aSEmmanuel Vadot 418f126890aSEmmanuel Vadot /* Apalis SATA1_ACT# */ 419f126890aSEmmanuel Vadot pex-l0-prsnt-n-pdd0 { 420f126890aSEmmanuel Vadot nvidia,pins = "pex_l0_prsnt_n_pdd0"; 421f126890aSEmmanuel Vadot nvidia,function = "rsvd3"; 422f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 423f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 424f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 425f126890aSEmmanuel Vadot }; 426f126890aSEmmanuel Vadot 427f126890aSEmmanuel Vadot /* Apalis SD1 */ 428f126890aSEmmanuel Vadot sdmmc1-clk-pz0 { 429f126890aSEmmanuel Vadot nvidia,pins = "sdmmc1_clk_pz0"; 430f126890aSEmmanuel Vadot nvidia,function = "sdmmc1"; 431f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 432f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 433f126890aSEmmanuel Vadot }; 434f126890aSEmmanuel Vadot sdmmc1-cmd-pz1 { 435f126890aSEmmanuel Vadot nvidia,pins = "sdmmc1_cmd_pz1", 436f126890aSEmmanuel Vadot "sdmmc1_dat0_py7", 437f126890aSEmmanuel Vadot "sdmmc1_dat1_py6", 438f126890aSEmmanuel Vadot "sdmmc1_dat2_py5", 439f126890aSEmmanuel Vadot "sdmmc1_dat3_py4"; 440f126890aSEmmanuel Vadot nvidia,function = "sdmmc1"; 441f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 442f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 443f126890aSEmmanuel Vadot }; 444f126890aSEmmanuel Vadot /* Apalis SD1_CD# */ 445f126890aSEmmanuel Vadot clk2-req-pcc5 { 446f126890aSEmmanuel Vadot nvidia,pins = "clk2_req_pcc5"; 447f126890aSEmmanuel Vadot nvidia,function = "rsvd2"; 448f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 449f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 450f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 451f126890aSEmmanuel Vadot }; 452f126890aSEmmanuel Vadot 453f126890aSEmmanuel Vadot /* Apalis SPDIF1 */ 454f126890aSEmmanuel Vadot spdif-out-pk5 { 455f126890aSEmmanuel Vadot nvidia,pins = "spdif_out_pk5", 456f126890aSEmmanuel Vadot "spdif_in_pk6"; 457f126890aSEmmanuel Vadot nvidia,function = "spdif"; 458f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 459f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 460f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 461f126890aSEmmanuel Vadot }; 462f126890aSEmmanuel Vadot 463f126890aSEmmanuel Vadot /* Apalis SPI1 */ 464f126890aSEmmanuel Vadot spi1-sck-px5 { 465f126890aSEmmanuel Vadot nvidia,pins = "spi1_sck_px5", 466f126890aSEmmanuel Vadot "spi1_mosi_px4", 467f126890aSEmmanuel Vadot "spi1_miso_px7", 468f126890aSEmmanuel Vadot "spi1_cs0_n_px6"; 469f126890aSEmmanuel Vadot nvidia,function = "spi1"; 470f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 471f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 472f126890aSEmmanuel Vadot }; 473f126890aSEmmanuel Vadot 474f126890aSEmmanuel Vadot /* Apalis SPI2 */ 475f126890aSEmmanuel Vadot lcd-sck-pz4 { 476f126890aSEmmanuel Vadot nvidia,pins = "lcd_sck_pz4", 477f126890aSEmmanuel Vadot "lcd_sdout_pn5", 478f126890aSEmmanuel Vadot "lcd_sdin_pz2", 479f126890aSEmmanuel Vadot "lcd_cs0_n_pn4"; 480f126890aSEmmanuel Vadot nvidia,function = "spi5"; 481f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 482f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 483f126890aSEmmanuel Vadot }; 484f126890aSEmmanuel Vadot 485f126890aSEmmanuel Vadot /* 486f126890aSEmmanuel Vadot * Apalis TS (Low-speed type specific) 487f126890aSEmmanuel Vadot * pins may be used as GPIOs 488f126890aSEmmanuel Vadot */ 489f126890aSEmmanuel Vadot kb-col5-pq5 { 490f126890aSEmmanuel Vadot nvidia,pins = "kb_col5_pq5"; 491f126890aSEmmanuel Vadot nvidia,function = "rsvd4"; 492f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 493f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 494f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 495f126890aSEmmanuel Vadot }; 496f126890aSEmmanuel Vadot kb-col6-pq6 { 497f126890aSEmmanuel Vadot nvidia,pins = "kb_col6_pq6", 498f126890aSEmmanuel Vadot "kb_col7_pq7", 499f126890aSEmmanuel Vadot "kb_row8_ps0", 500f126890aSEmmanuel Vadot "kb_row9_ps1"; 501f126890aSEmmanuel Vadot nvidia,function = "kbc"; 502f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 503f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 504f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 505f126890aSEmmanuel Vadot }; 506f126890aSEmmanuel Vadot 507f126890aSEmmanuel Vadot /* Apalis UART1 */ 508f126890aSEmmanuel Vadot ulpi-data0 { 509f126890aSEmmanuel Vadot nvidia,pins = "ulpi_data0_po1", 510f126890aSEmmanuel Vadot "ulpi_data1_po2", 511f126890aSEmmanuel Vadot "ulpi_data2_po3", 512f126890aSEmmanuel Vadot "ulpi_data3_po4", 513f126890aSEmmanuel Vadot "ulpi_data4_po5", 514f126890aSEmmanuel Vadot "ulpi_data5_po6", 515f126890aSEmmanuel Vadot "ulpi_data6_po7", 516f126890aSEmmanuel Vadot "ulpi_data7_po0"; 517f126890aSEmmanuel Vadot nvidia,function = "uarta"; 518f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 519f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 520f126890aSEmmanuel Vadot }; 521f126890aSEmmanuel Vadot 522f126890aSEmmanuel Vadot /* Apalis UART2 */ 523f126890aSEmmanuel Vadot ulpi-clk-py0 { 524f126890aSEmmanuel Vadot nvidia,pins = "ulpi_clk_py0", 525f126890aSEmmanuel Vadot "ulpi_dir_py1", 526f126890aSEmmanuel Vadot "ulpi_nxt_py2", 527f126890aSEmmanuel Vadot "ulpi_stp_py3"; 528f126890aSEmmanuel Vadot nvidia,function = "uartd"; 529f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 530f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 531f126890aSEmmanuel Vadot }; 532f126890aSEmmanuel Vadot 533f126890aSEmmanuel Vadot /* Apalis UART3 */ 534f126890aSEmmanuel Vadot uart2-rxd-pc3 { 535f126890aSEmmanuel Vadot nvidia,pins = "uart2_rxd_pc3", 536f126890aSEmmanuel Vadot "uart2_txd_pc2"; 537f126890aSEmmanuel Vadot nvidia,function = "uartb"; 538f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 539f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 540f126890aSEmmanuel Vadot }; 541f126890aSEmmanuel Vadot 542f126890aSEmmanuel Vadot /* Apalis UART4 */ 543f126890aSEmmanuel Vadot uart3-rxd-pw7 { 544f126890aSEmmanuel Vadot nvidia,pins = "uart3_rxd_pw7", 545f126890aSEmmanuel Vadot "uart3_txd_pw6"; 546f126890aSEmmanuel Vadot nvidia,function = "uartc"; 547f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 548f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 549f126890aSEmmanuel Vadot }; 550f126890aSEmmanuel Vadot 551f126890aSEmmanuel Vadot /* Apalis USBH_EN */ 552f126890aSEmmanuel Vadot pex-l0-rst-n-pdd1 { 553f126890aSEmmanuel Vadot nvidia,pins = "pex_l0_rst_n_pdd1"; 554f126890aSEmmanuel Vadot nvidia,function = "rsvd3"; 555f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 556f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 557f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 558f126890aSEmmanuel Vadot }; 559f126890aSEmmanuel Vadot 560f126890aSEmmanuel Vadot /* Apalis USBH_OC# */ 561f126890aSEmmanuel Vadot pex-l0-clkreq-n-pdd2 { 562f126890aSEmmanuel Vadot nvidia,pins = "pex_l0_clkreq_n_pdd2"; 563f126890aSEmmanuel Vadot nvidia,function = "rsvd3"; 564f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 565f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 566f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 567f126890aSEmmanuel Vadot }; 568f126890aSEmmanuel Vadot 569f126890aSEmmanuel Vadot /* Apalis USBO1_EN */ 570f126890aSEmmanuel Vadot gen2-i2c-scl-pt5 { 571f126890aSEmmanuel Vadot nvidia,pins = "gen2_i2c_scl_pt5"; 572f126890aSEmmanuel Vadot nvidia,function = "rsvd4"; 573f126890aSEmmanuel Vadot nvidia,open-drain = <TEGRA_PIN_DISABLE>; 574f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 575f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 576f126890aSEmmanuel Vadot }; 577f126890aSEmmanuel Vadot 578f126890aSEmmanuel Vadot /* Apalis USBO1_OC# */ 579f126890aSEmmanuel Vadot gen2-i2c-sda-pt6 { 580f126890aSEmmanuel Vadot nvidia,pins = "gen2_i2c_sda_pt6"; 581f126890aSEmmanuel Vadot nvidia,function = "rsvd4"; 582f126890aSEmmanuel Vadot nvidia,open-drain = <TEGRA_PIN_DISABLE>; 583f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 584f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 585f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 586f126890aSEmmanuel Vadot }; 587f126890aSEmmanuel Vadot 588f126890aSEmmanuel Vadot /* Apalis VGA1 not supported and therefore disabled */ 589f126890aSEmmanuel Vadot crt-hsync-pv6 { 590f126890aSEmmanuel Vadot nvidia,pins = "crt_hsync_pv6", 591f126890aSEmmanuel Vadot "crt_vsync_pv7"; 592f126890aSEmmanuel Vadot nvidia,function = "rsvd2"; 593f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 594f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_ENABLE>; 595f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 596f126890aSEmmanuel Vadot }; 597f126890aSEmmanuel Vadot 598f126890aSEmmanuel Vadot /* Apalis WAKE1_MICO */ 599f126890aSEmmanuel Vadot pv1 { 600f126890aSEmmanuel Vadot nvidia,pins = "pv1"; 601f126890aSEmmanuel Vadot nvidia,function = "rsvd1"; 602f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 603f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 604f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 605f126890aSEmmanuel Vadot }; 606f126890aSEmmanuel Vadot 607f126890aSEmmanuel Vadot /* eMMC (On-module) */ 608f126890aSEmmanuel Vadot sdmmc4-clk-pcc4 { 609f126890aSEmmanuel Vadot nvidia,pins = "sdmmc4_clk_pcc4", 610f126890aSEmmanuel Vadot "sdmmc4_cmd_pt7", 611f126890aSEmmanuel Vadot "sdmmc4_rst_n_pcc3"; 612f126890aSEmmanuel Vadot nvidia,function = "sdmmc4"; 613f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 614f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 615f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 616f126890aSEmmanuel Vadot }; 617f126890aSEmmanuel Vadot sdmmc4-dat0-paa0 { 618f126890aSEmmanuel Vadot nvidia,pins = "sdmmc4_dat0_paa0", 619f126890aSEmmanuel Vadot "sdmmc4_dat1_paa1", 620f126890aSEmmanuel Vadot "sdmmc4_dat2_paa2", 621f126890aSEmmanuel Vadot "sdmmc4_dat3_paa3", 622f126890aSEmmanuel Vadot "sdmmc4_dat4_paa4", 623f126890aSEmmanuel Vadot "sdmmc4_dat5_paa5", 624f126890aSEmmanuel Vadot "sdmmc4_dat6_paa6", 625f126890aSEmmanuel Vadot "sdmmc4_dat7_paa7"; 626f126890aSEmmanuel Vadot nvidia,function = "sdmmc4"; 627f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 628f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 629f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 630f126890aSEmmanuel Vadot }; 631f126890aSEmmanuel Vadot 632f126890aSEmmanuel Vadot /* LAN i210/i211 DEV_OFF_N, PE_RST_N (On-module) */ 633f126890aSEmmanuel Vadot pex-l2-prsnt-n-pdd7 { 634f126890aSEmmanuel Vadot nvidia,pins = "pex_l2_prsnt_n_pdd7", 635f126890aSEmmanuel Vadot "pex_l2_rst_n_pcc6"; 636f126890aSEmmanuel Vadot nvidia,function = "pcie"; 637f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 638f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 639f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 640f126890aSEmmanuel Vadot }; 641f126890aSEmmanuel Vadot /* LAN i210/i211 PE_WAKE_N, SDP3 (On-module) */ 642f126890aSEmmanuel Vadot pex-wake-n-pdd3 { 643f126890aSEmmanuel Vadot nvidia,pins = "pex_wake_n_pdd3", 644f126890aSEmmanuel Vadot "pex_l2_clkreq_n_pcc7"; 645f126890aSEmmanuel Vadot nvidia,function = "pcie"; 646f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 647f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 648f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 649f126890aSEmmanuel Vadot }; 650f126890aSEmmanuel Vadot /* LAN i210/i211 SMB_ALERT_N (On-module) */ 651f126890aSEmmanuel Vadot sys-clk-req-pz5 { 652f126890aSEmmanuel Vadot nvidia,pins = "sys_clk_req_pz5"; 653f126890aSEmmanuel Vadot nvidia,function = "rsvd2"; 654f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 655f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 656f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 657f126890aSEmmanuel Vadot }; 658f126890aSEmmanuel Vadot 659f126890aSEmmanuel Vadot /* LVDS Transceiver Configuration */ 660f126890aSEmmanuel Vadot pbb0 { 661f126890aSEmmanuel Vadot nvidia,pins = "pbb0", 662f126890aSEmmanuel Vadot "pbb7", 663f126890aSEmmanuel Vadot "pcc1", 664f126890aSEmmanuel Vadot "pcc2"; 665f126890aSEmmanuel Vadot nvidia,function = "rsvd2"; 666f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 667f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 668f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 669f126890aSEmmanuel Vadot }; 670f126890aSEmmanuel Vadot pbb3 { 671f126890aSEmmanuel Vadot nvidia,pins = "pbb3", 672f126890aSEmmanuel Vadot "pbb4", 673f126890aSEmmanuel Vadot "pbb5", 674f126890aSEmmanuel Vadot "pbb6"; 675f126890aSEmmanuel Vadot nvidia,function = "displayb"; 676f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 677f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 678f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 679f126890aSEmmanuel Vadot }; 680f126890aSEmmanuel Vadot 681f126890aSEmmanuel Vadot /* Not connected and therefore disabled */ 682f126890aSEmmanuel Vadot clk-32k-out-pa0 { 683f126890aSEmmanuel Vadot nvidia,pins = "clk3_out_pee0", 684f126890aSEmmanuel Vadot "clk3_req_pee1", 685f126890aSEmmanuel Vadot "clk_32k_out_pa0", 686f126890aSEmmanuel Vadot "dap4_din_pp5", 687f126890aSEmmanuel Vadot "dap4_dout_pp6", 688f126890aSEmmanuel Vadot "dap4_fs_pp4", 689f126890aSEmmanuel Vadot "dap4_sclk_pp7"; 690f126890aSEmmanuel Vadot nvidia,function = "rsvd2"; 691f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 692f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_ENABLE>; 693f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 694f126890aSEmmanuel Vadot }; 695f126890aSEmmanuel Vadot dap2-fs-pa2 { 696f126890aSEmmanuel Vadot nvidia,pins = "dap2_fs_pa2", 697f126890aSEmmanuel Vadot "dap2_sclk_pa3", 698f126890aSEmmanuel Vadot "dap2_din_pa4", 699f126890aSEmmanuel Vadot "dap2_dout_pa5", 700f126890aSEmmanuel Vadot "lcd_dc0_pn6", 701f126890aSEmmanuel Vadot "lcd_m1_pw1", 702f126890aSEmmanuel Vadot "lcd_pwr1_pc1", 703f126890aSEmmanuel Vadot "pex_l1_clkreq_n_pdd6", 704f126890aSEmmanuel Vadot "pex_l1_prsnt_n_pdd4", 705f126890aSEmmanuel Vadot "pex_l1_rst_n_pdd5"; 706f126890aSEmmanuel Vadot nvidia,function = "rsvd3"; 707f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 708f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_ENABLE>; 709f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 710f126890aSEmmanuel Vadot }; 711f126890aSEmmanuel Vadot gmi-ad0-pg0 { 712f126890aSEmmanuel Vadot nvidia,pins = "gmi_ad0_pg0", 713f126890aSEmmanuel Vadot "gmi_ad2_pg2", 714f126890aSEmmanuel Vadot "gmi_ad3_pg3", 715f126890aSEmmanuel Vadot "gmi_ad4_pg4", 716f126890aSEmmanuel Vadot "gmi_ad5_pg5", 717f126890aSEmmanuel Vadot "gmi_ad6_pg6", 718f126890aSEmmanuel Vadot "gmi_ad7_pg7", 719f126890aSEmmanuel Vadot "gmi_ad8_ph0", 720f126890aSEmmanuel Vadot "gmi_ad9_ph1", 721f126890aSEmmanuel Vadot "gmi_ad10_ph2", 722f126890aSEmmanuel Vadot "gmi_ad11_ph3", 723f126890aSEmmanuel Vadot "gmi_ad12_ph4", 724f126890aSEmmanuel Vadot "gmi_ad13_ph5", 725f126890aSEmmanuel Vadot "gmi_ad14_ph6", 726f126890aSEmmanuel Vadot "gmi_ad15_ph7", 727f126890aSEmmanuel Vadot "gmi_adv_n_pk0", 728f126890aSEmmanuel Vadot "gmi_clk_pk1", 729f126890aSEmmanuel Vadot "gmi_cs4_n_pk2", 730f126890aSEmmanuel Vadot "gmi_cs2_n_pk3", 731f126890aSEmmanuel Vadot "gmi_dqs_pi2", 732f126890aSEmmanuel Vadot "gmi_iordy_pi5", 733f126890aSEmmanuel Vadot "gmi_oe_n_pi1", 734f126890aSEmmanuel Vadot "gmi_wait_pi7", 735f126890aSEmmanuel Vadot "gmi_wr_n_pi0", 736f126890aSEmmanuel Vadot "lcd_cs1_n_pw0", 737f126890aSEmmanuel Vadot "pu0", 738f126890aSEmmanuel Vadot "pu1", 739f126890aSEmmanuel Vadot "pu2"; 740f126890aSEmmanuel Vadot nvidia,function = "rsvd4"; 741f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 742f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_ENABLE>; 743f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 744f126890aSEmmanuel Vadot }; 745f126890aSEmmanuel Vadot gmi-cs0-n-pj0 { 746f126890aSEmmanuel Vadot nvidia,pins = "gmi_cs0_n_pj0", 747f126890aSEmmanuel Vadot "gmi_cs1_n_pj2", 748f126890aSEmmanuel Vadot "gmi_cs3_n_pk4"; 749f126890aSEmmanuel Vadot nvidia,function = "rsvd1"; 750f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 751f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_ENABLE>; 752f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 753f126890aSEmmanuel Vadot }; 754f126890aSEmmanuel Vadot gmi-cs6-n-pi3 { 755f126890aSEmmanuel Vadot nvidia,pins = "gmi_cs6_n_pi3"; 756f126890aSEmmanuel Vadot nvidia,function = "sata"; 757f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 758f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_ENABLE>; 759f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 760f126890aSEmmanuel Vadot }; 761f126890aSEmmanuel Vadot gmi-cs7-n-pi6 { 762f126890aSEmmanuel Vadot nvidia,pins = "gmi_cs7_n_pi6"; 763f126890aSEmmanuel Vadot nvidia,function = "gmi_alt"; 764f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 765f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_ENABLE>; 766f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 767f126890aSEmmanuel Vadot }; 768f126890aSEmmanuel Vadot lcd-pwr0-pb2 { 769f126890aSEmmanuel Vadot nvidia,pins = "lcd_pwr0_pb2", 770f126890aSEmmanuel Vadot "lcd_pwr2_pc6", 771f126890aSEmmanuel Vadot "lcd_wr_n_pz3"; 772f126890aSEmmanuel Vadot nvidia,function = "hdcp"; 773f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 774f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_ENABLE>; 775f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 776f126890aSEmmanuel Vadot }; 777f126890aSEmmanuel Vadot uart2-cts-n-pj5 { 778f126890aSEmmanuel Vadot nvidia,pins = "uart2_cts_n_pj5", 779f126890aSEmmanuel Vadot "uart2_rts_n_pj6"; 780f126890aSEmmanuel Vadot nvidia,function = "gmi"; 781f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 782f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_ENABLE>; 783f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 784f126890aSEmmanuel Vadot }; 785f126890aSEmmanuel Vadot 786f126890aSEmmanuel Vadot /* Power I2C (On-module) */ 787f126890aSEmmanuel Vadot pwr-i2c-scl-pz6 { 788f126890aSEmmanuel Vadot nvidia,pins = "pwr_i2c_scl_pz6", 789f126890aSEmmanuel Vadot "pwr_i2c_sda_pz7"; 790f126890aSEmmanuel Vadot nvidia,function = "i2cpwr"; 791f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 792f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 793f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 794f126890aSEmmanuel Vadot nvidia,open-drain = <TEGRA_PIN_ENABLE>; 795f126890aSEmmanuel Vadot }; 796f126890aSEmmanuel Vadot 797f126890aSEmmanuel Vadot /* 798f126890aSEmmanuel Vadot * THERMD_ALERT#, unlatched I2C address pin of LM95245 799f126890aSEmmanuel Vadot * temperature sensor therefore requires disabling for 800f126890aSEmmanuel Vadot * now 801f126890aSEmmanuel Vadot */ 802f126890aSEmmanuel Vadot lcd-dc1-pd2 { 803f126890aSEmmanuel Vadot nvidia,pins = "lcd_dc1_pd2"; 804f126890aSEmmanuel Vadot nvidia,function = "rsvd3"; 805f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 806f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_ENABLE>; 807f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 808f126890aSEmmanuel Vadot }; 809f126890aSEmmanuel Vadot 810f126890aSEmmanuel Vadot /* TOUCH_PEN_INT# (On-module) */ 811f126890aSEmmanuel Vadot pv0 { 812f126890aSEmmanuel Vadot nvidia,pins = "pv0"; 813f126890aSEmmanuel Vadot nvidia,function = "rsvd1"; 814f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 815f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 816f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 817f126890aSEmmanuel Vadot }; 818f126890aSEmmanuel Vadot }; 819f126890aSEmmanuel Vadot }; 820f126890aSEmmanuel Vadot 821f126890aSEmmanuel Vadot serial@70006040 { 822f126890aSEmmanuel Vadot compatible = "nvidia,tegra30-hsuart"; 823*aa1a8ff2SEmmanuel Vadot reset-names = "serial"; 824f126890aSEmmanuel Vadot /delete-property/ reg-shift; 825f126890aSEmmanuel Vadot }; 826f126890aSEmmanuel Vadot 827f126890aSEmmanuel Vadot serial@70006200 { 828f126890aSEmmanuel Vadot compatible = "nvidia,tegra30-hsuart"; 829*aa1a8ff2SEmmanuel Vadot reset-names = "serial"; 830f126890aSEmmanuel Vadot /delete-property/ reg-shift; 831f126890aSEmmanuel Vadot }; 832f126890aSEmmanuel Vadot 833f126890aSEmmanuel Vadot serial@70006300 { 834f126890aSEmmanuel Vadot compatible = "nvidia,tegra30-hsuart"; 835*aa1a8ff2SEmmanuel Vadot reset-names = "serial"; 836f126890aSEmmanuel Vadot /delete-property/ reg-shift; 837f126890aSEmmanuel Vadot }; 838f126890aSEmmanuel Vadot 839f126890aSEmmanuel Vadot hdmi_ddc: i2c@7000c700 { 840f126890aSEmmanuel Vadot clock-frequency = <10000>; 841f126890aSEmmanuel Vadot }; 842f126890aSEmmanuel Vadot 843f126890aSEmmanuel Vadot /* 844f126890aSEmmanuel Vadot * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and 845f126890aSEmmanuel Vadot * touch screen controller 846f126890aSEmmanuel Vadot */ 847f126890aSEmmanuel Vadot i2c@7000d000 { 848f126890aSEmmanuel Vadot status = "okay"; 849f126890aSEmmanuel Vadot clock-frequency = <100000>; 850f126890aSEmmanuel Vadot 851f126890aSEmmanuel Vadot /* SGTL5000 audio codec */ 852f126890aSEmmanuel Vadot sgtl5000: codec@a { 853f126890aSEmmanuel Vadot compatible = "fsl,sgtl5000"; 854f126890aSEmmanuel Vadot reg = <0x0a>; 855f126890aSEmmanuel Vadot #sound-dai-cells = <0>; 856f126890aSEmmanuel Vadot VDDA-supply = <®_module_3v3_audio>; 857f126890aSEmmanuel Vadot VDDD-supply = <®_1v8_vio>; 858f126890aSEmmanuel Vadot VDDIO-supply = <®_module_3v3>; 859f126890aSEmmanuel Vadot clocks = <&tegra_car TEGRA30_CLK_EXTERN1>; 860f126890aSEmmanuel Vadot }; 861f126890aSEmmanuel Vadot 862f126890aSEmmanuel Vadot pmic: pmic@2d { 863f126890aSEmmanuel Vadot compatible = "ti,tps65911"; 864f126890aSEmmanuel Vadot reg = <0x2d>; 865f126890aSEmmanuel Vadot 866f126890aSEmmanuel Vadot interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 867f126890aSEmmanuel Vadot #interrupt-cells = <2>; 868f126890aSEmmanuel Vadot interrupt-controller; 869f126890aSEmmanuel Vadot wakeup-source; 870f126890aSEmmanuel Vadot 871f126890aSEmmanuel Vadot ti,system-power-controller; 872f126890aSEmmanuel Vadot 873f126890aSEmmanuel Vadot #gpio-cells = <2>; 874f126890aSEmmanuel Vadot gpio-controller; 875f126890aSEmmanuel Vadot 876f126890aSEmmanuel Vadot vcc1-supply = <®_module_3v3>; 877f126890aSEmmanuel Vadot vcc2-supply = <®_module_3v3>; 878f126890aSEmmanuel Vadot vcc3-supply = <®_1v8_vio>; 879f126890aSEmmanuel Vadot vcc4-supply = <®_module_3v3>; 880f126890aSEmmanuel Vadot vcc5-supply = <®_module_3v3>; 881f126890aSEmmanuel Vadot vcc6-supply = <®_1v8_vio>; 882f126890aSEmmanuel Vadot vcc7-supply = <®_5v0_charge_pump>; 883f126890aSEmmanuel Vadot vccio-supply = <®_module_3v3>; 884f126890aSEmmanuel Vadot 885f126890aSEmmanuel Vadot regulators { 886f126890aSEmmanuel Vadot vdd1_reg: vdd1 { 887f126890aSEmmanuel Vadot regulator-name = "+V1.35_VDDIO_DDR"; 888f126890aSEmmanuel Vadot regulator-min-microvolt = <1350000>; 889f126890aSEmmanuel Vadot regulator-max-microvolt = <1350000>; 890f126890aSEmmanuel Vadot regulator-always-on; 891f126890aSEmmanuel Vadot }; 892f126890aSEmmanuel Vadot 893f126890aSEmmanuel Vadot vdd2_reg: vdd2 { 894f126890aSEmmanuel Vadot regulator-name = "+V1.05"; 895f126890aSEmmanuel Vadot regulator-min-microvolt = <1050000>; 896f126890aSEmmanuel Vadot regulator-max-microvolt = <1050000>; 897f126890aSEmmanuel Vadot }; 898f126890aSEmmanuel Vadot 899f126890aSEmmanuel Vadot vddctrl_reg: vddctrl { 900f126890aSEmmanuel Vadot regulator-name = "+V1.0_VDD_CPU"; 901f126890aSEmmanuel Vadot regulator-min-microvolt = <1150000>; 902f126890aSEmmanuel Vadot regulator-max-microvolt = <1150000>; 903f126890aSEmmanuel Vadot regulator-always-on; 904f126890aSEmmanuel Vadot }; 905f126890aSEmmanuel Vadot 906f126890aSEmmanuel Vadot reg_1v8_vio: vio { 907f126890aSEmmanuel Vadot regulator-name = "+V1.8"; 908f126890aSEmmanuel Vadot regulator-min-microvolt = <1800000>; 909f126890aSEmmanuel Vadot regulator-max-microvolt = <1800000>; 910f126890aSEmmanuel Vadot regulator-always-on; 911f126890aSEmmanuel Vadot }; 912f126890aSEmmanuel Vadot 913f126890aSEmmanuel Vadot /* LDO1: unused */ 914f126890aSEmmanuel Vadot 915f126890aSEmmanuel Vadot /* 916f126890aSEmmanuel Vadot * EN_+V3.3 switching via FET: 917f126890aSEmmanuel Vadot * +V3.3_AUDIO_AVDD_S, +V3.3 918f126890aSEmmanuel Vadot * see also +V3.3 fixed supply 919f126890aSEmmanuel Vadot */ 920f126890aSEmmanuel Vadot ldo2_reg: ldo2 { 921f126890aSEmmanuel Vadot regulator-name = "EN_+V3.3"; 922f126890aSEmmanuel Vadot regulator-min-microvolt = <3300000>; 923f126890aSEmmanuel Vadot regulator-max-microvolt = <3300000>; 924f126890aSEmmanuel Vadot regulator-always-on; 925f126890aSEmmanuel Vadot }; 926f126890aSEmmanuel Vadot 927f126890aSEmmanuel Vadot ldo3_reg: ldo3 { 928f126890aSEmmanuel Vadot regulator-name = "+V1.2_CSI"; 929f126890aSEmmanuel Vadot regulator-min-microvolt = <1200000>; 930f126890aSEmmanuel Vadot regulator-max-microvolt = <1200000>; 931f126890aSEmmanuel Vadot }; 932f126890aSEmmanuel Vadot 933f126890aSEmmanuel Vadot ldo4_reg: ldo4 { 934f126890aSEmmanuel Vadot regulator-name = "+V1.2_VDD_RTC"; 935f126890aSEmmanuel Vadot regulator-min-microvolt = <1200000>; 936f126890aSEmmanuel Vadot regulator-max-microvolt = <1200000>; 937f126890aSEmmanuel Vadot regulator-always-on; 938f126890aSEmmanuel Vadot }; 939f126890aSEmmanuel Vadot 940f126890aSEmmanuel Vadot /* 941f126890aSEmmanuel Vadot * +V2.8_AVDD_VDAC: 942f126890aSEmmanuel Vadot * only required for (unsupported) analog RGB 943f126890aSEmmanuel Vadot */ 944f126890aSEmmanuel Vadot ldo5_reg: ldo5 { 945f126890aSEmmanuel Vadot regulator-name = "+V2.8_AVDD_VDAC"; 946f126890aSEmmanuel Vadot regulator-min-microvolt = <2800000>; 947f126890aSEmmanuel Vadot regulator-max-microvolt = <2800000>; 948f126890aSEmmanuel Vadot regulator-always-on; 949f126890aSEmmanuel Vadot }; 950f126890aSEmmanuel Vadot 951f126890aSEmmanuel Vadot /* 952f126890aSEmmanuel Vadot * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V 953f126890aSEmmanuel Vadot * but LDO6 can't set voltage in 50mV 954f126890aSEmmanuel Vadot * granularity 955f126890aSEmmanuel Vadot */ 956f126890aSEmmanuel Vadot ldo6_reg: ldo6 { 957f126890aSEmmanuel Vadot regulator-name = "+V1.05_AVDD_PLLE"; 958f126890aSEmmanuel Vadot regulator-min-microvolt = <1100000>; 959f126890aSEmmanuel Vadot regulator-max-microvolt = <1100000>; 960f126890aSEmmanuel Vadot }; 961f126890aSEmmanuel Vadot 962f126890aSEmmanuel Vadot ldo7_reg: ldo7 { 963f126890aSEmmanuel Vadot regulator-name = "+V1.2_AVDD_PLL"; 964f126890aSEmmanuel Vadot regulator-min-microvolt = <1200000>; 965f126890aSEmmanuel Vadot regulator-max-microvolt = <1200000>; 966f126890aSEmmanuel Vadot regulator-always-on; 967f126890aSEmmanuel Vadot }; 968f126890aSEmmanuel Vadot 969f126890aSEmmanuel Vadot ldo8_reg: ldo8 { 970f126890aSEmmanuel Vadot regulator-name = "+V1.0_VDD_DDR_HS"; 971f126890aSEmmanuel Vadot regulator-min-microvolt = <1000000>; 972f126890aSEmmanuel Vadot regulator-max-microvolt = <1000000>; 973f126890aSEmmanuel Vadot regulator-always-on; 974f126890aSEmmanuel Vadot }; 975f126890aSEmmanuel Vadot }; 976f126890aSEmmanuel Vadot }; 977f126890aSEmmanuel Vadot 978f126890aSEmmanuel Vadot /* STMPE811 touch screen controller */ 979f126890aSEmmanuel Vadot touchscreen@41 { 980f126890aSEmmanuel Vadot compatible = "st,stmpe811"; 981f126890aSEmmanuel Vadot reg = <0x41>; 982f126890aSEmmanuel Vadot irq-gpio = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; 983f126890aSEmmanuel Vadot id = <0>; 984f126890aSEmmanuel Vadot blocks = <0x5>; 985f126890aSEmmanuel Vadot irq-trigger = <0x1>; 986f126890aSEmmanuel Vadot /* 3.25 MHz ADC clock speed */ 987f126890aSEmmanuel Vadot st,adc-freq = <1>; 988f126890aSEmmanuel Vadot /* 12-bit ADC */ 989f126890aSEmmanuel Vadot st,mod-12b = <1>; 990f126890aSEmmanuel Vadot /* internal ADC reference */ 991f126890aSEmmanuel Vadot st,ref-sel = <0>; 992f126890aSEmmanuel Vadot /* ADC converstion time: 80 clocks */ 993f126890aSEmmanuel Vadot st,sample-time = <4>; 994f126890aSEmmanuel Vadot 995f126890aSEmmanuel Vadot stmpe_adc { 996f126890aSEmmanuel Vadot compatible = "st,stmpe-adc"; 997f126890aSEmmanuel Vadot /* forbid to use ADC channels 3-0 (touch) */ 998f126890aSEmmanuel Vadot st,norequest-mask = <0x0F>; 999f126890aSEmmanuel Vadot }; 1000f126890aSEmmanuel Vadot 1001f126890aSEmmanuel Vadot stmpe_touchscreen { 1002f126890aSEmmanuel Vadot compatible = "st,stmpe-ts"; 1003f126890aSEmmanuel Vadot /* 8 sample average control */ 1004f126890aSEmmanuel Vadot st,ave-ctrl = <3>; 1005f126890aSEmmanuel Vadot /* 7 length fractional part in z */ 1006f126890aSEmmanuel Vadot st,fraction-z = <7>; 1007f126890aSEmmanuel Vadot /* 1008f126890aSEmmanuel Vadot * 50 mA typical 80 mA max touchscreen drivers 1009f126890aSEmmanuel Vadot * current limit value 1010f126890aSEmmanuel Vadot */ 1011f126890aSEmmanuel Vadot st,i-drive = <1>; 1012f126890aSEmmanuel Vadot /* 1 ms panel driver settling time */ 1013f126890aSEmmanuel Vadot st,settling = <3>; 1014f126890aSEmmanuel Vadot /* 5 ms touch detect interrupt delay */ 1015f126890aSEmmanuel Vadot st,touch-det-delay = <5>; 1016f126890aSEmmanuel Vadot }; 1017f126890aSEmmanuel Vadot }; 1018f126890aSEmmanuel Vadot 1019f126890aSEmmanuel Vadot /* 1020f126890aSEmmanuel Vadot * LM95245 temperature sensor 1021f126890aSEmmanuel Vadot * Note: OVERT1# directly connected to TPS65911 PMIC PWRDN 1022f126890aSEmmanuel Vadot */ 1023f126890aSEmmanuel Vadot temp-sensor@4c { 1024f126890aSEmmanuel Vadot compatible = "national,lm95245"; 1025f126890aSEmmanuel Vadot reg = <0x4c>; 1026f126890aSEmmanuel Vadot }; 1027f126890aSEmmanuel Vadot 1028f126890aSEmmanuel Vadot /* SW: +V1.2_VDD_CORE */ 1029f126890aSEmmanuel Vadot regulator@60 { 1030f126890aSEmmanuel Vadot compatible = "ti,tps62362"; 1031f126890aSEmmanuel Vadot reg = <0x60>; 1032f126890aSEmmanuel Vadot 1033f126890aSEmmanuel Vadot regulator-name = "tps62362-vout"; 1034f126890aSEmmanuel Vadot regulator-min-microvolt = <900000>; 1035f126890aSEmmanuel Vadot regulator-max-microvolt = <1400000>; 1036f126890aSEmmanuel Vadot regulator-boot-on; 1037f126890aSEmmanuel Vadot regulator-always-on; 1038f126890aSEmmanuel Vadot }; 1039f126890aSEmmanuel Vadot }; 1040f126890aSEmmanuel Vadot 1041f126890aSEmmanuel Vadot /* SPI4: CAN2 */ 1042f126890aSEmmanuel Vadot spi@7000da00 { 1043f126890aSEmmanuel Vadot status = "okay"; 1044f126890aSEmmanuel Vadot spi-max-frequency = <10000000>; 1045f126890aSEmmanuel Vadot 1046f126890aSEmmanuel Vadot can@1 { 1047f126890aSEmmanuel Vadot compatible = "microchip,mcp2515"; 1048f126890aSEmmanuel Vadot reg = <1>; 1049f126890aSEmmanuel Vadot clocks = <&clk16m>; 1050f126890aSEmmanuel Vadot interrupt-parent = <&gpio>; 1051f126890aSEmmanuel Vadot interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_FALLING>; 1052f126890aSEmmanuel Vadot spi-max-frequency = <10000000>; 1053f126890aSEmmanuel Vadot }; 1054f126890aSEmmanuel Vadot }; 1055f126890aSEmmanuel Vadot 1056f126890aSEmmanuel Vadot /* SPI6: CAN1 */ 1057f126890aSEmmanuel Vadot spi@7000de00 { 1058f126890aSEmmanuel Vadot status = "okay"; 1059f126890aSEmmanuel Vadot spi-max-frequency = <10000000>; 1060f126890aSEmmanuel Vadot 1061f126890aSEmmanuel Vadot can@0 { 1062f126890aSEmmanuel Vadot compatible = "microchip,mcp2515"; 1063f126890aSEmmanuel Vadot reg = <0>; 1064f126890aSEmmanuel Vadot clocks = <&clk16m>; 1065f126890aSEmmanuel Vadot interrupt-parent = <&gpio>; 1066f126890aSEmmanuel Vadot interrupts = <TEGRA_GPIO(W, 2) IRQ_TYPE_EDGE_FALLING>; 1067f126890aSEmmanuel Vadot spi-max-frequency = <10000000>; 1068f126890aSEmmanuel Vadot }; 1069f126890aSEmmanuel Vadot }; 1070f126890aSEmmanuel Vadot 1071f126890aSEmmanuel Vadot pmc@7000e400 { 1072f126890aSEmmanuel Vadot nvidia,invert-interrupt; 1073f126890aSEmmanuel Vadot nvidia,suspend-mode = <1>; 1074f126890aSEmmanuel Vadot nvidia,cpu-pwr-good-time = <5000>; 1075f126890aSEmmanuel Vadot nvidia,cpu-pwr-off-time = <5000>; 1076f126890aSEmmanuel Vadot nvidia,core-pwr-good-time = <3845 3845>; 1077f126890aSEmmanuel Vadot nvidia,core-pwr-off-time = <0>; 1078f126890aSEmmanuel Vadot nvidia,core-power-req-active-high; 1079f126890aSEmmanuel Vadot nvidia,sys-clock-req-active-high; 1080f126890aSEmmanuel Vadot 1081f126890aSEmmanuel Vadot /* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */ 1082f126890aSEmmanuel Vadot i2c-thermtrip { 1083f126890aSEmmanuel Vadot nvidia,i2c-controller-id = <4>; 1084f126890aSEmmanuel Vadot nvidia,bus-addr = <0x2d>; 1085f126890aSEmmanuel Vadot nvidia,reg-addr = <0x3f>; 1086f126890aSEmmanuel Vadot nvidia,reg-data = <0x1>; 1087f126890aSEmmanuel Vadot }; 1088f126890aSEmmanuel Vadot }; 1089f126890aSEmmanuel Vadot 1090f126890aSEmmanuel Vadot hda@70030000 { 1091f126890aSEmmanuel Vadot status = "okay"; 1092f126890aSEmmanuel Vadot }; 1093f126890aSEmmanuel Vadot 1094f126890aSEmmanuel Vadot ahub@70080000 { 1095f126890aSEmmanuel Vadot i2s@70080500 { 1096f126890aSEmmanuel Vadot status = "okay"; 1097f126890aSEmmanuel Vadot }; 1098f126890aSEmmanuel Vadot }; 1099f126890aSEmmanuel Vadot 1100f126890aSEmmanuel Vadot /* eMMC */ 1101f126890aSEmmanuel Vadot mmc@78000600 { 1102f126890aSEmmanuel Vadot status = "okay"; 1103f126890aSEmmanuel Vadot bus-width = <8>; 1104f126890aSEmmanuel Vadot non-removable; 1105f126890aSEmmanuel Vadot vmmc-supply = <®_module_3v3>; /* VCC */ 1106f126890aSEmmanuel Vadot vqmmc-supply = <®_1v8_vio>; /* VCCQ */ 1107f126890aSEmmanuel Vadot mmc-ddr-1_8v; 1108f126890aSEmmanuel Vadot }; 1109f126890aSEmmanuel Vadot 1110f126890aSEmmanuel Vadot clk16m: clock-osc4 { 1111f126890aSEmmanuel Vadot compatible = "fixed-clock"; 1112f126890aSEmmanuel Vadot #clock-cells = <0>; 1113f126890aSEmmanuel Vadot clock-frequency = <16000000>; 1114f126890aSEmmanuel Vadot }; 1115f126890aSEmmanuel Vadot 1116f126890aSEmmanuel Vadot clk32k_in: clock-xtal1 { 1117f126890aSEmmanuel Vadot compatible = "fixed-clock"; 1118f126890aSEmmanuel Vadot #clock-cells = <0>; 1119f126890aSEmmanuel Vadot clock-frequency = <32768>; 1120f126890aSEmmanuel Vadot }; 1121f126890aSEmmanuel Vadot 1122f126890aSEmmanuel Vadot reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll { 1123f126890aSEmmanuel Vadot compatible = "regulator-fixed"; 1124f126890aSEmmanuel Vadot regulator-name = "+V1.8_AVDD_HDMI_PLL"; 1125f126890aSEmmanuel Vadot regulator-min-microvolt = <1800000>; 1126f126890aSEmmanuel Vadot regulator-max-microvolt = <1800000>; 1127f126890aSEmmanuel Vadot enable-active-high; 1128f126890aSEmmanuel Vadot gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; 1129f126890aSEmmanuel Vadot vin-supply = <®_1v8_vio>; 1130f126890aSEmmanuel Vadot }; 1131f126890aSEmmanuel Vadot 1132f126890aSEmmanuel Vadot reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { 1133f126890aSEmmanuel Vadot compatible = "regulator-fixed"; 1134f126890aSEmmanuel Vadot regulator-name = "+V3.3_AVDD_HDMI"; 1135f126890aSEmmanuel Vadot regulator-min-microvolt = <3300000>; 1136f126890aSEmmanuel Vadot regulator-max-microvolt = <3300000>; 1137f126890aSEmmanuel Vadot enable-active-high; 1138f126890aSEmmanuel Vadot gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; 1139f126890aSEmmanuel Vadot vin-supply = <®_module_3v3>; 1140f126890aSEmmanuel Vadot }; 1141f126890aSEmmanuel Vadot 1142f126890aSEmmanuel Vadot reg_5v0_charge_pump: regulator-5v0-charge-pump { 1143f126890aSEmmanuel Vadot compatible = "regulator-fixed"; 1144f126890aSEmmanuel Vadot regulator-name = "+V5.0"; 1145f126890aSEmmanuel Vadot regulator-min-microvolt = <5000000>; 1146f126890aSEmmanuel Vadot regulator-max-microvolt = <5000000>; 1147f126890aSEmmanuel Vadot regulator-always-on; 1148f126890aSEmmanuel Vadot }; 1149f126890aSEmmanuel Vadot 1150f126890aSEmmanuel Vadot reg_module_3v3: regulator-module-3v3 { 1151f126890aSEmmanuel Vadot compatible = "regulator-fixed"; 1152f126890aSEmmanuel Vadot regulator-name = "+V3.3"; 1153f126890aSEmmanuel Vadot regulator-min-microvolt = <3300000>; 1154f126890aSEmmanuel Vadot regulator-max-microvolt = <3300000>; 1155f126890aSEmmanuel Vadot regulator-always-on; 1156f126890aSEmmanuel Vadot }; 1157f126890aSEmmanuel Vadot 1158f126890aSEmmanuel Vadot reg_module_3v3_audio: regulator-module-3v3-audio { 1159f126890aSEmmanuel Vadot compatible = "regulator-fixed"; 1160f126890aSEmmanuel Vadot regulator-name = "+V3.3_AUDIO_AVDD_S"; 1161f126890aSEmmanuel Vadot regulator-min-microvolt = <3300000>; 1162f126890aSEmmanuel Vadot regulator-max-microvolt = <3300000>; 1163f126890aSEmmanuel Vadot regulator-always-on; 1164f126890aSEmmanuel Vadot }; 1165f126890aSEmmanuel Vadot 1166f126890aSEmmanuel Vadot sound { 1167f126890aSEmmanuel Vadot compatible = "toradex,tegra-audio-sgtl5000-apalis_t30", 1168f126890aSEmmanuel Vadot "nvidia,tegra-audio-sgtl5000"; 1169f126890aSEmmanuel Vadot nvidia,model = "Toradex Apalis T30"; 1170f126890aSEmmanuel Vadot nvidia,audio-routing = 1171f126890aSEmmanuel Vadot "Headphone Jack", "HP_OUT", 1172f126890aSEmmanuel Vadot "LINE_IN", "Line In Jack", 1173f126890aSEmmanuel Vadot "MIC_IN", "Mic Jack"; 1174f126890aSEmmanuel Vadot nvidia,i2s-controller = <&tegra_i2s2>; 1175f126890aSEmmanuel Vadot nvidia,audio-codec = <&sgtl5000>; 1176f126890aSEmmanuel Vadot clocks = <&tegra_car TEGRA30_CLK_PLL_A>, 1177f126890aSEmmanuel Vadot <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, 1178f126890aSEmmanuel Vadot <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; 1179f126890aSEmmanuel Vadot clock-names = "pll_a", "pll_a_out0", "mclk"; 1180f126890aSEmmanuel Vadot 1181f126890aSEmmanuel Vadot assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, 1182f126890aSEmmanuel Vadot <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; 1183f126890aSEmmanuel Vadot 1184f126890aSEmmanuel Vadot assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, 1185f126890aSEmmanuel Vadot <&tegra_car TEGRA30_CLK_EXTERN1>; 1186f126890aSEmmanuel Vadot }; 1187f126890aSEmmanuel Vadot}; 1188