1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2016 Eckelmann AG.
4 * Copyright (C) 2013 Freescale Semiconductor, Inc.
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/gpio/gpio.h>
10
11#include "imx6dl.dtsi"
12
13/ {
14	model = "Eckelmann CI 4X10 Board";
15	compatible = "eckelmann,imx6dl-ci4x10", "fsl,imx6dl";
16
17	chosen {
18		stdout-path = &uart3;
19	};
20
21	memory@10000000 {
22		device_type = "memory";
23		reg = <0x10000000 0x40000000>;
24	};
25
26	rmii_clk: clock-rmii {
27		/* This clock is provided by the phy (KSZ8091RNB) */
28		compatible = "fixed-clock";
29		#clock-cells = <0>;
30		clock-frequency = <50000000>;
31		clock-output-names = "enet_ref_pad";
32	};
33
34	reg_usb_h1_vbus: regulator-usb-h1-vbus {
35		pinctrl-names = "default";
36		pinctrl-0 = <&pinctrl_reg_usb_h1_vbus>;
37		compatible = "regulator-fixed";
38		regulator-name = "usb_h1_vbus";
39		regulator-min-microvolt = <5000000>;
40		regulator-max-microvolt = <5000000>;
41		gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
42		enable-active-high;
43	};
44
45	siox {
46		compatible = "eckelmann,siox-gpio";
47		pinctrl-names = "default";
48		pinctrl-0 = <&pinctrl_siox>;
49		din-gpios = <&gpio6 11 GPIO_ACTIVE_HIGH>;
50		dout-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;
51		dclk-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>;
52		dld-gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>;
53	};
54};
55
56&can1 {
57	pinctrl-names = "default";
58	pinctrl-0 = <&pinctrl_flexcan1>;
59	status = "okay";
60};
61
62&can2 {
63	pinctrl-names = "default";
64	pinctrl-0 = <&pinctrl_flexcan2>;
65	status = "okay";
66};
67
68&clks {
69	clocks = <&rmii_clk>;
70	clock-names = "enet_ref_pad";
71	assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
72	assigned-clock-parents = <&rmii_clk>;
73};
74
75&ecspi2 {
76	pinctrl-names = "default";
77	pinctrl-0 = <&pinctrl_ecspi2>;
78	cs-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
79	status = "okay";
80
81	flash@0 {
82		compatible = "everspin,mr25h256";
83		reg = <0>;
84		spi-max-frequency = <15000000>;
85	};
86};
87
88&ecspi1 {
89	pinctrl-names = "default";
90	pinctrl-0 = <&pinctrl_ecspi1>;
91	cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
92	status = "okay";
93
94	tpm@0 {
95		compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
96		reg = <0>;
97		spi-max-frequency = <10000000>;
98	};
99};
100
101&gpio2 {
102	gpio-line-names = "buzzer", "", "", "", "", "", "", "",
103			  "", "", "", "", "", "", "", "",
104			  "", "", "", "", "", "", "", "",
105			  "", "", "", "", "", "", "", "";
106};
107
108&gpio4 {
109	gpio-line-names = "", "", "", "", "", "", "", "in2",
110			  "prio2", "prio1", "aux", "", "", "", "", "",
111			  "", "", "", "", "", "", "", "",
112			  "", "", "", "", "", "", "", "";
113};
114
115&gpio6 {
116	gpio-line-names = "", "", "", "", "", "", "", "",
117			  "", "", "", "", "", "", "", "in1",
118			  "", "", "", "", "", "", "", "",
119			  "", "", "", "", "", "", "", "";
120};
121
122&i2c1 {
123	pinctrl-names = "default";
124	pinctrl-0 = <&pinctrl_i2c1>;
125	status = "okay";
126
127	temperature-sensor@49 {
128		compatible = "ad,ad7414";
129		reg = <0x49>;
130	};
131
132	rtc@51 {
133		compatible = "nxp,pcf2127";
134		reg = <0x51>;
135	};
136};
137
138&iomuxc {
139	pinctrl-names = "default";
140	pinctrl-0 = <&pinctrl_hog>;
141
142	pinctrl_hog: hog {
143		fsl,pins = <
144			MX6QDL_PAD_NANDF_D0__GPIO2_IO00		0x00000018 /* buzzer */
145			MX6QDL_PAD_KEY_COL1__GPIO4_IO08		0x00000018 /* OUT_1 */
146			MX6QDL_PAD_KEY_ROW1__GPIO4_IO09		0x00000018 /* OUT_2 */
147			MX6QDL_PAD_KEY_COL2__GPIO4_IO10		0x00000018 /* OUT_3 */
148			MX6QDL_PAD_NANDF_CS2__GPIO6_IO15	0x00000000 /* In1 */
149			MX6QDL_PAD_KEY_ROW0__GPIO4_IO07		0x00000000 /* In2 */
150			MX6QDL_PAD_GPIO_9__GPIO1_IO09		0x00000018 /* unused watchdog pin */
151			MX6QDL_PAD_SD1_DAT2__GPIO1_IO19		0x00000018 /* unused watchdog pin */
152
153		>;
154	};
155
156	pinctrl_ecspi1: ecspi1grp {
157		fsl,pins = <
158			MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 	0x000100a0
159			MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI	0x000100a0
160			MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO	0x000100a0
161			MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25	0x000100a0
162		>;
163	};
164
165	pinctrl_ecspi2: ecspi2grp {
166		fsl,pins = <
167			MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK	0x000100b1
168			MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI		0x000100b1
169			MX6QDL_PAD_EIM_OE__ECSPI2_MISO		0x000100b1
170			MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12	0x000100b1
171		>;
172	};
173
174	pinctrl_enet: enetgrp {
175		fsl,pins = <
176			MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
177			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x0001b098
178			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x0001b098
179			MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0	0x0001b098
180			MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1	0x0001b098
181			MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN	0x0001b098
182			MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER	0x0001b0b0
183			MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0	0x0001b0b0
184			MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1	0x0001b0b0
185			MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN	0x0001b0b0
186			MX6QDL_PAD_SD1_CMD__GPIO1_IO18		0x00000018
187		>;
188	};
189
190	pinctrl_flexcan1: flexcan1grp {
191		fsl,pins = <
192			MX6QDL_PAD_GPIO_7__FLEXCAN1_TX		0x0001b020
193			MX6QDL_PAD_GPIO_8__FLEXCAN1_RX		0x0001b0b0
194		>;
195	};
196
197	pinctrl_flexcan2: flexcan2grp {
198		fsl,pins = <
199			MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX	0x0001b020
200			MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX	0x0001b0b0
201		>;
202	};
203
204	pinctrl_i2c1: i2c1grp {
205		fsl,pins = <
206			/* without SION i2c doesn't detect bus busy */
207			MX6QDL_PAD_CSI0_DAT9__I2C1_SCL		0x4001b820
208			MX6QDL_PAD_CSI0_DAT8__I2C1_SDA		0x4001b820
209		>;
210	};
211
212	pinctrl_pcie: pciegrp {
213		fsl,pins = <
214			MX6QDL_PAD_SD1_CLK__GPIO1_IO20		0x00000018
215		>;
216	};
217
218	pinctrl_reg_usb_h1_vbus: reg_usb_h1_vbusgrp {
219		fsl,pins = <
220			MX6QDL_PAD_EIM_D31__GPIO3_IO31		0x0001b0b0
221		>;
222	};
223
224	pinctrl_siox: sioxgrp {
225		fsl,pins = <
226			MX6QDL_PAD_NANDF_CS0__GPIO6_IO11	0x0001b010	/* DIN */
227			MX6QDL_PAD_NANDF_ALE__GPIO6_IO08	0x0001b010	/* DOUT */
228			MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09	0x0001b010	/* DCLK */
229			MX6QDL_PAD_NANDF_RB0__GPIO6_IO10	0x0001b010	/* DLD */
230		>;
231	};
232
233	pinctrl_uart1_dte: uart1grp {
234		fsl,pins = <
235			MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA	0x0001b010
236			MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA	0x0001b010
237			MX6QDL_PAD_EIM_D19__UART1_RTS_B 	0x0001b010
238			MX6QDL_PAD_EIM_D20__UART1_CTS_B 	0x0001b010
239			MX6QDL_PAD_EIM_D23__GPIO3_IO23		0x0001b010	/* DCD */
240			MX6QDL_PAD_EIM_D24__GPIO3_IO24		0x0001b010	/* DTR */
241			MX6QDL_PAD_EIM_D25__GPIO3_IO25		0x0001b010	/* DSR */
242		>;
243	};
244
245	pinctrl_uart2_dte: uart2grp {
246		fsl,pins = <
247			MX6QDL_PAD_EIM_D27__UART2_TX_DATA	0x0001b010
248			MX6QDL_PAD_EIM_D26__UART2_RX_DATA	0x0001b010
249			MX6QDL_PAD_EIM_D28__UART2_RTS_B 	0x0001b010
250			MX6QDL_PAD_EIM_D29__UART2_CTS_B 	0x0001b010
251			MX6QDL_PAD_NANDF_D1__GPIO2_IO01		0x0001b010	/* DCD */
252			MX6QDL_PAD_GPIO_18__GPIO7_IO13		0x0001b010	/* DTR */
253			MX6QDL_PAD_NANDF_CS3__GPIO6_IO16	0x0001b010	/* DSR */
254		>;
255	};
256
257	pinctrl_uart3_dce: uart3grp {
258		fsl,pins = <
259			MX6QDL_PAD_SD4_CLK__UART3_RX_DATA	0x0001b010
260			MX6QDL_PAD_SD4_CMD__UART3_TX_DATA	0x0001b010
261		>;
262	};
263
264	pinctrl_uart4_dce: uart4grp {
265		fsl,pins = <
266			MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA	0x0001b010
267			MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA	0x0001b010
268			MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03	0x0001b010
269		>;
270	};
271
272	pinctrl_uart5_dce: uart5grp {
273		fsl,pins = <
274			MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA	0x0001b010
275			MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA	0x0001b010
276			MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05	0x0001b010	/* RTS */
277		>;
278	};
279
280	pinctrl_usbh1: usbh1grp {
281		fsl,pins = <
282			MX6QDL_PAD_EIM_D30__USB_H1_OC		0x0001b0b0
283		>;
284	};
285
286	pinctrl_usdhc3: usdhc3grp {
287		fsl,pins = <
288			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x00017059
289			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x00010059
290			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x00017059
291			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x00017059
292			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x00017059
293			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x00017059
294			MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x00017059
295			MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x00017059
296			MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x00017059
297			MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x00017059
298		>;
299	};
300};
301
302&fec {
303	pinctrl-names = "default";
304	pinctrl-0 = <&pinctrl_enet>;
305	phy-mode = "rmii";
306	phy-reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
307	phy-handle = <&phy>;
308	status = "okay";
309
310	mdio {
311		#address-cells = <1>;
312		#size-cells = <0>;
313
314		phy: ethernet-phy@1 {
315			compatible = "ethernet-phy-ieee802.3-c22";
316			reg = <1>;
317		};
318	};
319};
320
321&pcie {
322	pinctrl-names = "default";
323	pinctrl-0 = <&pinctrl_pcie>;
324	reset-gpio = <&gpio1 20 GPIO_ACTIVE_LOW>;
325	status = "okay";
326};
327
328&uart1 {
329	pinctrl-names = "default";
330	pinctrl-0 = <&pinctrl_uart1_dte>;
331	uart-has-rtscts;
332	fsl,dte-mode;
333	dcd-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
334	dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
335	dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
336	status = "okay";
337};
338
339&uart2 {
340	pinctrl-names = "default";
341	pinctrl-0 = <&pinctrl_uart2_dte>;
342	uart-has-rtscts;
343	fsl,dte-mode;
344	dcd-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
345	dtr-gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
346	dsr-gpios = <&gpio6 16 GPIO_ACTIVE_LOW>;
347	status = "okay";
348};
349
350&uart3 {
351	pinctrl-names = "default";
352	pinctrl-0 = <&pinctrl_uart3_dce>;
353	status = "okay";
354};
355
356&uart4 {
357	pinctrl-names = "default";
358	pinctrl-0 = <&pinctrl_uart4_dce>;
359	rts-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>;
360	status = "okay";
361};
362
363&uart5 {
364	pinctrl-names = "default";
365	pinctrl-0 = <&pinctrl_uart5_dce>;
366	rts-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>;
367	status = "okay";
368};
369
370&usbh1 {
371	pinctrl-names = "default";
372	pinctrl-0 = <&pinctrl_usbh1>;
373	vbus-supply = <&reg_usb_h1_vbus>;
374	status = "okay";
375};
376
377&usbotg {
378	dr_mode = "peripheral";
379	status = "okay";
380};
381
382&usdhc3 {
383	pinctrl-names = "default";
384	pinctrl-0 = <&pinctrl_usdhc3>;
385	bus-width = <8>;
386	non-removable;
387	status = "okay";
388};
389