1*f126890aSEmmanuel Vadot// SPDX-License-Identifier: GPL-2.0-only 2*f126890aSEmmanuel Vadot/* 3*f126890aSEmmanuel Vadot * Copyright 2016-2017 4*f126890aSEmmanuel Vadot * Lukasz Majewski, DENX Software Engineering, lukma@denx.de 5*f126890aSEmmanuel Vadot */ 6*f126890aSEmmanuel Vadot 7*f126890aSEmmanuel Vadot/dts-v1/; 8*f126890aSEmmanuel Vadot 9*f126890aSEmmanuel Vadot#include "imx6q.dtsi" 10*f126890aSEmmanuel Vadot 11*f126890aSEmmanuel Vadot#include <dt-bindings/gpio/gpio.h> 12*f126890aSEmmanuel Vadot#include <dt-bindings/pwm/pwm.h> 13*f126890aSEmmanuel Vadot 14*f126890aSEmmanuel Vadot/ { 15*f126890aSEmmanuel Vadot model = "Liebherr (LWN) monitor6 i.MX6 Quad Board"; 16*f126890aSEmmanuel Vadot compatible = "lwn,mccmon6", "fsl,imx6q"; 17*f126890aSEmmanuel Vadot 18*f126890aSEmmanuel Vadot memory@10000000 { 19*f126890aSEmmanuel Vadot device_type = "memory"; 20*f126890aSEmmanuel Vadot reg = <0x10000000 0x80000000>; 21*f126890aSEmmanuel Vadot }; 22*f126890aSEmmanuel Vadot 23*f126890aSEmmanuel Vadot backlight_lvds: backlight { 24*f126890aSEmmanuel Vadot compatible = "pwm-backlight"; 25*f126890aSEmmanuel Vadot pinctrl-names = "default"; 26*f126890aSEmmanuel Vadot pinctrl-0 = <&pinctrl_backlight>; 27*f126890aSEmmanuel Vadot pwms = <&pwm2 0 5000000 PWM_POLARITY_INVERTED>; 28*f126890aSEmmanuel Vadot brightness-levels = < 0 1 2 3 4 5 6 7 8 9 29*f126890aSEmmanuel Vadot 10 11 12 13 14 15 16 17 18 19 30*f126890aSEmmanuel Vadot 20 21 22 23 24 25 26 27 28 29 31*f126890aSEmmanuel Vadot 30 31 32 33 34 35 36 37 38 39 32*f126890aSEmmanuel Vadot 40 41 42 43 44 45 46 47 48 49 33*f126890aSEmmanuel Vadot 50 51 52 53 54 55 56 57 58 59 34*f126890aSEmmanuel Vadot 60 61 62 63 64 65 66 67 68 69 35*f126890aSEmmanuel Vadot 70 71 72 73 74 75 76 77 78 79 36*f126890aSEmmanuel Vadot 80 81 82 83 84 85 86 87 88 89 37*f126890aSEmmanuel Vadot 90 91 92 93 94 95 96 97 98 99 38*f126890aSEmmanuel Vadot 100 101 102 103 104 105 106 107 108 109 39*f126890aSEmmanuel Vadot 110 111 112 113 114 115 116 117 118 119 40*f126890aSEmmanuel Vadot 120 121 122 123 124 125 126 127 128 129 41*f126890aSEmmanuel Vadot 130 131 132 133 134 135 136 137 138 139 42*f126890aSEmmanuel Vadot 140 141 142 143 144 145 146 147 148 149 43*f126890aSEmmanuel Vadot 150 151 152 153 154 155 156 157 158 159 44*f126890aSEmmanuel Vadot 160 161 162 163 164 165 166 167 168 169 45*f126890aSEmmanuel Vadot 170 171 172 173 174 175 176 177 178 179 46*f126890aSEmmanuel Vadot 180 181 182 183 184 185 186 187 188 189 47*f126890aSEmmanuel Vadot 190 191 192 193 194 195 196 197 198 199 48*f126890aSEmmanuel Vadot 200 201 202 203 204 205 206 207 208 209 49*f126890aSEmmanuel Vadot 210 211 212 213 214 215 216 217 218 219 50*f126890aSEmmanuel Vadot 220 221 222 223 224 225 226 227 228 229 51*f126890aSEmmanuel Vadot 230 231 232 233 234 235 236 237 238 239 52*f126890aSEmmanuel Vadot 240 241 242 243 244 245 246 247 248 249 53*f126890aSEmmanuel Vadot 250 251 252 253 254 255>; 54*f126890aSEmmanuel Vadot default-brightness-level = <50>; 55*f126890aSEmmanuel Vadot enable-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; 56*f126890aSEmmanuel Vadot }; 57*f126890aSEmmanuel Vadot 58*f126890aSEmmanuel Vadot reg_lvds: regulator-lvds { 59*f126890aSEmmanuel Vadot compatible = "regulator-fixed"; 60*f126890aSEmmanuel Vadot regulator-name = "lvds_ppen"; 61*f126890aSEmmanuel Vadot regulator-min-microvolt = <3300000>; 62*f126890aSEmmanuel Vadot regulator-max-microvolt = <3300000>; 63*f126890aSEmmanuel Vadot regulator-boot-on; 64*f126890aSEmmanuel Vadot pinctrl-names = "default"; 65*f126890aSEmmanuel Vadot pinctrl-0 = <&pinctrl_reg_lvds>; 66*f126890aSEmmanuel Vadot gpio = <&gpio1 19 GPIO_ACTIVE_HIGH>; 67*f126890aSEmmanuel Vadot enable-active-high; 68*f126890aSEmmanuel Vadot }; 69*f126890aSEmmanuel Vadot 70*f126890aSEmmanuel Vadot panel-lvds0 { 71*f126890aSEmmanuel Vadot compatible = "innolux,g121x1-l03"; 72*f126890aSEmmanuel Vadot backlight = <&backlight_lvds>; 73*f126890aSEmmanuel Vadot power-supply = <®_lvds>; 74*f126890aSEmmanuel Vadot 75*f126890aSEmmanuel Vadot port { 76*f126890aSEmmanuel Vadot panel_in_lvds0: endpoint { 77*f126890aSEmmanuel Vadot remote-endpoint = <&lvds0_out>; 78*f126890aSEmmanuel Vadot }; 79*f126890aSEmmanuel Vadot }; 80*f126890aSEmmanuel Vadot }; 81*f126890aSEmmanuel Vadot}; 82*f126890aSEmmanuel Vadot 83*f126890aSEmmanuel Vadot&ecspi3 { 84*f126890aSEmmanuel Vadot cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; 85*f126890aSEmmanuel Vadot pinctrl-names = "default"; 86*f126890aSEmmanuel Vadot pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs &pinctrl_ecspi3_flwp>; 87*f126890aSEmmanuel Vadot status = "okay"; 88*f126890aSEmmanuel Vadot 89*f126890aSEmmanuel Vadot s25sl032p: flash@0 { 90*f126890aSEmmanuel Vadot #address-cells = <1>; 91*f126890aSEmmanuel Vadot #size-cells = <1>; 92*f126890aSEmmanuel Vadot compatible = "jedec,spi-nor"; 93*f126890aSEmmanuel Vadot spi-max-frequency = <40000000>; 94*f126890aSEmmanuel Vadot reg = <0>; 95*f126890aSEmmanuel Vadot }; 96*f126890aSEmmanuel Vadot}; 97*f126890aSEmmanuel Vadot 98*f126890aSEmmanuel Vadot&fec { 99*f126890aSEmmanuel Vadot pinctrl-names = "default"; 100*f126890aSEmmanuel Vadot pinctrl-0 = <&pinctrl_enet>; 101*f126890aSEmmanuel Vadot phy-mode = "rgmii"; 102*f126890aSEmmanuel Vadot phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; 103*f126890aSEmmanuel Vadot /delete-property/ interrupts; 104*f126890aSEmmanuel Vadot interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, 105*f126890aSEmmanuel Vadot <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; 106*f126890aSEmmanuel Vadot fsl,err006687-workaround-present; 107*f126890aSEmmanuel Vadot status = "okay"; 108*f126890aSEmmanuel Vadot}; 109*f126890aSEmmanuel Vadot 110*f126890aSEmmanuel Vadot&i2c1 { 111*f126890aSEmmanuel Vadot clock-frequency = <100000>; 112*f126890aSEmmanuel Vadot pinctrl-names = "default"; 113*f126890aSEmmanuel Vadot pinctrl-0 = <&pinctrl_i2c1>; 114*f126890aSEmmanuel Vadot status = "okay"; 115*f126890aSEmmanuel Vadot}; 116*f126890aSEmmanuel Vadot 117*f126890aSEmmanuel Vadot&i2c2 { 118*f126890aSEmmanuel Vadot clock-frequency = <100000>; 119*f126890aSEmmanuel Vadot pinctrl-names = "default"; 120*f126890aSEmmanuel Vadot pinctrl-0 = <&pinctrl_i2c2>; 121*f126890aSEmmanuel Vadot status = "okay"; 122*f126890aSEmmanuel Vadot 123*f126890aSEmmanuel Vadot pfuze100: pmic@8 { 124*f126890aSEmmanuel Vadot compatible = "fsl,pfuze100"; 125*f126890aSEmmanuel Vadot reg = <0x08>; 126*f126890aSEmmanuel Vadot 127*f126890aSEmmanuel Vadot regulators { 128*f126890aSEmmanuel Vadot sw1a_reg: sw1ab { 129*f126890aSEmmanuel Vadot regulator-min-microvolt = <300000>; 130*f126890aSEmmanuel Vadot regulator-max-microvolt = <1875000>; 131*f126890aSEmmanuel Vadot regulator-boot-on; 132*f126890aSEmmanuel Vadot regulator-always-on; 133*f126890aSEmmanuel Vadot regulator-ramp-delay = <6250>; 134*f126890aSEmmanuel Vadot }; 135*f126890aSEmmanuel Vadot 136*f126890aSEmmanuel Vadot sw1c_reg: sw1c { 137*f126890aSEmmanuel Vadot regulator-min-microvolt = <300000>; 138*f126890aSEmmanuel Vadot regulator-max-microvolt = <1875000>; 139*f126890aSEmmanuel Vadot regulator-boot-on; 140*f126890aSEmmanuel Vadot regulator-always-on; 141*f126890aSEmmanuel Vadot regulator-ramp-delay = <6250>; 142*f126890aSEmmanuel Vadot }; 143*f126890aSEmmanuel Vadot 144*f126890aSEmmanuel Vadot sw2_reg: sw2 { 145*f126890aSEmmanuel Vadot regulator-min-microvolt = <800000>; 146*f126890aSEmmanuel Vadot regulator-max-microvolt = <3950000>; 147*f126890aSEmmanuel Vadot regulator-boot-on; 148*f126890aSEmmanuel Vadot regulator-always-on; 149*f126890aSEmmanuel Vadot }; 150*f126890aSEmmanuel Vadot 151*f126890aSEmmanuel Vadot sw3a_reg: sw3a { 152*f126890aSEmmanuel Vadot regulator-min-microvolt = <400000>; 153*f126890aSEmmanuel Vadot regulator-max-microvolt = <1975000>; 154*f126890aSEmmanuel Vadot regulator-boot-on; 155*f126890aSEmmanuel Vadot regulator-always-on; 156*f126890aSEmmanuel Vadot }; 157*f126890aSEmmanuel Vadot 158*f126890aSEmmanuel Vadot sw3b_reg: sw3b { 159*f126890aSEmmanuel Vadot regulator-min-microvolt = <400000>; 160*f126890aSEmmanuel Vadot regulator-max-microvolt = <1975000>; 161*f126890aSEmmanuel Vadot regulator-boot-on; 162*f126890aSEmmanuel Vadot regulator-always-on; 163*f126890aSEmmanuel Vadot }; 164*f126890aSEmmanuel Vadot 165*f126890aSEmmanuel Vadot sw4_reg: sw4 { 166*f126890aSEmmanuel Vadot regulator-min-microvolt = <800000>; 167*f126890aSEmmanuel Vadot regulator-max-microvolt = <3300000>; 168*f126890aSEmmanuel Vadot }; 169*f126890aSEmmanuel Vadot 170*f126890aSEmmanuel Vadot swbst_reg: swbst { 171*f126890aSEmmanuel Vadot regulator-min-microvolt = <5000000>; 172*f126890aSEmmanuel Vadot regulator-max-microvolt = <5150000>; 173*f126890aSEmmanuel Vadot }; 174*f126890aSEmmanuel Vadot 175*f126890aSEmmanuel Vadot snvs_reg: vsnvs { 176*f126890aSEmmanuel Vadot regulator-min-microvolt = <1000000>; 177*f126890aSEmmanuel Vadot regulator-max-microvolt = <3000000>; 178*f126890aSEmmanuel Vadot regulator-boot-on; 179*f126890aSEmmanuel Vadot regulator-always-on; 180*f126890aSEmmanuel Vadot }; 181*f126890aSEmmanuel Vadot 182*f126890aSEmmanuel Vadot vref_reg: vrefddr { 183*f126890aSEmmanuel Vadot regulator-boot-on; 184*f126890aSEmmanuel Vadot regulator-always-on; 185*f126890aSEmmanuel Vadot }; 186*f126890aSEmmanuel Vadot 187*f126890aSEmmanuel Vadot vgen1_reg: vgen1 { 188*f126890aSEmmanuel Vadot regulator-min-microvolt = <800000>; 189*f126890aSEmmanuel Vadot regulator-max-microvolt = <1550000>; 190*f126890aSEmmanuel Vadot }; 191*f126890aSEmmanuel Vadot 192*f126890aSEmmanuel Vadot vgen2_reg: vgen2 { 193*f126890aSEmmanuel Vadot regulator-min-microvolt = <800000>; 194*f126890aSEmmanuel Vadot regulator-max-microvolt = <1550000>; 195*f126890aSEmmanuel Vadot }; 196*f126890aSEmmanuel Vadot 197*f126890aSEmmanuel Vadot vgen3_reg: vgen3 { 198*f126890aSEmmanuel Vadot regulator-min-microvolt = <1800000>; 199*f126890aSEmmanuel Vadot regulator-max-microvolt = <3300000>; 200*f126890aSEmmanuel Vadot }; 201*f126890aSEmmanuel Vadot 202*f126890aSEmmanuel Vadot vgen4_reg: vgen4 { 203*f126890aSEmmanuel Vadot regulator-min-microvolt = <1800000>; 204*f126890aSEmmanuel Vadot regulator-max-microvolt = <3300000>; 205*f126890aSEmmanuel Vadot regulator-always-on; 206*f126890aSEmmanuel Vadot }; 207*f126890aSEmmanuel Vadot 208*f126890aSEmmanuel Vadot vgen5_reg: vgen5 { 209*f126890aSEmmanuel Vadot regulator-min-microvolt = <1800000>; 210*f126890aSEmmanuel Vadot regulator-max-microvolt = <3300000>; 211*f126890aSEmmanuel Vadot regulator-always-on; 212*f126890aSEmmanuel Vadot }; 213*f126890aSEmmanuel Vadot 214*f126890aSEmmanuel Vadot vgen6_reg: vgen6 { 215*f126890aSEmmanuel Vadot regulator-min-microvolt = <1800000>; 216*f126890aSEmmanuel Vadot regulator-max-microvolt = <3300000>; 217*f126890aSEmmanuel Vadot regulator-always-on; 218*f126890aSEmmanuel Vadot }; 219*f126890aSEmmanuel Vadot }; 220*f126890aSEmmanuel Vadot }; 221*f126890aSEmmanuel Vadot}; 222*f126890aSEmmanuel Vadot 223*f126890aSEmmanuel Vadot&ldb { 224*f126890aSEmmanuel Vadot status = "okay"; 225*f126890aSEmmanuel Vadot 226*f126890aSEmmanuel Vadot lvds0: lvds-channel@0 { 227*f126890aSEmmanuel Vadot fsl,data-mapping = "spwg"; 228*f126890aSEmmanuel Vadot fsl,data-width = <24>; 229*f126890aSEmmanuel Vadot status = "okay"; 230*f126890aSEmmanuel Vadot 231*f126890aSEmmanuel Vadot port@4 { 232*f126890aSEmmanuel Vadot reg = <4>; 233*f126890aSEmmanuel Vadot 234*f126890aSEmmanuel Vadot lvds0_out: endpoint { 235*f126890aSEmmanuel Vadot remote-endpoint = <&panel_in_lvds0>; 236*f126890aSEmmanuel Vadot }; 237*f126890aSEmmanuel Vadot }; 238*f126890aSEmmanuel Vadot }; 239*f126890aSEmmanuel Vadot}; 240*f126890aSEmmanuel Vadot 241*f126890aSEmmanuel Vadot&pwm2 { 242*f126890aSEmmanuel Vadot pinctrl-names = "default"; 243*f126890aSEmmanuel Vadot pinctrl-0 = <&pinctrl_pwm2>; 244*f126890aSEmmanuel Vadot status = "okay"; 245*f126890aSEmmanuel Vadot}; 246*f126890aSEmmanuel Vadot 247*f126890aSEmmanuel Vadot&uart1 { 248*f126890aSEmmanuel Vadot pinctrl-names = "default"; 249*f126890aSEmmanuel Vadot pinctrl-0 = <&pinctrl_uart1>; 250*f126890aSEmmanuel Vadot status = "okay"; 251*f126890aSEmmanuel Vadot}; 252*f126890aSEmmanuel Vadot 253*f126890aSEmmanuel Vadot&uart4 { 254*f126890aSEmmanuel Vadot pinctrl-names = "default"; 255*f126890aSEmmanuel Vadot pinctrl-0 = <&pinctrl_uart4>; 256*f126890aSEmmanuel Vadot uart-has-rtscts; 257*f126890aSEmmanuel Vadot status = "okay"; 258*f126890aSEmmanuel Vadot}; 259*f126890aSEmmanuel Vadot 260*f126890aSEmmanuel Vadot&usdhc2 { 261*f126890aSEmmanuel Vadot pinctrl-names = "default"; 262*f126890aSEmmanuel Vadot pinctrl-0 = <&pinctrl_usdhc2>; 263*f126890aSEmmanuel Vadot cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; 264*f126890aSEmmanuel Vadot bus-width = <4>; 265*f126890aSEmmanuel Vadot status = "okay"; 266*f126890aSEmmanuel Vadot}; 267*f126890aSEmmanuel Vadot 268*f126890aSEmmanuel Vadot&usdhc3 { 269*f126890aSEmmanuel Vadot pinctrl-names = "default"; 270*f126890aSEmmanuel Vadot pinctrl-0 = <&pinctrl_usdhc3>; 271*f126890aSEmmanuel Vadot bus-width = <8>; 272*f126890aSEmmanuel Vadot non-removable; 273*f126890aSEmmanuel Vadot status = "okay"; 274*f126890aSEmmanuel Vadot}; 275*f126890aSEmmanuel Vadot 276*f126890aSEmmanuel Vadot&weim { 277*f126890aSEmmanuel Vadot pinctrl-names = "default"; 278*f126890aSEmmanuel Vadot pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>; 279*f126890aSEmmanuel Vadot ranges = <0 0 0x08000000 0x08000000>; 280*f126890aSEmmanuel Vadot status = "okay"; 281*f126890aSEmmanuel Vadot 282*f126890aSEmmanuel Vadot nor@0,0 { 283*f126890aSEmmanuel Vadot compatible = "cfi-flash"; 284*f126890aSEmmanuel Vadot reg = <0 0 0x02000000>; 285*f126890aSEmmanuel Vadot #address-cells = <1>; 286*f126890aSEmmanuel Vadot #size-cells = <1>; 287*f126890aSEmmanuel Vadot bank-width = <2>; 288*f126890aSEmmanuel Vadot use-advanced-sector-protection; 289*f126890aSEmmanuel Vadot fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000 290*f126890aSEmmanuel Vadot 0x0000c000 0x1404a38e 0x00000000>; 291*f126890aSEmmanuel Vadot }; 292*f126890aSEmmanuel Vadot}; 293*f126890aSEmmanuel Vadot 294*f126890aSEmmanuel Vadot&iomuxc { 295*f126890aSEmmanuel Vadot pinctrl-names = "default"; 296*f126890aSEmmanuel Vadot 297*f126890aSEmmanuel Vadot pinctrl_backlight: dispgrp { 298*f126890aSEmmanuel Vadot fsl,pins = < 299*f126890aSEmmanuel Vadot /* BLEN_OUT */ 300*f126890aSEmmanuel Vadot MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 301*f126890aSEmmanuel Vadot >; 302*f126890aSEmmanuel Vadot }; 303*f126890aSEmmanuel Vadot 304*f126890aSEmmanuel Vadot pinctrl_ecspi3: ecspi3grp { 305*f126890aSEmmanuel Vadot fsl,pins = < 306*f126890aSEmmanuel Vadot MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 307*f126890aSEmmanuel Vadot MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 308*f126890aSEmmanuel Vadot MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 309*f126890aSEmmanuel Vadot >; 310*f126890aSEmmanuel Vadot }; 311*f126890aSEmmanuel Vadot 312*f126890aSEmmanuel Vadot pinctrl_ecspi3_cs: ecspi3csgrp { 313*f126890aSEmmanuel Vadot fsl,pins = < 314*f126890aSEmmanuel Vadot MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 315*f126890aSEmmanuel Vadot >; 316*f126890aSEmmanuel Vadot }; 317*f126890aSEmmanuel Vadot 318*f126890aSEmmanuel Vadot pinctrl_ecspi3_flwp: ecspi3flwpgrp { 319*f126890aSEmmanuel Vadot fsl,pins = < 320*f126890aSEmmanuel Vadot MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x80000000 321*f126890aSEmmanuel Vadot >; 322*f126890aSEmmanuel Vadot }; 323*f126890aSEmmanuel Vadot 324*f126890aSEmmanuel Vadot pinctrl_enet: enetgrp { 325*f126890aSEmmanuel Vadot fsl,pins = < 326*f126890aSEmmanuel Vadot MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 327*f126890aSEmmanuel Vadot MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 328*f126890aSEmmanuel Vadot MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 329*f126890aSEmmanuel Vadot MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 330*f126890aSEmmanuel Vadot MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 331*f126890aSEmmanuel Vadot MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 332*f126890aSEmmanuel Vadot MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 333*f126890aSEmmanuel Vadot MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 334*f126890aSEmmanuel Vadot MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 335*f126890aSEmmanuel Vadot MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 336*f126890aSEmmanuel Vadot MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 337*f126890aSEmmanuel Vadot MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 338*f126890aSEmmanuel Vadot MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 339*f126890aSEmmanuel Vadot MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 340*f126890aSEmmanuel Vadot MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 341*f126890aSEmmanuel Vadot MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 342*f126890aSEmmanuel Vadot MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 343*f126890aSEmmanuel Vadot MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 344*f126890aSEmmanuel Vadot >; 345*f126890aSEmmanuel Vadot }; 346*f126890aSEmmanuel Vadot 347*f126890aSEmmanuel Vadot pinctrl_i2c1: i2c1grp { 348*f126890aSEmmanuel Vadot fsl,pins = < 349*f126890aSEmmanuel Vadot MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 350*f126890aSEmmanuel Vadot MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 351*f126890aSEmmanuel Vadot >; 352*f126890aSEmmanuel Vadot }; 353*f126890aSEmmanuel Vadot 354*f126890aSEmmanuel Vadot pinctrl_i2c2: i2c2grp { 355*f126890aSEmmanuel Vadot fsl,pins = < 356*f126890aSEmmanuel Vadot MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 357*f126890aSEmmanuel Vadot MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 358*f126890aSEmmanuel Vadot >; 359*f126890aSEmmanuel Vadot }; 360*f126890aSEmmanuel Vadot 361*f126890aSEmmanuel Vadot pinctrl_pwm2: pwm2grp { 362*f126890aSEmmanuel Vadot fsl,pins = < 363*f126890aSEmmanuel Vadot MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 364*f126890aSEmmanuel Vadot >; 365*f126890aSEmmanuel Vadot }; 366*f126890aSEmmanuel Vadot 367*f126890aSEmmanuel Vadot pinctrl_reg_lvds: reqlvdsgrp { 368*f126890aSEmmanuel Vadot fsl,pins = < 369*f126890aSEmmanuel Vadot /* LVDS_PPEN_OUT */ 370*f126890aSEmmanuel Vadot MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0 371*f126890aSEmmanuel Vadot >; 372*f126890aSEmmanuel Vadot }; 373*f126890aSEmmanuel Vadot 374*f126890aSEmmanuel Vadot pinctrl_uart1: uart1grp { 375*f126890aSEmmanuel Vadot fsl,pins = < 376*f126890aSEmmanuel Vadot MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 377*f126890aSEmmanuel Vadot MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 378*f126890aSEmmanuel Vadot >; 379*f126890aSEmmanuel Vadot }; 380*f126890aSEmmanuel Vadot 381*f126890aSEmmanuel Vadot pinctrl_uart4: uart4grp { 382*f126890aSEmmanuel Vadot fsl,pins = < 383*f126890aSEmmanuel Vadot MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 384*f126890aSEmmanuel Vadot MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 385*f126890aSEmmanuel Vadot MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 386*f126890aSEmmanuel Vadot MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 387*f126890aSEmmanuel Vadot >; 388*f126890aSEmmanuel Vadot }; 389*f126890aSEmmanuel Vadot 390*f126890aSEmmanuel Vadot pinctrl_usdhc2: usdhc2grp { 391*f126890aSEmmanuel Vadot fsl,pins = < 392*f126890aSEmmanuel Vadot MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 393*f126890aSEmmanuel Vadot MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 394*f126890aSEmmanuel Vadot MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 395*f126890aSEmmanuel Vadot MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 396*f126890aSEmmanuel Vadot MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 397*f126890aSEmmanuel Vadot MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 398*f126890aSEmmanuel Vadot MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b1 399*f126890aSEmmanuel Vadot >; 400*f126890aSEmmanuel Vadot }; 401*f126890aSEmmanuel Vadot 402*f126890aSEmmanuel Vadot pinctrl_usdhc3: usdhc3grp { 403*f126890aSEmmanuel Vadot fsl,pins = < 404*f126890aSEmmanuel Vadot MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 405*f126890aSEmmanuel Vadot MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 406*f126890aSEmmanuel Vadot MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 407*f126890aSEmmanuel Vadot MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 408*f126890aSEmmanuel Vadot MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 409*f126890aSEmmanuel Vadot MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 410*f126890aSEmmanuel Vadot MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 411*f126890aSEmmanuel Vadot MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 412*f126890aSEmmanuel Vadot MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 413*f126890aSEmmanuel Vadot MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 414*f126890aSEmmanuel Vadot MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 415*f126890aSEmmanuel Vadot >; 416*f126890aSEmmanuel Vadot }; 417*f126890aSEmmanuel Vadot 418*f126890aSEmmanuel Vadot pinctrl_weim_cs0: weimcs0grp { 419*f126890aSEmmanuel Vadot fsl,pins = < 420*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 421*f126890aSEmmanuel Vadot >; 422*f126890aSEmmanuel Vadot }; 423*f126890aSEmmanuel Vadot 424*f126890aSEmmanuel Vadot pinctrl_weim_nor: weimnorgrp { 425*f126890aSEmmanuel Vadot fsl,pins = < 426*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 427*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 428*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 429*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 430*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 431*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 432*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 433*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 434*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 435*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 436*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 437*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 438*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 439*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 440*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 441*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 442*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 443*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 444*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 445*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 446*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 447*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 448*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 449*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 450*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 451*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 452*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 453*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 454*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 455*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 456*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 457*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 458*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 459*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 460*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 461*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 462*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 463*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 464*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 465*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 466*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 467*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 468*f126890aSEmmanuel Vadot MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 469*f126890aSEmmanuel Vadot >; 470*f126890aSEmmanuel Vadot }; 471*f126890aSEmmanuel Vadot}; 472