1/*
2 * Copyright 2017 Gateworks Corporation
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 *  a) This file is free software; you can redistribute it and/or
10 *     modify it under the terms of the GNU General Public License as
11 *     published by the Free Software Foundation; either version 2 of
12 *     the License, or (at your option) any later version.
13 *
14 *     This file is distributed in the hope that it will be useful,
15 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 *     GNU General Public License for more details.
18 *
19 *     You should have received a copy of the GNU General Public
20 *     License along with this file; if not, write to the Free
21 *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 *     MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 *  b) Permission is hereby granted, free of charge, to any person
27 *     obtaining a copy of this software and associated documentation
28 *     files (the "Software"), to deal in the Software without
29 *     restriction, including without limitation the rights to use,
30 *     copy, modify, merge, publish, distribute, sublicense, and/or
31 *     sell copies of the Software, and to permit persons to whom the
32 *     Software is furnished to do so, subject to the following
33 *     conditions:
34 *
35 *     The above copyright notice and this permission notice shall be
36 *     included in all copies or substantial portions of the Software.
37 *
38 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 *     OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48#include <dt-bindings/gpio/gpio.h>
49#include <dt-bindings/input/linux-event-codes.h>
50#include <dt-bindings/interrupt-controller/irq.h>
51
52/ {
53	/* these are used by bootloader for disabling nodes */
54	aliases {
55		led0 = &led0;
56		led1 = &led1;
57		led2 = &led2;
58		usb0 = &usbh1;
59		usb1 = &usbotg;
60	};
61
62	chosen {
63		stdout-path = &uart2;
64	};
65
66	backlight {
67		compatible = "pwm-backlight";
68		pwms = <&pwm4 0 5000000>;
69		brightness-levels = <0 4 8 16 32 64 128 255>;
70		default-brightness-level = <7>;
71	};
72
73	gpio-keys {
74		compatible = "gpio-keys";
75
76		user-pb {
77			label = "user_pb";
78			gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
79			linux,code = <BTN_0>;
80		};
81
82		user-pb1x {
83			label = "user_pb1x";
84			linux,code = <BTN_1>;
85			interrupt-parent = <&gsc>;
86			interrupts = <0>;
87		};
88
89		key-erased {
90			label = "key-erased";
91			linux,code = <BTN_2>;
92			interrupt-parent = <&gsc>;
93			interrupts = <1>;
94		};
95
96		eeprom-wp {
97			label = "eeprom_wp";
98			linux,code = <BTN_3>;
99			interrupt-parent = <&gsc>;
100			interrupts = <2>;
101		};
102
103		tamper {
104			label = "tamper";
105			linux,code = <BTN_4>;
106			interrupt-parent = <&gsc>;
107			interrupts = <5>;
108		};
109
110		switch-hold {
111			label = "switch_hold";
112			linux,code = <BTN_5>;
113			interrupt-parent = <&gsc>;
114			interrupts = <7>;
115		};
116	};
117
118	leds {
119		compatible = "gpio-leds";
120		pinctrl-names = "default";
121		pinctrl-0 = <&pinctrl_gpio_leds>;
122
123		led0: led-user1 {
124			label = "user1";
125			gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
126			default-state = "on";
127			linux,default-trigger = "heartbeat";
128		};
129
130		led1: led-user2 {
131			label = "user2";
132			gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
133			default-state = "off";
134		};
135
136		led2: led-user3 {
137			label = "user3";
138			gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
139			default-state = "off";
140		};
141	};
142
143	memory@10000000 {
144		device_type = "memory";
145		reg = <0x10000000 0x40000000>;
146	};
147
148	pps {
149		compatible = "pps-gpio";
150		pinctrl-names = "default";
151		pinctrl-0 = <&pinctrl_pps>;
152		gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
153	};
154
155	reg_1p0v: regulator-1p0v {
156		compatible = "regulator-fixed";
157		regulator-name = "1P0V";
158		regulator-min-microvolt = <1000000>;
159		regulator-max-microvolt = <1000000>;
160		regulator-always-on;
161	};
162
163	reg_3p3v: regulator-3p3v {
164		compatible = "regulator-fixed";
165		regulator-name = "3P3V";
166		regulator-min-microvolt = <3300000>;
167		regulator-max-microvolt = <3300000>;
168		regulator-always-on;
169	};
170
171	reg_usb_h1_vbus: regulator-usb-h1-vbus {
172		compatible = "regulator-fixed";
173		regulator-name = "usb_h1_vbus";
174		regulator-min-microvolt = <5000000>;
175		regulator-max-microvolt = <5000000>;
176		regulator-always-on;
177	};
178
179	reg_usb_otg_vbus: regulator-usb-otg-vbus {
180		compatible = "regulator-fixed";
181		regulator-name = "usb_otg_vbus";
182		regulator-min-microvolt = <5000000>;
183		regulator-max-microvolt = <5000000>;
184		gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
185		enable-active-high;
186	};
187};
188
189&clks {
190	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
191			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
192	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
193				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
194};
195
196&fec {
197	pinctrl-names = "default";
198	pinctrl-0 = <&pinctrl_enet>;
199	phy-mode = "rgmii-id";
200	status = "okay";
201
202	fixed-link {
203		speed = <1000>;
204		full-duplex;
205	};
206
207	mdio {
208		#address-cells = <1>;
209		#size-cells = <0>;
210
211		switch@0 {
212			compatible = "marvell,mv88e6085";
213			reg = <0>;
214
215			ports {
216				#address-cells = <1>;
217				#size-cells = <0>;
218
219				port@0 {
220					reg = <0>;
221					label = "lan4";
222				};
223
224				port@1 {
225					reg = <1>;
226					label = "lan3";
227				};
228
229				port@2 {
230					reg = <2>;
231					label = "lan2";
232				};
233
234				port@3 {
235					reg = <3>;
236					label = "lan1";
237				};
238
239				port@5 {
240					reg = <5>;
241					ethernet = <&fec>;
242					phy-mode = "rgmii-id";
243
244					fixed-link {
245						speed = <1000>;
246						full-duplex;
247					};
248				};
249			};
250		};
251	};
252};
253
254&i2c1 {
255	clock-frequency = <100000>;
256	pinctrl-names = "default";
257	pinctrl-0 = <&pinctrl_i2c1>;
258	status = "okay";
259
260	gsc: gsc@20 {
261		compatible = "gw,gsc";
262		reg = <0x20>;
263		interrupt-parent = <&gpio1>;
264		interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
265		interrupt-controller;
266		#interrupt-cells = <1>;
267		#size-cells = <0>;
268
269		adc {
270			compatible = "gw,gsc-adc";
271			#address-cells = <1>;
272			#size-cells = <0>;
273
274			channel@0 {
275				gw,mode = <0>;
276				reg = <0x00>;
277				label = "temp";
278			};
279
280			channel@2 {
281				gw,mode = <1>;
282				reg = <0x02>;
283				label = "vdd_vin";
284			};
285
286			channel@5 {
287				gw,mode = <1>;
288				reg = <0x05>;
289				label = "vdd_3p3";
290			};
291
292			channel@8 {
293				gw,mode = <1>;
294				reg = <0x08>;
295				label = "vdd_bat";
296			};
297
298			channel@b {
299				gw,mode = <1>;
300				reg = <0x0b>;
301				label = "vdd_5p0";
302			};
303
304			channel@e {
305				gw,mode = <1>;
306				reg = <0xe>;
307				label = "vdd_arm";
308			};
309
310			channel@11 {
311				gw,mode = <1>;
312				reg = <0x11>;
313				label = "vdd_soc";
314			};
315
316			channel@14 {
317				gw,mode = <1>;
318				reg = <0x14>;
319				label = "vdd_3p0";
320			};
321
322			channel@17 {
323				gw,mode = <1>;
324				reg = <0x17>;
325				label = "vdd_1p5";
326			};
327
328			channel@1d {
329				gw,mode = <1>;
330				reg = <0x1d>;
331				label = "vdd_1p8";
332			};
333
334			channel@20 {
335				gw,mode = <1>;
336				reg = <0x20>;
337				label = "vdd_an1";
338			};
339
340			channel@23 {
341				gw,mode = <1>;
342				reg = <0x23>;
343				label = "vdd_2p5";
344			};
345		};
346	};
347
348	gsc_gpio: gpio@23 {
349		compatible = "nxp,pca9555";
350		reg = <0x23>;
351		gpio-controller;
352		#gpio-cells = <2>;
353		interrupt-parent = <&gsc>;
354		interrupts = <4>;
355	};
356
357	eeprom1: eeprom@50 {
358		compatible = "atmel,24c02";
359		reg = <0x50>;
360		pagesize = <16>;
361	};
362
363	eeprom2: eeprom@51 {
364		compatible = "atmel,24c02";
365		reg = <0x51>;
366		pagesize = <16>;
367	};
368
369	eeprom3: eeprom@52 {
370		compatible = "atmel,24c02";
371		reg = <0x52>;
372		pagesize = <16>;
373	};
374
375	eeprom4: eeprom@53 {
376		compatible = "atmel,24c02";
377		reg = <0x53>;
378		pagesize = <16>;
379	};
380
381	dts1672: rtc@68 {
382		compatible = "dallas,ds1672";
383		reg = <0x68>;
384	};
385};
386
387&i2c2 {
388	clock-frequency = <100000>;
389	pinctrl-names = "default";
390	pinctrl-0 = <&pinctrl_i2c2>;
391	status = "okay";
392
393	magn@1c {
394		compatible = "st,lsm9ds1-magn";
395		reg = <0x1c>;
396		pinctrl-names = "default";
397		pinctrl-0 = <&pinctrl_mag>;
398		interrupt-parent = <&gpio5>;
399		interrupts = <17 IRQ_TYPE_EDGE_RISING>;
400	};
401
402	ltc3676: pmic@3c {
403		compatible = "lltc,ltc3676";
404		reg = <0x3c>;
405		interrupt-parent = <&gpio1>;
406		interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
407
408		regulators {
409			/* VDD_SOC (1+R1/R2 = 1.635) */
410			reg_vdd_soc: sw1 {
411				regulator-name = "vddsoc";
412				regulator-min-microvolt = <674400>;
413				regulator-max-microvolt = <1308000>;
414				lltc,fb-voltage-divider = <127000 200000>;
415				regulator-ramp-delay = <7000>;
416				regulator-boot-on;
417				regulator-always-on;
418			};
419
420			/* VDD_1P8 (1+R1/R2 = 2.505): GbE switch */
421			reg_1p8v: sw2 {
422				regulator-name = "vdd1p8";
423				regulator-min-microvolt = <1033310>;
424				regulator-max-microvolt = <2004000>;
425				lltc,fb-voltage-divider = <301000 200000>;
426				regulator-ramp-delay = <7000>;
427				regulator-boot-on;
428				regulator-always-on;
429			};
430
431			/* VDD_ARM (1+R1/R2 = 1.635) */
432			reg_vdd_arm: sw3 {
433				regulator-name = "vddarm";
434				regulator-min-microvolt = <674400>;
435				regulator-max-microvolt = <1308000>;
436				lltc,fb-voltage-divider = <127000 200000>;
437				regulator-ramp-delay = <7000>;
438				regulator-boot-on;
439				regulator-always-on;
440			};
441
442			/* VDD_DDR (1+R1/R2 = 2.105) */
443			reg_vdd_ddr: sw4 {
444				regulator-name = "vddddr";
445				regulator-min-microvolt = <868310>;
446				regulator-max-microvolt = <1684000>;
447				lltc,fb-voltage-divider = <221000 200000>;
448				regulator-ramp-delay = <7000>;
449				regulator-boot-on;
450				regulator-always-on;
451			};
452
453			/* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
454			reg_2p5v: ldo2 {
455				regulator-name = "vdd2p5";
456				regulator-min-microvolt = <2490375>;
457				regulator-max-microvolt = <2490375>;
458				lltc,fb-voltage-divider = <487000 200000>;
459				regulator-boot-on;
460				regulator-always-on;
461			};
462
463			/* VDD_HIGH (1+R1/R2 = 4.17) */
464			reg_3p0v: ldo4 {
465				regulator-name = "vdd3p0";
466				regulator-min-microvolt = <3023250>;
467				regulator-max-microvolt = <3023250>;
468				lltc,fb-voltage-divider = <634000 200000>;
469				regulator-boot-on;
470				regulator-always-on;
471			};
472		};
473	};
474
475	crypto@60 {
476		compatible = "atmel,atecc508a";
477		reg = <0x60>;
478	};
479
480	imu@6a {
481		compatible = "st,lsm9ds1-imu";
482		reg = <0x6a>;
483		st,drdy-int-pin = <1>;
484		pinctrl-names = "default";
485		pinctrl-0 = <&pinctrl_imu>;
486		interrupt-parent = <&gpio4>;
487		interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
488	};
489};
490
491&i2c3 {
492	clock-frequency = <100000>;
493	pinctrl-names = "default";
494	pinctrl-0 = <&pinctrl_i2c3>;
495	status = "okay";
496
497	egalax_ts: touchscreen@4 {
498		compatible = "eeti,egalax_ts";
499		reg = <0x04>;
500		interrupt-parent = <&gpio1>;
501		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
502		wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
503	};
504};
505
506&ldb {
507	status = "okay";
508
509	lvds-channel@0 {
510		fsl,data-mapping = "spwg";
511		fsl,data-width = <18>;
512		status = "okay";
513
514		display-timings {
515			native-mode = <&timing0>;
516			timing0: hsd100pxn1 {
517				clock-frequency = <65000000>;
518				hactive = <1024>;
519				vactive = <768>;
520				hback-porch = <220>;
521				hfront-porch = <40>;
522				vback-porch = <21>;
523				vfront-porch = <7>;
524				hsync-len = <60>;
525				vsync-len = <10>;
526			};
527		};
528	};
529};
530
531&pcie {
532	pinctrl-names = "default";
533	pinctrl-0 = <&pinctrl_pcie>;
534	reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
535	status = "okay";
536};
537
538&pwm2 {
539	pinctrl-names = "default";
540	pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
541	status = "disabled";
542};
543
544&pwm3 {
545	pinctrl-names = "default";
546	pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
547	status = "disabled";
548};
549
550&pwm4 {
551	#pwm-cells = <2>;
552	pinctrl-names = "default";
553	pinctrl-0 = <&pinctrl_pwm4>;
554	status = "okay";
555};
556
557&uart1 {
558	pinctrl-names = "default";
559	pinctrl-0 = <&pinctrl_uart1>;
560	status = "okay";
561};
562
563&uart2 {
564	pinctrl-names = "default";
565	pinctrl-0 = <&pinctrl_uart2>;
566	status = "okay";
567};
568
569&uart3 {
570	pinctrl-names = "default";
571	pinctrl-0 = <&pinctrl_uart3>;
572	uart-has-rtscts;
573	status = "okay";
574};
575
576&uart4 {
577	pinctrl-names = "default";
578	pinctrl-0 = <&pinctrl_uart4>;
579	uart-has-rtscts;
580	status = "okay";
581};
582
583&uart5 {
584	pinctrl-names = "default";
585	pinctrl-0 = <&pinctrl_uart5>;
586	status = "okay";
587};
588
589&usbotg {
590	vbus-supply = <&reg_usb_otg_vbus>;
591	pinctrl-names = "default";
592	pinctrl-0 = <&pinctrl_usbotg>;
593	disable-over-current;
594	status = "okay";
595};
596
597&usbh1 {
598	vbus-supply = <&reg_usb_h1_vbus>;
599	status = "okay";
600};
601
602&usdhc3 {
603	pinctrl-names = "default", "state_100mhz", "state_200mhz";
604	pinctrl-0 = <&pinctrl_usdhc3>;
605	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
606	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
607	non-removable;
608	vmmc-supply = <&reg_3p3v>;
609	keep-power-in-suspend;
610	status = "okay";
611};
612
613&wdog1 {
614	pinctrl-names = "default";
615	pinctrl-0 = <&pinctrl_wdog>;
616	fsl,ext-reset-output;
617};
618
619&iomuxc {
620	pinctrl_enet: enetgrp {
621		fsl,pins = <
622			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
623			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
624			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
625			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
626			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
627			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
628			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
629			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
630			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
631			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
632			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
633			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
634			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
635			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
636			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
637			MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
638			MX6QDL_PAD_ENET_TXD0__GPIO1_IO30	0x4001b0b0 /* PHY_RST# */
639		>;
640	};
641
642	pinctrl_gpio_leds: gpioledsgrp {
643		fsl,pins = <
644			MX6QDL_PAD_KEY_COL0__GPIO4_IO06		0x1b0b0
645			MX6QDL_PAD_KEY_ROW0__GPIO4_IO07		0x1b0b0
646			MX6QDL_PAD_KEY_ROW4__GPIO4_IO15		0x1b0b0
647		>;
648	};
649
650	pinctrl_i2c1: i2c1grp {
651		fsl,pins = <
652			MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
653			MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
654			MX6QDL_PAD_GPIO_4__GPIO1_IO04		0x0001b0b0 /* GSC_IRQ# */
655		>;
656	};
657
658	pinctrl_i2c2: i2c2grp {
659		fsl,pins = <
660			MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
661			MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
662		>;
663	};
664
665	pinctrl_i2c3: i2c3grp {
666		fsl,pins = <
667			MX6QDL_PAD_GPIO_3__I2C3_SCL		0x4001b8b1
668			MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
669		>;
670	};
671
672	pinctrl_imu: imugrp {
673		fsl,pins = <
674			MX6QDL_PAD_DI0_PIN2__GPIO4_IO18		0x1b0b0
675		>;
676	};
677
678	pinctrl_mag: maggrp {
679		fsl,pins = <
680			MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17	0x1b0b0
681		>;
682	};
683
684	pinctrl_pcie: pciegrp {
685		fsl,pins = <
686			MX6QDL_PAD_GPIO_0__GPIO1_IO00	0x1b0b0 /* PCIE RST */
687		>;
688	};
689
690	pinctrl_pmic: pmicgrp {
691		fsl,pins = <
692			MX6QDL_PAD_GPIO_8__GPIO1_IO08	0x1b0b0 /* PMIC_IRQ# */
693		>;
694	};
695
696	pinctrl_pps: ppsgrp {
697		fsl,pins = <
698			MX6QDL_PAD_ENET_RXD1__GPIO1_IO26	0x1b0b1
699		>;
700	};
701
702	pinctrl_pwm2: pwm2grp {
703		fsl,pins = <
704			MX6QDL_PAD_SD1_DAT2__PWM2_OUT		0x1b0b1
705		>;
706	};
707
708	pinctrl_pwm3: pwm3grp {
709		fsl,pins = <
710			MX6QDL_PAD_SD1_DAT1__PWM3_OUT		0x1b0b1
711		>;
712	};
713
714	pinctrl_pwm4: pwm4grp {
715		fsl,pins = <
716			MX6QDL_PAD_SD1_CMD__PWM4_OUT		0x1b0b1
717		>;
718	};
719
720	pinctrl_uart1: uart1grp {
721		fsl,pins = <
722			MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1
723			MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
724		>;
725	};
726
727	pinctrl_uart2: uart2grp {
728		fsl,pins = <
729			MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA	0x1b0b1
730			MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA	0x1b0b1
731		>;
732	};
733
734	pinctrl_uart3: uart3grp {
735		fsl,pins = <
736			MX6QDL_PAD_EIM_D23__UART3_CTS_B         0x1b0b1
737			MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
738			MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
739			MX6QDL_PAD_EIM_D31__UART3_RTS_B         0x1b0b1
740		>;
741	};
742
743	pinctrl_uart4: uart4grp {
744		fsl,pins = <
745			MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA    0x1b0b1
746			MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA    0x1b0b1
747			MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B      0x1b0b1
748			MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B      0x1b0b1
749		>;
750	};
751
752	pinctrl_uart5: uart5grp {
753		fsl,pins = <
754			MX6QDL_PAD_KEY_COL1__UART5_TX_DATA	0x1b0b1
755			MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA	0x1b0b1
756		>;
757	};
758
759	pinctrl_usbotg: usbotggrp {
760		fsl,pins = <
761			MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
762			MX6QDL_PAD_EIM_D22__GPIO3_IO22		0x1b0b0 /* PWR_EN */
763			MX6QDL_PAD_KEY_COL4__GPIO4_IO14		0x1b0b0 /* OC */
764		>;
765	};
766
767	pinctrl_usdhc3: usdhc3grp {
768		fsl,pins = <
769			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
770			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
771			MX6QDL_PAD_SD3_RST__SD3_RESET		0x10059
772			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
773			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
774			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
775			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
776			MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x17059
777			MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x17059
778			MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x17059
779			MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x17059
780		>;
781	};
782
783	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
784		fsl,pins = <
785			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170b9
786			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100b9
787			MX6QDL_PAD_SD3_RST__SD3_RESET		0x100b9
788			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170b9
789			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170b9
790			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170b9
791			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170b9
792			MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x170b9
793			MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x170b9
794			MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x170b9
795			MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x170b9
796		>;
797	};
798
799	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
800		fsl,pins = <
801			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170f9
802			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100f9
803			MX6QDL_PAD_SD3_RST__SD3_RESET		0x100f9
804			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170f9
805			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170f9
806			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170f9
807			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170f9
808			MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x170f9
809			MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x170f9
810			MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x170f9
811			MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x170f9
812		>;
813	};
814
815	pinctrl_wdog: wdoggrp {
816		fsl,pins = <
817			MX6QDL_PAD_DISP0_DAT8__WDOG1_B		0x1b0b0
818		>;
819	};
820};
821