1*f126890aSEmmanuel Vadot// SPDX-License-Identifier: (GPL-2.0) 2*f126890aSEmmanuel Vadot/* 3*f126890aSEmmanuel Vadot * Device tree for the Kobo Clara HD ebook reader 4*f126890aSEmmanuel Vadot * 5*f126890aSEmmanuel Vadot * Name on mainboard is: 37NB-E60K00+4A4 6*f126890aSEmmanuel Vadot * Serials start with: E60K02 (a number also seen in 7*f126890aSEmmanuel Vadot * vendor kernel sources) 8*f126890aSEmmanuel Vadot * 9*f126890aSEmmanuel Vadot * This mainboard seems to be equipped with different SoCs. 10*f126890aSEmmanuel Vadot * In the Kobo Clara HD ebook reader it is an i.MX6SLL 11*f126890aSEmmanuel Vadot * 12*f126890aSEmmanuel Vadot * Copyright 2019 Andreas Kemnade 13*f126890aSEmmanuel Vadot * based on works 14*f126890aSEmmanuel Vadot * Copyright 2016 Freescale Semiconductor, Inc. 15*f126890aSEmmanuel Vadot */ 16*f126890aSEmmanuel Vadot 17*f126890aSEmmanuel Vadot/dts-v1/; 18*f126890aSEmmanuel Vadot 19*f126890aSEmmanuel Vadot#include <dt-bindings/input/input.h> 20*f126890aSEmmanuel Vadot#include <dt-bindings/gpio/gpio.h> 21*f126890aSEmmanuel Vadot#include "imx6sll.dtsi" 22*f126890aSEmmanuel Vadot#include "e60k02.dtsi" 23*f126890aSEmmanuel Vadot 24*f126890aSEmmanuel Vadot/ { 25*f126890aSEmmanuel Vadot model = "Kobo Clara HD"; 26*f126890aSEmmanuel Vadot compatible = "kobo,clarahd", "fsl,imx6sll"; 27*f126890aSEmmanuel Vadot}; 28*f126890aSEmmanuel Vadot 29*f126890aSEmmanuel Vadot&clks { 30*f126890aSEmmanuel Vadot assigned-clocks = <&clks IMX6SLL_CLK_PLL4_AUDIO_DIV>; 31*f126890aSEmmanuel Vadot assigned-clock-rates = <393216000>; 32*f126890aSEmmanuel Vadot}; 33*f126890aSEmmanuel Vadot 34*f126890aSEmmanuel Vadot&cpu0 { 35*f126890aSEmmanuel Vadot arm-supply = <&dcdc3_reg>; 36*f126890aSEmmanuel Vadot soc-supply = <&dcdc1_reg>; 37*f126890aSEmmanuel Vadot}; 38*f126890aSEmmanuel Vadot 39*f126890aSEmmanuel Vadot&gpio_keys { 40*f126890aSEmmanuel Vadot pinctrl-names = "default"; 41*f126890aSEmmanuel Vadot pinctrl-0 = <&pinctrl_gpio_keys>; 42*f126890aSEmmanuel Vadot}; 43*f126890aSEmmanuel Vadot 44*f126890aSEmmanuel Vadot&i2c1 { 45*f126890aSEmmanuel Vadot pinctrl-names = "default","sleep"; 46*f126890aSEmmanuel Vadot pinctrl-0 = <&pinctrl_i2c1>; 47*f126890aSEmmanuel Vadot pinctrl-1 = <&pinctrl_i2c1_sleep>; 48*f126890aSEmmanuel Vadot}; 49*f126890aSEmmanuel Vadot 50*f126890aSEmmanuel Vadot&i2c2 { 51*f126890aSEmmanuel Vadot pinctrl-names = "default","sleep"; 52*f126890aSEmmanuel Vadot pinctrl-0 = <&pinctrl_i2c2>; 53*f126890aSEmmanuel Vadot pinctrl-1 = <&pinctrl_i2c2_sleep>; 54*f126890aSEmmanuel Vadot}; 55*f126890aSEmmanuel Vadot 56*f126890aSEmmanuel Vadot&i2c3 { 57*f126890aSEmmanuel Vadot pinctrl-names = "default"; 58*f126890aSEmmanuel Vadot pinctrl-0 = <&pinctrl_i2c3>; 59*f126890aSEmmanuel Vadot}; 60*f126890aSEmmanuel Vadot 61*f126890aSEmmanuel Vadot&iomuxc { 62*f126890aSEmmanuel Vadot pinctrl-names = "default"; 63*f126890aSEmmanuel Vadot pinctrl-0 = <&pinctrl_hog>; 64*f126890aSEmmanuel Vadot 65*f126890aSEmmanuel Vadot pinctrl_cyttsp5_gpio: cyttsp5-gpiogrp { 66*f126890aSEmmanuel Vadot fsl,pins = < 67*f126890aSEmmanuel Vadot MX6SLL_PAD_SD1_DATA3__GPIO5_IO06 0x17059 /* TP_INT */ 68*f126890aSEmmanuel Vadot MX6SLL_PAD_SD1_DATA2__GPIO5_IO13 0x10059 /* TP_RST */ 69*f126890aSEmmanuel Vadot >; 70*f126890aSEmmanuel Vadot }; 71*f126890aSEmmanuel Vadot 72*f126890aSEmmanuel Vadot pinctrl_gpio_keys: gpio-keysgrp { 73*f126890aSEmmanuel Vadot fsl,pins = < 74*f126890aSEmmanuel Vadot MX6SLL_PAD_SD1_DATA1__GPIO5_IO08 0x17059 /* PWR_SW */ 75*f126890aSEmmanuel Vadot MX6SLL_PAD_SD1_DATA4__GPIO5_IO12 0x17059 /* HALL_EN */ 76*f126890aSEmmanuel Vadot >; 77*f126890aSEmmanuel Vadot }; 78*f126890aSEmmanuel Vadot 79*f126890aSEmmanuel Vadot pinctrl_hog: hoggrp { 80*f126890aSEmmanuel Vadot fsl,pins = < 81*f126890aSEmmanuel Vadot MX6SLL_PAD_LCD_DATA00__GPIO2_IO20 0x79 82*f126890aSEmmanuel Vadot MX6SLL_PAD_LCD_DATA01__GPIO2_IO21 0x79 83*f126890aSEmmanuel Vadot MX6SLL_PAD_LCD_DATA02__GPIO2_IO22 0x79 84*f126890aSEmmanuel Vadot MX6SLL_PAD_LCD_DATA03__GPIO2_IO23 0x79 85*f126890aSEmmanuel Vadot MX6SLL_PAD_LCD_DATA04__GPIO2_IO24 0x79 86*f126890aSEmmanuel Vadot MX6SLL_PAD_LCD_DATA05__GPIO2_IO25 0x79 87*f126890aSEmmanuel Vadot MX6SLL_PAD_LCD_DATA06__GPIO2_IO26 0x79 88*f126890aSEmmanuel Vadot MX6SLL_PAD_LCD_DATA07__GPIO2_IO27 0x79 89*f126890aSEmmanuel Vadot MX6SLL_PAD_LCD_DATA08__GPIO2_IO28 0x79 90*f126890aSEmmanuel Vadot MX6SLL_PAD_LCD_DATA09__GPIO2_IO29 0x79 91*f126890aSEmmanuel Vadot MX6SLL_PAD_LCD_DATA10__GPIO2_IO30 0x79 92*f126890aSEmmanuel Vadot MX6SLL_PAD_LCD_DATA11__GPIO2_IO31 0x79 93*f126890aSEmmanuel Vadot MX6SLL_PAD_LCD_DATA12__GPIO3_IO00 0x79 94*f126890aSEmmanuel Vadot MX6SLL_PAD_LCD_DATA13__GPIO3_IO01 0x79 95*f126890aSEmmanuel Vadot MX6SLL_PAD_LCD_DATA14__GPIO3_IO02 0x79 96*f126890aSEmmanuel Vadot MX6SLL_PAD_LCD_DATA15__GPIO3_IO03 0x79 97*f126890aSEmmanuel Vadot MX6SLL_PAD_LCD_DATA16__GPIO3_IO04 0x79 98*f126890aSEmmanuel Vadot MX6SLL_PAD_LCD_DATA17__GPIO3_IO05 0x79 99*f126890aSEmmanuel Vadot MX6SLL_PAD_LCD_DATA18__GPIO3_IO06 0x79 100*f126890aSEmmanuel Vadot MX6SLL_PAD_LCD_DATA19__GPIO3_IO07 0x79 101*f126890aSEmmanuel Vadot MX6SLL_PAD_LCD_DATA20__GPIO3_IO08 0x79 102*f126890aSEmmanuel Vadot MX6SLL_PAD_LCD_DATA21__GPIO3_IO09 0x79 103*f126890aSEmmanuel Vadot MX6SLL_PAD_LCD_DATA22__GPIO3_IO10 0x79 104*f126890aSEmmanuel Vadot MX6SLL_PAD_LCD_DATA23__GPIO3_IO11 0x79 105*f126890aSEmmanuel Vadot MX6SLL_PAD_LCD_CLK__GPIO2_IO15 0x79 106*f126890aSEmmanuel Vadot MX6SLL_PAD_LCD_ENABLE__GPIO2_IO16 0x79 107*f126890aSEmmanuel Vadot MX6SLL_PAD_LCD_HSYNC__GPIO2_IO17 0x79 108*f126890aSEmmanuel Vadot MX6SLL_PAD_LCD_VSYNC__GPIO2_IO18 0x79 109*f126890aSEmmanuel Vadot MX6SLL_PAD_LCD_RESET__GPIO2_IO19 0x79 110*f126890aSEmmanuel Vadot MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x79 111*f126890aSEmmanuel Vadot MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x79 112*f126890aSEmmanuel Vadot MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x79 113*f126890aSEmmanuel Vadot MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x79 114*f126890aSEmmanuel Vadot >; 115*f126890aSEmmanuel Vadot }; 116*f126890aSEmmanuel Vadot 117*f126890aSEmmanuel Vadot pinctrl_i2c1: i2c1grp { 118*f126890aSEmmanuel Vadot fsl,pins = < 119*f126890aSEmmanuel Vadot MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1 120*f126890aSEmmanuel Vadot MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1 121*f126890aSEmmanuel Vadot >; 122*f126890aSEmmanuel Vadot }; 123*f126890aSEmmanuel Vadot 124*f126890aSEmmanuel Vadot pinctrl_i2c1_sleep: i2c1grp-sleep { 125*f126890aSEmmanuel Vadot fsl,pins = < 126*f126890aSEmmanuel Vadot MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1 127*f126890aSEmmanuel Vadot MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1 128*f126890aSEmmanuel Vadot >; 129*f126890aSEmmanuel Vadot }; 130*f126890aSEmmanuel Vadot 131*f126890aSEmmanuel Vadot pinctrl_i2c2: i2c2grp { 132*f126890aSEmmanuel Vadot fsl,pins = < 133*f126890aSEmmanuel Vadot MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1 134*f126890aSEmmanuel Vadot MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1 135*f126890aSEmmanuel Vadot >; 136*f126890aSEmmanuel Vadot }; 137*f126890aSEmmanuel Vadot 138*f126890aSEmmanuel Vadot pinctrl_i2c2_sleep: i2c2grp-sleep { 139*f126890aSEmmanuel Vadot fsl,pins = < 140*f126890aSEmmanuel Vadot MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1 141*f126890aSEmmanuel Vadot MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1 142*f126890aSEmmanuel Vadot >; 143*f126890aSEmmanuel Vadot }; 144*f126890aSEmmanuel Vadot 145*f126890aSEmmanuel Vadot pinctrl_i2c3: i2c3grp { 146*f126890aSEmmanuel Vadot fsl,pins = < 147*f126890aSEmmanuel Vadot MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1 148*f126890aSEmmanuel Vadot MX6SLL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1 149*f126890aSEmmanuel Vadot >; 150*f126890aSEmmanuel Vadot }; 151*f126890aSEmmanuel Vadot 152*f126890aSEmmanuel Vadot pinctrl_led: ledgrp { 153*f126890aSEmmanuel Vadot fsl,pins = < 154*f126890aSEmmanuel Vadot MX6SLL_PAD_SD1_DATA6__GPIO5_IO07 0x17059 155*f126890aSEmmanuel Vadot >; 156*f126890aSEmmanuel Vadot }; 157*f126890aSEmmanuel Vadot 158*f126890aSEmmanuel Vadot pinctrl_lm3630a_bl_gpio: lm3630a-bl-gpiogrp { 159*f126890aSEmmanuel Vadot fsl,pins = < 160*f126890aSEmmanuel Vadot MX6SLL_PAD_EPDC_PWR_CTRL3__GPIO2_IO10 0x10059 /* HWEN */ 161*f126890aSEmmanuel Vadot >; 162*f126890aSEmmanuel Vadot }; 163*f126890aSEmmanuel Vadot 164*f126890aSEmmanuel Vadot pinctrl_ricoh_gpio: ricoh-gpiogrp { 165*f126890aSEmmanuel Vadot fsl,pins = < 166*f126890aSEmmanuel Vadot MX6SLL_PAD_SD1_CLK__GPIO5_IO15 0x1b8b1 /* ricoh619 chg */ 167*f126890aSEmmanuel Vadot MX6SLL_PAD_SD1_DATA0__GPIO5_IO11 0x1b8b1 /* ricoh619 irq */ 168*f126890aSEmmanuel Vadot MX6SLL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 bat_low_int */ 169*f126890aSEmmanuel Vadot >; 170*f126890aSEmmanuel Vadot }; 171*f126890aSEmmanuel Vadot 172*f126890aSEmmanuel Vadot pinctrl_uart1: uart1grp { 173*f126890aSEmmanuel Vadot fsl,pins = < 174*f126890aSEmmanuel Vadot MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1 175*f126890aSEmmanuel Vadot MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1 176*f126890aSEmmanuel Vadot >; 177*f126890aSEmmanuel Vadot }; 178*f126890aSEmmanuel Vadot 179*f126890aSEmmanuel Vadot pinctrl_uart4: uart4grp { 180*f126890aSEmmanuel Vadot fsl,pins = < 181*f126890aSEmmanuel Vadot MX6SLL_PAD_KEY_ROW6__UART4_DCE_TX 0x1b0b1 182*f126890aSEmmanuel Vadot MX6SLL_PAD_KEY_COL6__UART4_DCE_RX 0x1b0b1 183*f126890aSEmmanuel Vadot >; 184*f126890aSEmmanuel Vadot }; 185*f126890aSEmmanuel Vadot 186*f126890aSEmmanuel Vadot pinctrl_usbotg1: usbotg1grp { 187*f126890aSEmmanuel Vadot fsl,pins = < 188*f126890aSEmmanuel Vadot MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059 189*f126890aSEmmanuel Vadot >; 190*f126890aSEmmanuel Vadot }; 191*f126890aSEmmanuel Vadot 192*f126890aSEmmanuel Vadot pinctrl_usdhc2: usdhc2grp { 193*f126890aSEmmanuel Vadot fsl,pins = < 194*f126890aSEmmanuel Vadot MX6SLL_PAD_SD2_CMD__SD2_CMD 0x17059 195*f126890aSEmmanuel Vadot MX6SLL_PAD_SD2_CLK__SD2_CLK 0x13059 196*f126890aSEmmanuel Vadot MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x17059 197*f126890aSEmmanuel Vadot MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x17059 198*f126890aSEmmanuel Vadot MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x17059 199*f126890aSEmmanuel Vadot MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x17059 200*f126890aSEmmanuel Vadot >; 201*f126890aSEmmanuel Vadot }; 202*f126890aSEmmanuel Vadot 203*f126890aSEmmanuel Vadot pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { 204*f126890aSEmmanuel Vadot fsl,pins = < 205*f126890aSEmmanuel Vadot MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170b9 206*f126890aSEmmanuel Vadot MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130b9 207*f126890aSEmmanuel Vadot MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170b9 208*f126890aSEmmanuel Vadot MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170b9 209*f126890aSEmmanuel Vadot MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170b9 210*f126890aSEmmanuel Vadot MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170b9 211*f126890aSEmmanuel Vadot >; 212*f126890aSEmmanuel Vadot }; 213*f126890aSEmmanuel Vadot 214*f126890aSEmmanuel Vadot pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { 215*f126890aSEmmanuel Vadot fsl,pins = < 216*f126890aSEmmanuel Vadot MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170f9 217*f126890aSEmmanuel Vadot MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130f9 218*f126890aSEmmanuel Vadot MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170f9 219*f126890aSEmmanuel Vadot MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170f9 220*f126890aSEmmanuel Vadot MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170f9 221*f126890aSEmmanuel Vadot MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170f9 222*f126890aSEmmanuel Vadot >; 223*f126890aSEmmanuel Vadot }; 224*f126890aSEmmanuel Vadot 225*f126890aSEmmanuel Vadot pinctrl_usdhc2_sleep: usdhc2grp-sleep { 226*f126890aSEmmanuel Vadot fsl,pins = < 227*f126890aSEmmanuel Vadot MX6SLL_PAD_SD2_CMD__GPIO5_IO04 0x100f9 228*f126890aSEmmanuel Vadot MX6SLL_PAD_SD2_CLK__GPIO5_IO05 0x100f9 229*f126890aSEmmanuel Vadot MX6SLL_PAD_SD2_DATA0__GPIO5_IO01 0x100f9 230*f126890aSEmmanuel Vadot MX6SLL_PAD_SD2_DATA1__GPIO4_IO30 0x100f9 231*f126890aSEmmanuel Vadot MX6SLL_PAD_SD2_DATA2__GPIO5_IO03 0x100f9 232*f126890aSEmmanuel Vadot MX6SLL_PAD_SD2_DATA3__GPIO4_IO28 0x100f9 233*f126890aSEmmanuel Vadot >; 234*f126890aSEmmanuel Vadot }; 235*f126890aSEmmanuel Vadot 236*f126890aSEmmanuel Vadot pinctrl_usdhc3: usdhc3grp { 237*f126890aSEmmanuel Vadot fsl,pins = < 238*f126890aSEmmanuel Vadot MX6SLL_PAD_SD3_CMD__SD3_CMD 0x11059 239*f126890aSEmmanuel Vadot MX6SLL_PAD_SD3_CLK__SD3_CLK 0x11059 240*f126890aSEmmanuel Vadot MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x11059 241*f126890aSEmmanuel Vadot MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x11059 242*f126890aSEmmanuel Vadot MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x11059 243*f126890aSEmmanuel Vadot MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x11059 244*f126890aSEmmanuel Vadot >; 245*f126890aSEmmanuel Vadot }; 246*f126890aSEmmanuel Vadot 247*f126890aSEmmanuel Vadot pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { 248*f126890aSEmmanuel Vadot fsl,pins = < 249*f126890aSEmmanuel Vadot MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170b9 250*f126890aSEmmanuel Vadot MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170b9 251*f126890aSEmmanuel Vadot MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170b9 252*f126890aSEmmanuel Vadot MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170b9 253*f126890aSEmmanuel Vadot MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170b9 254*f126890aSEmmanuel Vadot MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170b9 255*f126890aSEmmanuel Vadot >; 256*f126890aSEmmanuel Vadot }; 257*f126890aSEmmanuel Vadot 258*f126890aSEmmanuel Vadot pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { 259*f126890aSEmmanuel Vadot fsl,pins = < 260*f126890aSEmmanuel Vadot MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170f9 261*f126890aSEmmanuel Vadot MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170f9 262*f126890aSEmmanuel Vadot MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170f9 263*f126890aSEmmanuel Vadot MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170f9 264*f126890aSEmmanuel Vadot MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170f9 265*f126890aSEmmanuel Vadot MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170f9 266*f126890aSEmmanuel Vadot >; 267*f126890aSEmmanuel Vadot }; 268*f126890aSEmmanuel Vadot 269*f126890aSEmmanuel Vadot pinctrl_usdhc3_sleep: usdhc3grp-sleep { 270*f126890aSEmmanuel Vadot fsl,pins = < 271*f126890aSEmmanuel Vadot MX6SLL_PAD_SD3_CMD__GPIO5_IO21 0x100c1 272*f126890aSEmmanuel Vadot MX6SLL_PAD_SD3_CLK__GPIO5_IO18 0x100c1 273*f126890aSEmmanuel Vadot MX6SLL_PAD_SD3_DATA0__GPIO5_IO19 0x100c1 274*f126890aSEmmanuel Vadot MX6SLL_PAD_SD3_DATA1__GPIO5_IO20 0x100c1 275*f126890aSEmmanuel Vadot MX6SLL_PAD_SD3_DATA2__GPIO5_IO16 0x100c1 276*f126890aSEmmanuel Vadot MX6SLL_PAD_SD3_DATA3__GPIO5_IO17 0x100c1 277*f126890aSEmmanuel Vadot >; 278*f126890aSEmmanuel Vadot }; 279*f126890aSEmmanuel Vadot 280*f126890aSEmmanuel Vadot pinctrl_wifi_power: wifi-powergrp { 281*f126890aSEmmanuel Vadot fsl,pins = < 282*f126890aSEmmanuel Vadot MX6SLL_PAD_SD2_DATA6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */ 283*f126890aSEmmanuel Vadot >; 284*f126890aSEmmanuel Vadot }; 285*f126890aSEmmanuel Vadot 286*f126890aSEmmanuel Vadot pinctrl_wifi_reset: wifi-resetgrp { 287*f126890aSEmmanuel Vadot fsl,pins = < 288*f126890aSEmmanuel Vadot MX6SLL_PAD_SD2_DATA7__GPIO5_IO00 0x10059 /* WIFI_RST */ 289*f126890aSEmmanuel Vadot >; 290*f126890aSEmmanuel Vadot }; 291*f126890aSEmmanuel Vadot}; 292*f126890aSEmmanuel Vadot 293*f126890aSEmmanuel Vadot&leds { 294*f126890aSEmmanuel Vadot pinctrl-names = "default"; 295*f126890aSEmmanuel Vadot pinctrl-0 = <&pinctrl_led>; 296*f126890aSEmmanuel Vadot}; 297*f126890aSEmmanuel Vadot 298*f126890aSEmmanuel Vadot&lm3630a { 299*f126890aSEmmanuel Vadot pinctrl-names = "default"; 300*f126890aSEmmanuel Vadot pinctrl-0 = <&pinctrl_lm3630a_bl_gpio>; 301*f126890aSEmmanuel Vadot}; 302*f126890aSEmmanuel Vadot 303*f126890aSEmmanuel Vadot®_wifi { 304*f126890aSEmmanuel Vadot pinctrl-names = "default"; 305*f126890aSEmmanuel Vadot pinctrl-0 = <&pinctrl_wifi_power>; 306*f126890aSEmmanuel Vadot}; 307*f126890aSEmmanuel Vadot 308*f126890aSEmmanuel Vadot&ricoh619 { 309*f126890aSEmmanuel Vadot pinctrl-names = "default"; 310*f126890aSEmmanuel Vadot pinctrl-0 = <&pinctrl_ricoh_gpio>; 311*f126890aSEmmanuel Vadot}; 312*f126890aSEmmanuel Vadot 313*f126890aSEmmanuel Vadot&uart1 { 314*f126890aSEmmanuel Vadot pinctrl-names = "default"; 315*f126890aSEmmanuel Vadot pinctrl-0 = <&pinctrl_uart1>; 316*f126890aSEmmanuel Vadot}; 317*f126890aSEmmanuel Vadot 318*f126890aSEmmanuel Vadot&uart4 { 319*f126890aSEmmanuel Vadot pinctrl-names = "default"; 320*f126890aSEmmanuel Vadot pinctrl-0 = <&pinctrl_uart4>; 321*f126890aSEmmanuel Vadot}; 322*f126890aSEmmanuel Vadot 323*f126890aSEmmanuel Vadot&usdhc2 { 324*f126890aSEmmanuel Vadot pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep"; 325*f126890aSEmmanuel Vadot pinctrl-0 = <&pinctrl_usdhc2>; 326*f126890aSEmmanuel Vadot pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 327*f126890aSEmmanuel Vadot pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 328*f126890aSEmmanuel Vadot pinctrl-3 = <&pinctrl_usdhc2_sleep>; 329*f126890aSEmmanuel Vadot}; 330*f126890aSEmmanuel Vadot 331*f126890aSEmmanuel Vadot&usdhc3 { 332*f126890aSEmmanuel Vadot pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep"; 333*f126890aSEmmanuel Vadot pinctrl-0 = <&pinctrl_usdhc3>; 334*f126890aSEmmanuel Vadot pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 335*f126890aSEmmanuel Vadot pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 336*f126890aSEmmanuel Vadot pinctrl-3 = <&pinctrl_usdhc3_sleep>; 337*f126890aSEmmanuel Vadot}; 338*f126890aSEmmanuel Vadot 339*f126890aSEmmanuel Vadot&wifi_pwrseq { 340*f126890aSEmmanuel Vadot pinctrl-names = "default"; 341*f126890aSEmmanuel Vadot pinctrl-0 = <&pinctrl_wifi_reset>; 342*f126890aSEmmanuel Vadot}; 343