1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright 2018-2022 Toradex 4 */ 5 6#include "imx6ull.dtsi" 7 8/ { 9 /* Ethernet aliases to ensure correct MAC addresses */ 10 aliases { 11 ethernet0 = &fec2; 12 ethernet1 = &fec1; 13 }; 14 15 backlight: backlight { 16 compatible = "pwm-backlight"; 17 brightness-levels = <0 4 8 16 32 64 128 255>; 18 default-brightness-level = <6>; 19 enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; 20 pinctrl-names = "default"; 21 pinctrl-0 = <&pinctrl_gpio_bl_on>; 22 power-supply = <®_3v3>; 23 pwms = <&pwm4 0 5000000 1>; 24 status = "disabled"; 25 }; 26 27 connector { 28 compatible = "gpio-usb-b-connector", "usb-b-connector"; 29 pinctrl-names = "default"; 30 pinctrl-0 = <&pinctrl_snvs_usbc_det>; 31 id-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; /* SODIMM 137 / USBC_DET */ 32 label = "USBC"; 33 self-powered; 34 type = "micro"; 35 36 port { 37 usb_dr_connector: endpoint { 38 remote-endpoint = <&usb1_drd_sw>; 39 }; 40 }; 41 }; 42 43 gpio-keys { 44 compatible = "gpio-keys"; 45 pinctrl-names = "default"; 46 pinctrl-0 = <&pinctrl_snvs_gpiokeys>; 47 48 key-wakeup { 49 debounce-interval = <10>; 50 gpios = <&gpio5 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* SODIMM 45 */ 51 label = "Wake-Up"; 52 linux,code = <KEY_WAKEUP>; 53 wakeup-source; 54 }; 55 }; 56 57 panel_dpi: panel-dpi { 58 compatible = "edt,et057090dhu"; 59 backlight = <&backlight>; 60 power-supply = <®_3v3>; 61 status = "disabled"; 62 63 port { 64 lcd_panel_in: endpoint { 65 remote-endpoint = <&lcdif_out>; 66 }; 67 }; 68 }; 69 70 reg_module_3v3: regulator-module-3v3 { 71 compatible = "regulator-fixed"; 72 regulator-always-on; 73 regulator-name = "+V3.3"; 74 regulator-min-microvolt = <3300000>; 75 regulator-max-microvolt = <3300000>; 76 }; 77 78 reg_module_3v3_avdd: regulator-module-3v3-avdd { 79 compatible = "regulator-fixed"; 80 regulator-always-on; 81 regulator-name = "+V3.3_AVDD_AUDIO"; 82 regulator-min-microvolt = <3300000>; 83 regulator-max-microvolt = <3300000>; 84 }; 85 86 reg_sd1_vqmmc: regulator-sd1-vqmmc { 87 compatible = "regulator-gpio"; 88 gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; 89 pinctrl-names = "default"; 90 pinctrl-0 = <&pinctrl_snvs_reg_sd>; 91 regulator-always-on; 92 regulator-name = "+V3.3_1.8_SD"; 93 regulator-min-microvolt = <1800000>; 94 regulator-max-microvolt = <3300000>; 95 states = <1800000 0x1 3300000 0x0>; 96 vin-supply = <®_module_3v3>; 97 }; 98 99 reg_eth_phy: regulator-eth-phy { 100 compatible = "regulator-fixed-clock"; 101 regulator-boot-on; 102 regulator-min-microvolt = <3300000>; 103 regulator-max-microvolt = <3300000>; 104 regulator-name = "+V3.3_ETH"; 105 regulator-type = "voltage"; 106 vin-supply = <®_module_3v3>; 107 clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>; 108 startup-delay-us = <150000>; 109 }; 110}; 111 112&adc1 { 113 vref-supply = <®_module_3v3_avdd>; 114 pinctrl-names = "default"; 115 pinctrl-0 = <&pinctrl_adc1>; 116}; 117 118&can1 { 119 pinctrl-names = "default"; 120 pinctrl-0 = <&pinctrl_flexcan1>; 121 status = "disabled"; 122}; 123 124&can2 { 125 pinctrl-names = "default"; 126 pinctrl-0 = <&pinctrl_flexcan2>; 127 status = "disabled"; 128}; 129 130/* Colibri SPI */ 131&ecspi1 { 132 cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; 133 pinctrl-names = "default"; 134 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; 135}; 136 137/* Ethernet */ 138&fec2 { 139 pinctrl-names = "default", "sleep"; 140 pinctrl-0 = <&pinctrl_enet2>; 141 pinctrl-1 = <&pinctrl_enet2_sleep>; 142 phy-mode = "rmii"; 143 phy-handle = <ðphy1>; 144 phy-supply = <®_eth_phy>; 145 status = "okay"; 146 147 mdio { 148 #address-cells = <1>; 149 #size-cells = <0>; 150 151 ethphy1: ethernet-phy@2 { 152 compatible = "ethernet-phy-ieee802.3-c22"; 153 max-speed = <100>; 154 reg = <2>; 155 }; 156 }; 157}; 158 159/* NAND */ 160&gpmi { 161 pinctrl-names = "default"; 162 pinctrl-0 = <&pinctrl_gpmi_nand>; 163 fsl,use-minimum-ecc; 164 nand-on-flash-bbt; 165 nand-ecc-mode = "hw"; 166 nand-ecc-strength = <8>; 167 nand-ecc-step-size = <512>; 168 status = "okay"; 169}; 170 171/* I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) */ 172&i2c1 { 173 pinctrl-names = "default", "gpio"; 174 pinctrl-0 = <&pinctrl_i2c1>; 175 pinctrl-1 = <&pinctrl_i2c1_gpio>; 176 sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 177 scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 178 status = "disabled"; 179 180 /* Atmel maxtouch controller */ 181 atmel_mxt_ts: touchscreen@4a { 182 compatible = "atmel,maxtouch"; 183 pinctrl-names = "default"; 184 pinctrl-0 = <&pinctrl_atmel_conn &pinctrl_atmel_snvs_conn>; 185 reg = <0x4a>; 186 interrupt-parent = <&gpio5>; 187 interrupts = <4 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 / INT */ 188 reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* SODIMM 106 / RST */ 189 status = "disabled"; 190 }; 191}; 192 193/* 194 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and 195 * touch screen controller 196 */ 197&i2c2 { 198 /* Use low frequency to compensate for the high pull-up values. */ 199 clock-frequency = <40000>; 200 pinctrl-names = "default", "gpio"; 201 pinctrl-0 = <&pinctrl_i2c2>; 202 pinctrl-1 = <&pinctrl_i2c2_gpio>; 203 sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 204 scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 205 status = "okay"; 206 207 ad7879_ts: touchscreen@2c { 208 compatible = "adi,ad7879-1"; 209 pinctrl-names = "default"; 210 pinctrl-0 = <&pinctrl_snvs_ad7879_int>; 211 reg = <0x2c>; 212 interrupt-parent = <&gpio5>; 213 interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 214 touchscreen-max-pressure = <4096>; 215 adi,resistance-plate-x = <120>; 216 adi,first-conversion-delay = /bits/ 8 <3>; 217 adi,acquisition-time = /bits/ 8 <1>; 218 adi,median-filter-size = /bits/ 8 <2>; 219 adi,averaging = /bits/ 8 <1>; 220 adi,conversion-interval = /bits/ 8 <255>; 221 status = "disabled"; 222 }; 223}; 224 225&lcdif { 226 pinctrl-names = "default"; 227 pinctrl-0 = <&pinctrl_lcdif_dat 228 &pinctrl_lcdif_ctrl>; 229 status = "disabled"; 230 231 port { 232 lcdif_out: endpoint { 233 remote-endpoint = <&lcd_panel_in>; 234 }; 235 }; 236}; 237 238/* PWM <A> */ 239&pwm4 { 240 pinctrl-names = "default"; 241 pinctrl-0 = <&pinctrl_pwm4>; 242}; 243 244/* PWM <B> */ 245&pwm5 { 246 pinctrl-names = "default"; 247 pinctrl-0 = <&pinctrl_pwm5>; 248}; 249 250/* PWM <C> */ 251&pwm6 { 252 pinctrl-names = "default"; 253 pinctrl-0 = <&pinctrl_pwm6>; 254}; 255 256/* PWM <D> */ 257&pwm7 { 258 pinctrl-names = "default"; 259 pinctrl-0 = <&pinctrl_pwm7>; 260}; 261 262&sdma { 263 status = "okay"; 264}; 265 266&snvs_pwrkey { 267 status = "disabled"; 268}; 269 270/* Colibri UART_A */ 271&uart1 { 272 pinctrl-names = "default"; 273 pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>; 274 uart-has-rtscts; 275 fsl,dte-mode; 276}; 277 278/* Colibri UART_B */ 279&uart2 { 280 pinctrl-names = "default"; 281 pinctrl-0 = <&pinctrl_uart2>; 282 uart-has-rtscts; 283 fsl,dte-mode; 284}; 285 286/* Colibri UART_C */ 287&uart5 { 288 pinctrl-names = "default"; 289 pinctrl-0 = <&pinctrl_uart5>; 290 fsl,dte-mode; 291}; 292 293/* Colibri USBC */ 294&usbotg1 { 295 dr_mode = "otg"; 296 srp-disable; 297 hnp-disable; 298 adp-disable; 299 usb-role-switch; 300 301 port { 302 usb1_drd_sw: endpoint { 303 remote-endpoint = <&usb_dr_connector>; 304 }; 305 }; 306}; 307 308/* Colibri USBH */ 309&usbotg2 { 310 dr_mode = "host"; 311}; 312 313/* Colibri MMC/SD */ 314&usdhc1 { 315 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 316 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>; 317 pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>; 318 pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>; 319 pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd_sleep>; 320 assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>; 321 assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; 322 assigned-clock-rates = <0>, <198000000>; 323 bus-width = <4>; 324 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* MMC_CD */ 325 disable-wp; 326 keep-power-in-suspend; 327 no-1-8-v; 328 vqmmc-supply = <®_sd1_vqmmc>; 329 wakeup-source; 330}; 331 332&wdog1 { 333 pinctrl-names = "default"; 334 pinctrl-0 = <&pinctrl_wdog>; 335 fsl,ext-reset-output; 336}; 337 338&iomuxc { 339 pinctrl_adc1: adc1grp { 340 fsl,pins = < 341 MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x3000 /* SODIMM 8 */ 342 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x3000 /* SODIMM 6 */ 343 MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x3000 /* SODIMM 4 */ 344 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x3000 /* SODIMM 2 */ 345 >; 346 }; 347 348 pinctrl_atmel_adap: atmeladapgrp { 349 fsl,pins = < 350 MX6UL_PAD_NAND_DQS__GPIO4_IO16 0xb0a0 /* SODIMM 28 */ 351 MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0xb0a0 /* SODIMM 30 */ 352 >; 353 }; 354 355 pinctrl_atmel_conn: atmelconngrp { 356 fsl,pins = < 357 MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0xb0a0 /* SODIMM 106 */ 358 >; 359 }; 360 361 pinctrl_can_int: canintgrp { 362 fsl,pins = < 363 MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x13010 /* SODIMM 73 */ 364 >; 365 }; 366 367 pinctrl_enet2: enet2grp { 368 fsl,pins = < 369 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 370 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 371 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 372 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 373 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 374 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 375 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 376 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 377 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 378 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 379 >; 380 }; 381 382 pinctrl_enet2_sleep: enet2-sleepgrp { 383 fsl,pins = < 384 MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0 385 MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0 386 MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x0 387 MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x0 388 MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x0 389 MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0 390 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 391 MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0 392 MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x0 393 MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x0 394 >; 395 }; 396 397 pinctrl_ecspi1_cs: ecspi1csgrp { 398 fsl,pins = < 399 MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x70a0 /* SODIMM 86 */ 400 >; 401 }; 402 403 pinctrl_ecspi1: ecspi1grp { 404 fsl,pins = < 405 MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0 /* SODIMM 88 */ 406 MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0 /* SODIMM 92 */ 407 MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100a0 /* SODIMM 90 */ 408 >; 409 }; 410 411 pinctrl_flexcan1: flexcan1grp { 412 fsl,pins = < 413 MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020 414 MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020 415 >; 416 }; 417 418 pinctrl_flexcan2: flexcan2grp { 419 fsl,pins = < 420 MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020 421 MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020 422 >; 423 }; 424 425 pinctrl_gpio_bl_on: gpioblongrp { 426 fsl,pins = < 427 MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x30a0 /* SODIMM 71 */ 428 >; 429 }; 430 431 pinctrl_gpio1: gpio1grp { 432 fsl,pins = < 433 MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x10b0 /* SODIMM 77 */ 434 MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x70a0 /* SODIMM 99 */ 435 MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x10b0 /* SODIMM 133 */ 436 MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x10b0 /* SODIMM 135 */ 437 MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x10b0 /* SODIMM 100 */ 438 MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x70a0 /* SODIMM 102 */ 439 MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x10b0 /* SODIMM 104 */ 440 MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x10b0 /* SODIMM 186 */ 441 >; 442 }; 443 444 pinctrl_gpio2: gpio2grp { /* Camera */ 445 fsl,pins = < 446 MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x10b0 /* SODIMM 69 */ 447 MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x10b0 /* SODIMM 75 */ 448 MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x10b0 /* SODIMM 85 */ 449 MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x10b0 /* SODIMM 96 */ 450 MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x10b0 /* SODIMM 98 */ 451 >; 452 }; 453 454 pinctrl_gpio3: gpio3grp { /* CAN2 */ 455 fsl,pins = < 456 MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x10b0 /* SODIMM 178 */ 457 MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x10b0 /* SODIMM 188 */ 458 >; 459 }; 460 461 pinctrl_gpio4: gpio4grp { 462 fsl,pins = < 463 MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x10b0 /* SODIMM 65 */ 464 >; 465 }; 466 467 pinctrl_gpio6: gpio6grp { /* Wifi pins */ 468 fsl,pins = < 469 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x10b0 /* SODIMM 89 */ 470 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x10b0 /* SODIMM 79 */ 471 MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x10b0 /* SODIMM 81 */ 472 MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x10b0 /* SODIMM 97 */ 473 MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x10b0 /* SODIMM 101 */ 474 MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0 /* SODIMM 103 */ 475 MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x10b0 /* SODIMM 94 */ 476 >; 477 }; 478 479 pinctrl_gpio7: gpio7grp { /* CAN1 */ 480 fsl,pins = < 481 MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0xb0b0/* SODIMM 55 */ 482 MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0xb0b0 /* SODIMM 63 */ 483 >; 484 }; 485 486 /* 487 * With an eMMC instead of a raw NAND device the following pins 488 * are available at SODIMM pins. 489 */ 490 pinctrl_gpmi_gpio: gpmigpiogrp { 491 fsl,pins = < 492 MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x10b0 /* SODIMM 140 */ 493 MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0x10b0 /* SODIMM 144 */ 494 MX6UL_PAD_NAND_CLE__GPIO4_IO15 0x10b0 /* SODIMM 146 */ 495 MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x10b0 /* SODIMM 142 */ 496 >; 497 }; 498 499 pinctrl_gpmi_nand: gpminandgrp { 500 fsl,pins = < 501 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9 502 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x100a9 503 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x100a9 504 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x100a9 505 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x100a9 506 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x100a9 507 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x100a9 508 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x100a9 509 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x100a9 510 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x100a9 511 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x100a9 512 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x100a9 513 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x100a9 514 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x100a9 515 >; 516 }; 517 518 pinctrl_i2c1: i2c1grp { 519 fsl,pins = < 520 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 /* SODIMM 196 */ 521 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 /* SODIMM 194 */ 522 >; 523 }; 524 525 pinctrl_i2c1_gpio: i2c1-gpiogrp { 526 fsl,pins = < 527 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0 /* SODIMM 196 */ 528 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0 /* SODIMM 194 */ 529 >; 530 }; 531 532 pinctrl_i2c2: i2c2grp { 533 fsl,pins = < 534 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001f8b0 535 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001f8b0 536 >; 537 }; 538 539 pinctrl_i2c2_gpio: i2c2-gpiogrp { 540 fsl,pins = < 541 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001f8b0 542 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001f8b0 543 >; 544 }; 545 546 pinctrl_lcdif_dat: lcdifdatgrp { 547 fsl,pins = < 548 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x00079 /* SODIMM 76 */ 549 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x00079 /* SODIMM 70 */ 550 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x00079 /* SODIMM 60 */ 551 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x00079 /* SODIMM 58 */ 552 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x00079 /* SODIMM 78 */ 553 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x00079 /* SODIMM 72 */ 554 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x00079 /* SODIMM 80 */ 555 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x00079 /* SODIMM 46 */ 556 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x00079 /* SODIMM 62 */ 557 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x00079 /* SODIMM 48 */ 558 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x00079 /* SODIMM 74 */ 559 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x00079 /* SODIMM 50 */ 560 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x00079 /* SODIMM 52 */ 561 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x00079 /* SODIMM 54 */ 562 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x00079 /* SODIMM 66 */ 563 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x00079 /* SODIMM 64 */ 564 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x00079 /* SODIMM 57 */ 565 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x00079 /* SODIMM 61 */ 566 >; 567 }; 568 569 pinctrl_lcdif_ctrl: lcdifctrlgrp { 570 fsl,pins = < 571 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x00079 /* SODIMM 56 */ 572 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x00079 /* SODIMM 44 */ 573 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x00079 /* SODIMM 68 */ 574 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x00079 /* SODIMM 82 */ 575 >; 576 }; 577 578 pinctrl_pwm4: pwm4grp { 579 fsl,pins = < 580 MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x00079 /* SODIMM 59 */ 581 >; 582 }; 583 584 pinctrl_pwm5: pwm5grp { 585 fsl,pins = < 586 MX6UL_PAD_NAND_DQS__PWM5_OUT 0x00079 /* SODIMM 28 */ 587 >; 588 }; 589 590 pinctrl_pwm6: pwm6grp { 591 fsl,pins = < 592 MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079 /* SODIMM 30 */ 593 >; 594 }; 595 596 pinctrl_pwm7: pwm7grp { 597 fsl,pins = < 598 MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00079 /* SODIMM 67 */ 599 >; 600 }; 601 602 pinctrl_uart1: uart1grp { 603 fsl,pins = < 604 MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x1b0b1 /* SODIMM 33 */ 605 MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x1b0b1 /* SODIMM 35 */ 606 MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x1b0b1 /* SODIMM 27 */ 607 MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x1b0b1 /* SODIMM 25 */ 608 >; 609 }; 610 611 pinctrl_uart1_ctrl1: uart1ctrl1grp { /* Additional DTR, DCD */ 612 fsl,pins = < 613 MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x70a0 /* SODIMM 31 / DCD */ 614 MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x10b0 /* SODIMM 29 / DSR */ 615 MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x90b1 /* SODIMM 23 / DTR */ 616 MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x10b0 /* SODIMM 37 / RI */ 617 >; 618 }; 619 620 pinctrl_uart2: uart2grp { 621 fsl,pins = < 622 MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 /* SODIMM 36 */ 623 MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 /* SODIMM 38 */ 624 MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1 /* SODIMM 32 */ 625 MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 /* SODIMM 34 */ 626 >; 627 }; 628 pinctrl_uart5: uart5grp { 629 fsl,pins = < 630 MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x1b0b1 /* SODIMM 19 */ 631 MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1 /* SODIMM 21 */ 632 >; 633 }; 634 635 pinctrl_usbh_reg: usbhreggrp { 636 fsl,pins = < 637 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0 /* SODIMM 129 / USBH_PEN */ 638 >; 639 }; 640 641 pinctrl_usdhc1: usdhc1grp { 642 fsl,pins = < 643 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 /* SODIMM 47 */ 644 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 /* SODIMM 190 */ 645 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 /* SODIMM 192 */ 646 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 /* SODIMM 49 */ 647 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 /* SODIMM 51 */ 648 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 /* SODIMM 53 */ 649 >; 650 }; 651 652 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 653 fsl,pins = < 654 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 655 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 656 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 657 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 658 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 659 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 660 >; 661 }; 662 663 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 664 fsl,pins = < 665 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 666 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 667 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 668 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 669 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 670 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 671 >; 672 }; 673 674 pinctrl_usdhc2: usdhc2grp { 675 fsl,pins = < 676 MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17069 677 MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17069 678 MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17069 679 MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17069 680 MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17069 681 MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10069 682 683 MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x10 684 >; 685 }; 686 687 pinctrl_usdhc2emmc: usdhc2emmcgrp { 688 fsl,pins = < 689 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 690 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 691 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 692 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 693 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 694 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 695 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 696 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 697 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 698 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 699 >; 700 }; 701 702 pinctrl_wdog: wdoggrp { 703 fsl,pins = < 704 MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 705 >; 706 }; 707}; 708 709&iomuxc_snvs { 710 pinctrl_atmel_snvs_conn: atmelsnvsconngrp { 711 fsl,pins = < 712 MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0xb0a0 /* SODIMM 107 */ 713 >; 714 }; 715 716 pinctrl_snvs_gpio1: snvsgpio1grp { 717 fsl,pins = < 718 MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x110a0 /* SODIMM 93 */ 719 MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x110a0 /* SODIMM 95 */ 720 MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x1b0a0 /* SODIMM 105 */ 721 MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0a0 /* SODIMM 131 / USBH_OC */ 722 MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x110a0 /* SODIMM 138 */ 723 >; 724 }; 725 726 pinctrl_snvs_gpio3: snvsgpio3grp { /* Wifi pins */ 727 fsl,pins = < 728 MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 /* SODIMM 127 */ 729 >; 730 }; 731 732 pinctrl_snvs_ad7879_int: snvsad7879intgrp { /* TOUCH Interrupt */ 733 fsl,pins = < 734 MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x100b0 735 >; 736 }; 737 738 pinctrl_snvs_reg_sd: snvsregsdgrp { 739 fsl,pins = < 740 MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x400100b0 741 >; 742 }; 743 744 pinctrl_snvs_usbc_det: snvsusbcdetgrp { 745 fsl,pins = < 746 MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x130b0 747 >; 748 }; 749 750 pinctrl_snvs_gpiokeys: snvsgpiokeysgrp { 751 fsl,pins = < 752 MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130a0 /* SODIMM 45 / WAKE_UP */ 753 >; 754 }; 755 756 pinctrl_snvs_usdhc1_cd: snvsusdhc1cdgrp { 757 fsl,pins = < 758 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0a0 /* SODIMM 43 / MMC_CD */ 759 >; 760 }; 761 762 pinctrl_snvs_usdhc1_cd_sleep: snvsusdhc1cd-sleepgrp { 763 fsl,pins = < 764 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0 765 >; 766 }; 767 768 pinctrl_snvs_wifi_pdn: snvswifipdngrp { 769 fsl,pins = < 770 MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 771 >; 772 }; 773}; 774