1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2//
3// Copyright 2017 NXP
4
5/dts-v1/;
6
7#include "imx7d.dtsi"
8
9/ {
10	backlight: backlight {
11		compatible = "pwm-backlight";
12		pwms = <&pwm4 0 50000 0>;
13		brightness-levels = <0 36 72 108 144 180 216 255>;
14		default-brightness-level = <6>;
15	};
16
17	/* Will be filled by the bootloader */
18	memory@80000000 {
19		device_type = "memory";
20		reg = <0x80000000 0>;
21	};
22
23	panel {
24		compatible = "vxt,vl050-8048nt-c01";
25		backlight = <&backlight>;
26		power-supply = <&reg_lcd_3v3>;
27
28		port {
29			panel_in: endpoint {
30				remote-endpoint = <&display_out>;
31			};
32		};
33	};
34
35	reg_lcd_3v3: regulator-lcd-3v3 {
36		compatible = "regulator-fixed";
37		pinctrl-names = "default";
38		pinctrl-0 = <&pinctrl_reg_lcdreg_on>;
39		regulator-name = "lcd-3v3";
40		regulator-min-microvolt = <3300000>;
41		regulator-max-microvolt = <3300000>;
42		gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>;
43		enable-active-high;
44	};
45
46	reg_wlreg_on: regulator-wlreg_on {
47		compatible = "regulator-fixed";
48		pinctrl-names = "default";
49		pinctrl-0 = <&pinctrl_reg_wlreg_on>;
50		regulator-name = "wlreg_on";
51		regulator-min-microvolt = <3300000>;
52		regulator-max-microvolt = <3300000>;
53		gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
54		enable-active-high;
55	};
56
57	reg_2p5v: regulator-2p5v {
58		compatible = "regulator-fixed";
59		regulator-name = "2P5V";
60		regulator-min-microvolt = <2500000>;
61		regulator-max-microvolt = <2500000>;
62		regulator-always-on;
63	};
64
65	reg_3p3v: regulator-3p3v {
66		compatible = "regulator-fixed";
67		regulator-name = "3P3V";
68		regulator-min-microvolt = <3300000>;
69		regulator-max-microvolt = <3300000>;
70		regulator-always-on;
71	};
72
73	reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
74		pinctrl-names = "default";
75		pinctrl-0 = <&pinctrl_usbotg1_pwr>;
76		compatible = "regulator-fixed";
77		regulator-name = "usb_otg1_vbus";
78		regulator-min-microvolt = <5000000>;
79		regulator-max-microvolt = <5000000>;
80		gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
81	};
82
83	reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
84		compatible = "regulator-fixed";
85		regulator-name = "usb_otg2_vbus";
86		regulator-min-microvolt = <5000000>;
87		regulator-max-microvolt = <5000000>;
88	};
89
90	reg_vref_1v8: regulator-vref-1v8 {
91		compatible = "regulator-fixed";
92		regulator-name = "vref-1v8";
93		regulator-min-microvolt = <1800000>;
94		regulator-max-microvolt = <1800000>;
95	};
96
97	usdhc2_pwrseq: usdhc2_pwrseq {
98		compatible = "mmc-pwrseq-simple";
99		clocks = <&clks IMX7D_CLKO2_ROOT_DIV>;
100		clock-names = "ext_clock";
101	};
102};
103
104&clks {
105	assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
106			  <&clks IMX7D_CLKO2_ROOT_DIV>;
107	assigned-clock-parents = <&clks IMX7D_CKIL>;
108	assigned-clock-rates = <0>, <32768>;
109};
110
111&cpu0 {
112	cpu-supply = <&sw1a_reg>;
113};
114
115&cpu1 {
116	cpu-supply = <&sw1a_reg>;
117};
118
119&ecspi3 {
120	cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
121	pinctrl-names = "default";
122	pinctrl-0 = <&pinctrl_ecspi3>;
123	status = "okay";
124};
125
126&fec1 {
127	pinctrl-names = "default";
128	pinctrl-0 = <&pinctrl_enet1>;
129	assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
130			  <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
131	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
132	assigned-clock-rates = <0>, <100000000>;
133	phy-mode = "rgmii-id";
134	phy-handle = <&ethphy0>;
135	fsl,magic-packet;
136	phy-reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
137	status = "okay";
138
139	mdio {
140		#address-cells = <1>;
141		#size-cells = <0>;
142
143		ethphy0: ethernet-phy@1 {
144			compatible = "ethernet-phy-ieee802.3-c22";
145			reg = <1>;
146			status = "okay";
147		};
148	};
149};
150
151&flexcan1 {
152	pinctrl-names = "default";
153	pinctrl-0 = <&pinctrl_can1>;
154	status = "okay";
155};
156
157&flexcan2 {
158	pinctrl-names = "default";
159	pinctrl-0 = <&pinctrl_can2>;
160	status = "okay";
161};
162
163&i2c1 {
164	clock-frequency = <100000>;
165	pinctrl-names = "default";
166	pinctrl-0 = <&pinctrl_i2c1>;
167	status = "okay";
168};
169
170&i2c2 {
171	pinctrl-names = "default";
172	pinctrl-0 = <&pinctrl_i2c2>;
173	status = "okay";
174};
175
176&i2c4 {
177	pinctrl-names = "default";
178	pinctrl-0 = <&pinctrl_i2c4>;
179	status = "okay";
180
181	pmic: pmic@8 {
182		compatible = "fsl,pfuze3000";
183		reg = <0x08>;
184
185		regulators {
186			sw1a_reg: sw1a {
187				regulator-min-microvolt = <700000>;
188				regulator-max-microvolt = <3300000>;
189				regulator-boot-on;
190				regulator-always-on;
191				regulator-ramp-delay = <6250>;
192			};
193			/* use sw1c_reg to align with pfuze100/pfuze200 */
194			sw1c_reg: sw1b {
195				regulator-min-microvolt = <700000>;
196				regulator-max-microvolt = <1475000>;
197				regulator-boot-on;
198				regulator-always-on;
199				regulator-ramp-delay = <6250>;
200			};
201
202			sw2_reg: sw2 {
203				regulator-min-microvolt = <1800000>;
204				regulator-max-microvolt = <1850000>;
205				regulator-boot-on;
206				regulator-always-on;
207			};
208
209			sw3a_reg: sw3 {
210				regulator-min-microvolt = <900000>;
211				regulator-max-microvolt = <1650000>;
212				regulator-boot-on;
213				regulator-always-on;
214			};
215
216			swbst_reg: swbst {
217				regulator-min-microvolt = <5000000>;
218				regulator-max-microvolt = <5150000>;
219			};
220
221			snvs_reg: vsnvs {
222				regulator-min-microvolt = <1000000>;
223				regulator-max-microvolt = <3000000>;
224				regulator-boot-on;
225				regulator-always-on;
226			};
227
228			vref_reg: vrefddr {
229				regulator-boot-on;
230				regulator-always-on;
231			};
232
233			vgen1_reg: vldo1 {
234				regulator-min-microvolt = <1800000>;
235				regulator-max-microvolt = <3300000>;
236				regulator-always-on;
237			};
238
239			vgen2_reg: vldo2 {
240				regulator-min-microvolt = <800000>;
241				regulator-max-microvolt = <1550000>;
242			};
243
244			vgen3_reg: vccsd {
245				regulator-min-microvolt = <2850000>;
246				regulator-max-microvolt = <3300000>;
247				regulator-always-on;
248			};
249
250			vgen4_reg: v33 {
251				regulator-min-microvolt = <2850000>;
252				regulator-max-microvolt = <3300000>;
253				regulator-always-on;
254			};
255
256			vgen5_reg: vldo3 {
257				regulator-min-microvolt = <1800000>;
258				regulator-max-microvolt = <3300000>;
259				regulator-always-on;
260			};
261
262			vgen6_reg: vldo4 {
263				regulator-min-microvolt = <1800000>;
264				regulator-max-microvolt = <3300000>;
265				regulator-always-on;
266			};
267		};
268	};
269};
270
271&lcdif {
272	pinctrl-names = "default";
273	pinctrl-0 = <&pinctrl_lcdif>;
274	status = "okay";
275
276	port {
277		display_out: endpoint {
278			remote-endpoint = <&panel_in>;
279		};
280	};
281};
282
283&sai1 {
284	pinctrl-names = "default";
285	pinctrl-0 = <&pinctrl_sai1>;
286	assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
287			  <&clks IMX7D_SAI1_ROOT_CLK>;
288	assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
289	assigned-clock-rates = <0>, <24576000>;
290	status = "okay";
291};
292
293
294&pwm1 {
295	pinctrl-names = "default";
296	pinctrl-0 = <&pinctrl_pwm1>;
297	status = "okay";
298};
299
300&pwm2 {
301	pinctrl-names = "default";
302	pinctrl-0 = <&pinctrl_pwm2>;
303	status = "okay";
304};
305
306&pwm3 {
307	pinctrl-names = "default";
308	pinctrl-0 = <&pinctrl_pwm3>;
309	status = "okay";
310};
311
312&pwm4 { /* Backlight */
313	pinctrl-names = "default";
314	pinctrl-0 = <&pinctrl_pwm4>;
315	status = "okay";
316};
317
318&uart5 {
319	pinctrl-names = "default";
320	pinctrl-0 = <&pinctrl_uart5>;
321	assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
322	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
323	status = "okay";
324};
325
326&uart6 {
327	pinctrl-names = "default";
328	pinctrl-0 = <&pinctrl_uart6>;
329	assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
330	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
331	uart-has-rtscts;
332	status = "okay";
333};
334
335&uart7 { /* Bluetooth */
336	pinctrl-names = "default";
337	pinctrl-0 = <&pinctrl_uart7>;
338	assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>;
339	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
340	uart-has-rtscts;
341	status = "okay";
342};
343
344&usbotg1 {
345	vbus-supply = <&reg_usb_otg1_vbus>;
346	status = "okay";
347};
348
349&usbotg2 {
350	vbus-supply = <&reg_usb_otg2_vbus>;
351	dr_mode = "host";
352	status = "okay";
353};
354
355&usdhc1 {
356	pinctrl-names = "default", "state_100mhz", "state_200mhz";
357	pinctrl-0 = <&pinctrl_usdhc1>;
358	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
359	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
360	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
361	bus-width = <4>;
362	fsl,tuning-step = <2>;
363	vmmc-supply = <&reg_3p3v>;
364	wakeup-source;
365	no-1-8-v;
366	keep-power-in-suspend;
367	status = "okay";
368};
369
370&usdhc2 { /* Wifi SDIO */
371	pinctrl-names = "default";
372	pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_wifi_clk>;
373	no-1-8-v;
374	non-removable;
375	keep-power-in-suspend;
376	wakeup-source;
377	vmmc-supply = <&reg_wlreg_on>;
378	mmc-pwrseq = <&usdhc2_pwrseq>;
379	status = "okay";
380};
381
382&usdhc3 {
383	pinctrl-names = "default", "state_100mhz", "state_200mhz";
384	pinctrl-0 = <&pinctrl_usdhc3>;
385	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
386	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
387	assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
388	assigned-clock-rates = <400000000>;
389	bus-width = <8>;
390	no-1-8-v;
391	fsl,tuning-step = <2>;
392	non-removable;
393	status = "okay";
394};
395
396&wdog1 {
397	pinctrl-names = "default";
398	pinctrl-0 = <&pinctrl_wdog>;
399	fsl,ext-reset-output;
400	status = "okay";
401};
402
403&iomuxc {
404	pinctrl_ecspi3: ecspi3grp {
405		fsl,pins = <
406			MX7D_PAD_I2C1_SCL__ECSPI3_MISO		0x2
407			MX7D_PAD_I2C1_SDA__ECSPI3_MOSI		0x2
408			MX7D_PAD_I2C2_SCL__ECSPI3_SCLK		0x2
409			MX7D_PAD_I2C2_SDA__GPIO4_IO11		0x14
410		>;
411	};
412
413	pinctrl_i2c1: i2c1grp {
414		fsl,pins = <
415			MX7D_PAD_UART1_TX_DATA__I2C1_SDA	0x4000007f
416			MX7D_PAD_UART1_RX_DATA__I2C1_SCL	0x4000007f
417		>;
418	};
419
420	pinctrl_i2c2: i2c2grp {
421		fsl,pins = <
422			MX7D_PAD_UART2_TX_DATA__I2C2_SDA	0x4000007f
423			MX7D_PAD_UART2_RX_DATA__I2C2_SCL	0x4000007f
424		>;
425	};
426
427	pinctrl_enet1: enet1grp {
428		fsl,pins = <
429			MX7D_PAD_SD2_CD_B__ENET1_MDIO			0x3
430			MX7D_PAD_SD2_WP__ENET1_MDC			0x3
431			MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC	0x1
432			MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0	0x1
433			MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1	0x1
434			MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2	0x1
435			MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3	0x1
436			MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL	0x1
437			MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC	0x1
438			MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0	0x1
439			MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1	0x1
440			MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2	0x1
441			MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3	0x1
442			MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL	0x1
443			MX7D_PAD_SD3_RESET_B__GPIO6_IO11		0x1  /* Ethernet reset */
444		>;
445	};
446
447	pinctrl_can1: can1frp {
448		fsl,pins = <
449			MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX	0x59
450			MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX	0x59
451		>;
452	};
453
454	pinctrl_can2: can2frp {
455		fsl,pins = <
456			MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX	0x59
457			MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX	0x59
458		>;
459	};
460
461	pinctrl_i2c4: i2c4grp {
462		fsl,pins = <
463			MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA		0x4000007f
464			MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL		0x4000007f
465		>;
466	};
467
468	pinctrl_lcdif: lcdifgrp {
469		fsl,pins = <
470			MX7D_PAD_LCD_DATA00__LCD_DATA0		0x79
471			MX7D_PAD_LCD_DATA01__LCD_DATA1		0x79
472			MX7D_PAD_LCD_DATA02__LCD_DATA2		0x79
473			MX7D_PAD_LCD_DATA03__LCD_DATA3		0x79
474			MX7D_PAD_LCD_DATA04__LCD_DATA4		0x79
475			MX7D_PAD_LCD_DATA05__LCD_DATA5		0x79
476			MX7D_PAD_LCD_DATA06__LCD_DATA6		0x79
477			MX7D_PAD_LCD_DATA07__LCD_DATA7		0x79
478			MX7D_PAD_LCD_DATA08__LCD_DATA8		0x79
479			MX7D_PAD_LCD_DATA09__LCD_DATA9		0x79
480			MX7D_PAD_LCD_DATA10__LCD_DATA10		0x79
481			MX7D_PAD_LCD_DATA11__LCD_DATA11		0x79
482			MX7D_PAD_LCD_DATA12__LCD_DATA12		0x79
483			MX7D_PAD_LCD_DATA13__LCD_DATA13		0x79
484			MX7D_PAD_LCD_DATA14__LCD_DATA14		0x79
485			MX7D_PAD_LCD_DATA15__LCD_DATA15		0x79
486			MX7D_PAD_LCD_DATA16__LCD_DATA16		0x79
487			MX7D_PAD_LCD_DATA17__LCD_DATA17		0x79
488			MX7D_PAD_LCD_DATA18__LCD_DATA18		0x79
489			MX7D_PAD_LCD_DATA19__LCD_DATA19		0x79
490			MX7D_PAD_LCD_DATA20__LCD_DATA20		0x79
491			MX7D_PAD_LCD_DATA21__LCD_DATA21		0x79
492			MX7D_PAD_LCD_DATA22__LCD_DATA22		0x79
493			MX7D_PAD_LCD_DATA23__LCD_DATA23		0x79
494			MX7D_PAD_LCD_CLK__LCD_CLK		0x79
495			MX7D_PAD_LCD_ENABLE__LCD_ENABLE		0x78
496			MX7D_PAD_LCD_VSYNC__LCD_VSYNC		0x78
497			MX7D_PAD_LCD_HSYNC__LCD_HSYNC		0x78
498			MX7D_PAD_LCD_RESET__GPIO3_IO4		0x14
499		>;
500	};
501
502	pinctrl_pwm1: pwm1 {
503		fsl,pins = <
504			MX7D_PAD_GPIO1_IO08__PWM1_OUT	0x7f
505		>;
506	};
507
508	pinctrl_pwm2: pwm2 {
509		fsl,pins = <
510			MX7D_PAD_GPIO1_IO09__PWM2_OUT	0x7f
511		>;
512	};
513
514	pinctrl_pwm3: pwm3 {
515		fsl,pins = <
516			MX7D_PAD_GPIO1_IO10__PWM3_OUT	0x7f
517		>;
518	};
519
520	pinctrl_pwm4: pwm4grp {
521		fsl,pins = <
522			MX7D_PAD_GPIO1_IO11__PWM4_OUT	0x7f
523		>;
524	};
525
526	pinctrl_reg_wlreg_on: regregongrp {
527		fsl,pins = <
528			MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16	0x59
529		>;
530	};
531
532	pinctrl_sai1: sai1grp {
533		fsl,pins = <
534			MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK	0x1f
535			MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC	0x1f
536			MX7D_PAD_ENET1_COL__SAI1_TX_DATA0	0x30
537			MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0	0x1f
538		>;
539	};
540
541	pinctrl_uart5: uart5grp {
542		fsl,pins = <
543			MX7D_PAD_I2C4_SDA__UART5_DCE_TX		0x79
544			MX7D_PAD_I2C4_SCL__UART5_DCE_RX		0x79
545		>;
546	};
547
548	pinctrl_uart6: uart6grp {
549		fsl,pins = <
550			MX7D_PAD_EPDC_DATA08__UART6_DCE_RX	0x79
551			MX7D_PAD_EPDC_DATA09__UART6_DCE_TX	0x79
552			MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS	0x79
553			MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS	0x79
554		>;
555	};
556
557	pinctrl_uart7: uart7grp {
558		fsl,pins = <
559			MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX	0x79
560			MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX	0x79
561			MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS	0x79
562			MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS	0x79
563		>;
564	};
565
566	pinctrl_usbotg1_pwr: usbotg_pwr {
567		fsl,pins = <
568			MX7D_PAD_UART3_TX_DATA__GPIO4_IO5	0x14
569		>;
570	};
571
572	pinctrl_usdhc1: usdhc1grp {
573		fsl,pins = <
574			MX7D_PAD_SD1_CMD__SD1_CMD		0x59
575			MX7D_PAD_SD1_CLK__SD1_CLK		0x19
576			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x59
577			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x59
578			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x59
579			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x59
580			MX7D_PAD_SD1_CD_B__GPIO5_IO0		0x15
581		>;
582	};
583
584	pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
585		fsl,pins = <
586			MX7D_PAD_SD1_CMD__SD1_CMD		0x5a
587			MX7D_PAD_SD1_CLK__SD1_CLK		0x1a
588			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5a
589			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5a
590			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5a
591			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5a
592			MX7D_PAD_SD1_CD_B__GPIO5_IO0		0x15
593		>;
594	};
595
596	pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
597		fsl,pins = <
598			MX7D_PAD_SD1_CMD__SD1_CMD		0x5b
599			MX7D_PAD_SD1_CLK__SD1_CLK		0x1b
600			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5b
601			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5b
602			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5b
603			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5b
604			MX7D_PAD_SD1_CD_B__GPIO5_IO0		0x15
605		>;
606	};
607
608	pinctrl_usdhc2: usdhc2grp {
609		fsl,pins = <
610			MX7D_PAD_SD2_CMD__SD2_CMD		0x59
611			MX7D_PAD_SD2_CLK__SD2_CLK		0x19
612			MX7D_PAD_SD2_DATA0__SD2_DATA0		0x59
613			MX7D_PAD_SD2_DATA1__SD2_DATA1		0x59
614			MX7D_PAD_SD2_DATA2__SD2_DATA2		0x59
615			MX7D_PAD_SD2_DATA3__SD2_DATA3		0x59
616		>;
617	};
618
619	pinctrl_usdhc3: usdhc3grp {
620		fsl,pins = <
621			MX7D_PAD_SD3_CMD__SD3_CMD		0x59
622			MX7D_PAD_SD3_CLK__SD3_CLK		0x19
623			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x59
624			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x59
625			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x59
626			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x59
627			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x59
628			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x59
629			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x59
630			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x59
631		>;
632	};
633
634	pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
635		fsl,pins = <
636			MX7D_PAD_SD3_CMD__SD3_CMD		0x5a
637			MX7D_PAD_SD3_CLK__SD3_CLK		0x1a
638			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x5a
639			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x5a
640			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x5a
641			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x5a
642			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x5a
643			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x5a
644			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x5a
645			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x5a
646		>;
647	};
648
649	pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
650		fsl,pins = <
651			MX7D_PAD_SD3_CMD__SD3_CMD		0x5b
652			MX7D_PAD_SD3_CLK__SD3_CLK		0x1b
653			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x5b
654			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x5b
655			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x5b
656			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x5b
657			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x5b
658			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x5b
659			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x5b
660			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x5b
661		>;
662	};
663};
664
665&iomuxc_lpsr {
666	pinctrl_wifi_clk: wificlkgrp {
667		fsl,pins = <
668			MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2	0x7d
669		>;
670	};
671
672	pinctrl_reg_lcdreg_on: reglcdongrp {
673	fsl,pins = <
674			MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6	0x59
675		>;
676	};
677
678	pinctrl_wdog: wdoggrp {
679		fsl,pins = <
680			MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B	0x74
681		>;
682	};
683};
684