1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Device tree file for ZII's RPU2 board
4 *
5 * RPU - Remote Peripheral Unit
6 *
7 * Copyright (C) 2019 Zodiac Inflight Innovations
8 */
9
10/dts-v1/;
11#include <dt-bindings/thermal/thermal.h>
12#include "imx7d.dtsi"
13
14/ {
15	model = "ZII RPU2 Board";
16	compatible = "zii,imx7d-rpu2", "fsl,imx7d";
17
18	chosen {
19		stdout-path = &uart2;
20	};
21
22	cs2000_ref: oscillator {
23		compatible = "fixed-clock";
24		#clock-cells = <0>;
25		clock-frequency = <24576000>;
26	};
27
28	cs2000_in_dummy: dummy-oscillator {
29		compatible = "fixed-clock";
30		#clock-cells = <0>;
31		clock-frequency = <0>;
32	};
33
34	gpio-leds {
35		compatible = "gpio-leds";
36		pinctrl-0 = <&pinctrl_leds_debug>;
37		pinctrl-names = "default";
38
39		led-debug {
40			label = "zii:green:debug1";
41			gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
42			linux,default-trigger = "heartbeat";
43		};
44	};
45
46	iio-hwmon {
47		compatible = "iio-hwmon";
48		io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>,
49			      <&adc2 1>;
50	};
51
52	reg_can1_stby: regulator-can1-stby {
53		compatible = "regulator-fixed";
54		pinctrl-names = "default";
55		pinctrl-0 = <&pinctrl_flexcan1_stby>;
56		regulator-name = "can1-3v3";
57		regulator-min-microvolt = <3300000>;
58		regulator-max-microvolt = <3300000>;
59		gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
60		enable-active-high;
61	};
62
63	reg_can2_stby: regulator-can2-stby {
64		compatible = "regulator-fixed";
65		pinctrl-names = "default";
66		pinctrl-0 = <&pinctrl_flexcan2_stby>;
67		regulator-name = "can2-3v3";
68		regulator-min-microvolt = <3300000>;
69		regulator-max-microvolt = <3300000>;
70		gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
71		enable-active-high;
72	};
73
74	reg_vref_1v8: regulator-vref-1v8 {
75		compatible = "regulator-fixed";
76		regulator-name = "vref-1v8";
77		regulator-min-microvolt = <1800000>;
78		regulator-max-microvolt = <1800000>;
79		regulator-always-on;
80	};
81
82	reg_3p3v: regulator-3p3v {
83		compatible = "regulator-fixed";
84		regulator-name = "GEN_3V3";
85		regulator-min-microvolt = <3300000>;
86		regulator-max-microvolt = <3300000>;
87		regulator-always-on;
88	};
89
90	reg_5p0v_main: regulator-5p0v-main {
91		compatible = "regulator-fixed";
92		regulator-name = "5V_MAIN";
93		regulator-min-microvolt = <5000000>;
94		regulator-max-microvolt = <5000000>;
95		regulator-always-on;
96	};
97
98	sound1 {
99		compatible = "simple-audio-card";
100		simple-audio-card,name = "Audio Output 1";
101		simple-audio-card,format = "i2s";
102		simple-audio-card,bitclock-master = <&sound1_codec>;
103		simple-audio-card,frame-master = <&sound1_codec>;
104		simple-audio-card,widgets =
105			"Headphone", "Headphone Jack";
106		simple-audio-card,routing =
107			"Headphone Jack", "HPLEFT",
108			"Headphone Jack", "HPRIGHT",
109			"LEFTIN", "HPL",
110			"RIGHTIN", "HPR";
111		simple-audio-card,aux-devs = <&hpa1>;
112
113		simple-audio-card,cpu {
114			sound-dai = <&sai1>;
115		};
116
117		sound1_codec: simple-audio-card,codec {
118			sound-dai = <&codec1>;
119			clocks = <&cs2000>;
120		};
121	};
122
123	sound2 {
124		compatible = "simple-audio-card";
125		simple-audio-card,name = "Audio Output 2";
126		simple-audio-card,format = "i2s";
127		simple-audio-card,bitclock-master = <&sound2_codec>;
128		simple-audio-card,frame-master = <&sound2_codec>;
129		simple-audio-card,widgets =
130			"Headphone", "Headphone Jack";
131		simple-audio-card,routing =
132			"Headphone Jack", "HPLEFT",
133			"Headphone Jack", "HPRIGHT",
134			"LEFTIN", "HPL",
135			"RIGHTIN", "HPR";
136		simple-audio-card,aux-devs = <&hpa2>;
137
138		simple-audio-card,cpu {
139			sound-dai = <&sai2>;
140		};
141
142		sound2_codec: simple-audio-card,codec {
143			sound-dai = <&codec2>;
144			clocks = <&cs2000>;
145		};
146	};
147
148	sound3 {
149		compatible = "simple-audio-card";
150		simple-audio-card,name = "Audio Output 3";
151		simple-audio-card,format = "i2s";
152		simple-audio-card,bitclock-master = <&sound3_codec>;
153		simple-audio-card,frame-master = <&sound3_codec>;
154		simple-audio-card,widgets =
155			"Headphone", "Headphone Jack";
156		simple-audio-card,routing =
157			"Headphone Jack", "HPLEFT",
158			"Headphone Jack", "HPRIGHT",
159			"LEFTIN", "HPL",
160			"RIGHTIN", "HPR";
161		simple-audio-card,aux-devs = <&hpa3>;
162
163		simple-audio-card,cpu {
164			sound-dai = <&sai3>;
165		};
166
167		sound3_codec: simple-audio-card,codec {
168			sound-dai = <&codec3>;
169			clocks = <&cs2000>;
170		};
171	};
172};
173
174&adc1 {
175	vref-supply = <&reg_vref_1v8>;
176	status = "okay";
177};
178
179&adc2 {
180	vref-supply = <&reg_vref_1v8>;
181	status = "okay";
182};
183
184&cpu0 {
185	cpu-supply = <&sw1a_reg>;
186};
187
188&clks {
189	assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
190	assigned-clock-rates = <884736000>;
191};
192
193&ecspi1 {
194	pinctrl-names = "default";
195	pinctrl-0 = <&pinctrl_ecspi1>;
196	cs-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
197	status = "okay";
198
199	flash@0 {
200		compatible = "jedec,spi-nor";
201		spi-max-frequency = <20000000>;
202		reg = <0>;
203		#address-cells = <1>;
204		#size-cells = <1>;
205	};
206};
207
208&fec1 {
209	pinctrl-names = "default";
210	pinctrl-0 = <&pinctrl_enet1>;
211	assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
212			  <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
213	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
214	assigned-clock-rates = <0>, <100000000>;
215	phy-mode = "rgmii";
216	status = "okay";
217
218	fixed-link {
219		speed = <1000>;
220		full-duplex;
221	};
222
223	mdio1: mdio {
224		#address-cells = <1>;
225		#size-cells = <0>;
226		status = "okay";
227
228		switch: switch@0 {
229			compatible = "marvell,mv88e6085";
230			pinctrl-names = "default";
231			pinctrl-0 = <&pinctrl_switch>;
232			reg = <0>;
233			eeprom-length = <512>;
234			interrupt-parent = <&gpio1>;
235			interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
236			interrupt-controller;
237			#interrupt-cells = <2>;
238
239			ports {
240				#address-cells = <1>;
241				#size-cells = <0>;
242
243				port@0 {
244					reg = <0>;
245					label = "eth_cu_1000_1";
246				};
247
248				port@1 {
249					reg = <1>;
250					label = "eth_cu_1000_2";
251				};
252
253				port@2 {
254					reg = <2>;
255					label = "pic";
256
257					fixed-link {
258						speed = <100>;
259						full-duplex;
260					};
261				};
262
263				port@5 {
264					reg = <5>;
265					label = "cpu";
266					ethernet = <&fec1>;
267					phy-mode = "rgmii-id";
268
269					fixed-link {
270						speed = <1000>;
271						full-duplex;
272					};
273				};
274
275				port@6 {
276					reg = <6>;
277					label = "gigabit_proc";
278					ethernet = <&fec2>;
279					phy-mode = "rgmii-id";
280
281					fixed-link {
282						speed = <1000>;
283						full-duplex;
284					};
285				};
286			};
287		};
288	};
289};
290
291&fec2 {
292	pinctrl-names = "default";
293	pinctrl-0 = <&pinctrl_enet2>;
294	assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
295			  <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
296	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
297	assigned-clock-rates = <0>, <100000000>;
298	phy-mode = "rgmii";
299	fsl,magic-packet;
300	status = "okay";
301
302	fixed-link {
303		speed = <1000>;
304		full-duplex;
305	};
306};
307
308&flexcan1 {
309	pinctrl-names = "default";
310	pinctrl-0 = <&pinctrl_flexcan1>;
311	xceiver-supply = <&reg_can1_stby>;
312	status = "okay";
313};
314
315&flexcan2 {
316	pinctrl-names = "default";
317	pinctrl-0 = <&pinctrl_flexcan2>;
318	xceiver-supply = <&reg_can2_stby>;
319	status = "okay";
320};
321
322&gpio1 {
323	pinctrl-names = "default";
324	pinctrl-0 = <&pinctrl_gpio1>;
325
326	gpio-line-names = "", "", "", "", "", "", "", "",
327			  "", "",
328			  "usb_1_en_b",
329			  "usb_2_en_b",
330			  "", "", "", "", "", "", "", "",
331			  "", "", "", "", "", "", "", "",
332			  "", "", "", "";
333};
334
335&gpio2 {
336	pinctrl-names = "default";
337	pinctrl-0 = <&pinctrl_gpio2>;
338
339	gpio-line-names = "12v_out_en_1",
340			  "12v_out_en_2",
341			  "12v_out_en_3",
342			  "28v_out_en_5",
343			  "28v_out_en_1",
344			  "28v_out_en_2",
345			  "28v_out_en_3",
346			  "28v_out_en_4",
347			  "", "",
348			  "usb_3_en_b",
349			  "usb_4_en_b",
350			  "", "", "", "", "", "", "", "",
351			  "", "", "", "", "", "", "", "",
352			  "", "", "", "";
353};
354
355&i2c1 {
356	clock-frequency = <100000>;
357	pinctrl-names = "default";
358	pinctrl-0 = <&pinctrl_i2c1>;
359	status = "okay";
360
361	pmic: pmic@8 {
362		compatible = "fsl,pfuze3000";
363		reg = <0x08>;
364
365		regulators {
366			sw1a_reg: sw1a {
367				regulator-min-microvolt = <700000>;
368				regulator-max-microvolt = <3300000>;
369				regulator-boot-on;
370				regulator-always-on;
371				regulator-ramp-delay = <6250>;
372			};
373
374			sw1c_reg: sw1b {
375				regulator-min-microvolt = <700000>;
376				regulator-max-microvolt = <1475000>;
377				regulator-boot-on;
378				regulator-always-on;
379				regulator-ramp-delay = <6250>;
380			};
381
382			sw2_reg: sw2 {
383				regulator-min-microvolt = <1500000>;
384				regulator-max-microvolt = <1850000>;
385				regulator-boot-on;
386				regulator-always-on;
387			};
388
389			sw3a_reg: sw3 {
390				regulator-min-microvolt = <900000>;
391				regulator-max-microvolt = <1650000>;
392				regulator-boot-on;
393				regulator-always-on;
394			};
395
396			swbst_reg: swbst {
397				regulator-min-microvolt = <5000000>;
398				regulator-max-microvolt = <5150000>;
399			};
400
401			snvs_reg: vsnvs {
402				regulator-min-microvolt = <1000000>;
403				regulator-max-microvolt = <3000000>;
404				regulator-boot-on;
405				regulator-always-on;
406			};
407
408			vref_reg: vrefddr {
409				regulator-boot-on;
410				regulator-always-on;
411			};
412
413			vgen1_reg: vldo1 {
414				regulator-min-microvolt = <1800000>;
415				regulator-max-microvolt = <3300000>;
416				regulator-always-on;
417			};
418
419			vgen2_reg: vldo2 {
420				regulator-min-microvolt = <800000>;
421				regulator-max-microvolt = <1550000>;
422				regulator-always-on;
423			};
424
425			vgen3_reg: vccsd {
426				regulator-min-microvolt = <2850000>;
427				regulator-max-microvolt = <3300000>;
428				regulator-always-on;
429			};
430
431			vgen4_reg: v33 {
432				regulator-min-microvolt = <2850000>;
433				regulator-max-microvolt = <3300000>;
434				regulator-always-on;
435			};
436
437			vgen5_reg: vldo3 {
438				regulator-min-microvolt = <1800000>;
439				regulator-max-microvolt = <3300000>;
440				regulator-always-on;
441			};
442
443			vgen6_reg: vldo4 {
444				regulator-min-microvolt = <1800000>;
445				regulator-max-microvolt = <3300000>;
446				regulator-always-on;
447			};
448		};
449	};
450
451	cs2000: clkgen@4e {
452		compatible = "cirrus,cs2000-cp";
453		reg = <0x4e>;
454		#clock-cells = <0>;
455		clock-names = "clk_in", "ref_clk";
456		clocks = <&cs2000_in_dummy>, <&cs2000_ref>;
457		assigned-clocks = <&cs2000>;
458		assigned-clock-rates = <24000000>;
459	};
460
461	eeprom@50 {
462		compatible = "atmel,24c04";
463		reg = <0x50>;
464	};
465
466	eeprom@52 {
467		compatible = "atmel,24c04";
468		reg = <0x52>;
469	};
470};
471
472&i2c2 {
473	clock-frequency = <100000>;
474	pinctrl-names = "default";
475	pinctrl-0 = <&pinctrl_i2c2>;
476	status = "okay";
477
478	codec2: codec@18 {
479		compatible = "ti,tlv320dac3100";
480		pinctrl-names = "default";
481		pinctrl-0 = <&pinctrl_codec2>;
482		reg = <0x18>;
483		#sound-dai-cells = <0>;
484		HPVDD-supply = <&reg_3p3v>;
485		SPRVDD-supply = <&reg_3p3v>;
486		SPLVDD-supply = <&reg_3p3v>;
487		AVDD-supply = <&reg_3p3v>;
488		IOVDD-supply = <&reg_3p3v>;
489		DVDD-supply = <&vgen4_reg>;
490		gpio-reset = <&gpio1 6 GPIO_ACTIVE_LOW>;
491	};
492
493	hpa2: amp@60 {
494		compatible = "ti,tpa6130a2";
495		pinctrl-names = "default";
496		pinctrl-0 = <&pinctrl_tpa2>;
497		reg = <0x60>;
498		power-gpio = <&gpio3 27 GPIO_ACTIVE_HIGH>;
499		Vdd-supply = <&reg_5p0v_main>;
500	};
501};
502
503&i2c3 {
504	clock-frequency = <100000>;
505	pinctrl-names = "default";
506	pinctrl-0 = <&pinctrl_i2c3>;
507	status = "okay";
508
509	codec3: codec@18 {
510		compatible = "ti,tlv320dac3100";
511		pinctrl-names = "default";
512		pinctrl-0 = <&pinctrl_codec3>;
513		reg = <0x18>;
514		#sound-dai-cells = <0>;
515		HPVDD-supply = <&reg_3p3v>;
516		SPRVDD-supply = <&reg_3p3v>;
517		SPLVDD-supply = <&reg_3p3v>;
518		AVDD-supply = <&reg_3p3v>;
519		IOVDD-supply = <&reg_3p3v>;
520		DVDD-supply = <&vgen4_reg>;
521		gpio-reset = <&gpio1 7 GPIO_ACTIVE_LOW>;
522	};
523
524	hpa3: amp@60 {
525		compatible = "ti,tpa6130a2";
526		pinctrl-names = "default";
527		pinctrl-0 = <&pinctrl_tpa3>;
528		reg = <0x60>;
529		power-gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>;
530		Vdd-supply = <&reg_5p0v_main>;
531	};
532};
533
534&i2c4 {
535	clock-frequency = <100000>;
536	pinctrl-names = "default";
537	pinctrl-0 = <&pinctrl_i2c4>;
538	status = "okay";
539
540	codec1: codec@18 {
541		compatible = "ti,tlv320dac3100";
542		pinctrl-names = "default";
543		pinctrl-0 = <&pinctrl_codec1>;
544		reg = <0x18>;
545		#sound-dai-cells = <0>;
546		HPVDD-supply = <&reg_3p3v>;
547		SPRVDD-supply = <&reg_3p3v>;
548		SPLVDD-supply = <&reg_3p3v>;
549		AVDD-supply = <&reg_3p3v>;
550		IOVDD-supply = <&reg_3p3v>;
551		DVDD-supply = <&vgen4_reg>;
552		gpio-reset = <&gpio1 5 GPIO_ACTIVE_LOW>;
553	};
554
555	hpa1: amp@60 {
556		compatible = "ti,tpa6130a2";
557		pinctrl-names = "default";
558		pinctrl-0 = <&pinctrl_tpa1>;
559		reg = <0x60>;
560		power-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>;
561		Vdd-supply = <&reg_5p0v_main>;
562	};
563};
564
565&sai1 {
566	pinctrl-names = "default";
567	pinctrl-0 = <&pinctrl_sai1>;
568	assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
569			  <&clks IMX7D_SAI1_ROOT_CLK>;
570	assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
571	assigned-clock-rates = <0>, <36864000>;
572	status = "okay";
573};
574
575&sai2 {
576	pinctrl-names = "default";
577	pinctrl-0 = <&pinctrl_sai2>;
578	assigned-clocks = <&clks IMX7D_SAI2_ROOT_SRC>,
579			  <&clks IMX7D_SAI2_ROOT_CLK>;
580	assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
581	assigned-clock-rates = <0>, <36864000>;
582	status = "okay";
583};
584
585&sai3 {
586	pinctrl-names = "default";
587	pinctrl-0 = <&pinctrl_sai3>;
588	assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>,
589			  <&clks IMX7D_SAI3_ROOT_CLK>;
590	assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
591	assigned-clock-rates = <0>, <36864000>;
592	status = "okay";
593};
594
595&uart2 {
596	pinctrl-names = "default";
597	pinctrl-0 = <&pinctrl_uart2>;
598	assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
599	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
600	status = "okay";
601};
602
603&uart4 {
604	pinctrl-names = "default";
605	pinctrl-0 = <&pinctrl_uart4>;
606	assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>;
607	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
608	status = "okay";
609
610	mcu {
611		compatible = "zii,rave-sp-rdu2";
612		current-speed = <1000000>;
613		#address-cells = <1>;
614		#size-cells = <1>;
615
616		watchdog {
617			compatible = "zii,rave-sp-watchdog";
618		};
619
620		eeprom@a3 {
621			compatible = "zii,rave-sp-eeprom";
622			reg = <0xa3 0x4000>;
623			#address-cells = <1>;
624			#size-cells = <1>;
625			zii,eeprom-name = "main-eeprom";
626		};
627	};
628};
629
630&usbotg1 {
631	dr_mode = "host";
632	disable-over-current;
633	status = "okay";
634};
635
636&usbotg2 {
637	dr_mode = "host";
638	disable-over-current;
639	status = "okay";
640};
641
642&usdhc1 {
643	pinctrl-names = "default";
644	pinctrl-0 = <&pinctrl_usdhc1>;
645	bus-width = <4>;
646	no-1-8-v;
647	no-sdio;
648	keep-power-in-suspend;
649	status = "okay";
650};
651
652&usdhc3 {
653	pinctrl-names = "default";
654	pinctrl-0 = <&pinctrl_usdhc3>;
655	bus-width = <8>;
656	no-1-8-v;
657	non-removable;
658	no-sdio;
659	no-sd;
660	keep-power-in-suspend;
661	status = "okay";
662};
663
664&wdog1 {
665	status = "disabled";
666};
667
668&snvs_rtc {
669	status = "disabled";
670};
671
672&iomuxc {
673	pinctrl_ecspi1: ecspi1grp {
674		fsl,pins = <
675			MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK	0x2
676			MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI	0x2
677			MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO	0x2
678			MX7D_PAD_ECSPI1_SS0__GPIO4_IO19         0x59
679		>;
680	};
681
682	pinctrl_enet1: enet1grp {
683		fsl,pins = <
684			MX7D_PAD_SD2_CD_B__ENET1_MDIO				0x3
685			MX7D_PAD_SD2_WP__ENET1_MDC				0x3
686			MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC		0x1
687			MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0		0x1
688			MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1		0x1
689			MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2		0x1
690			MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3		0x1
691			MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL		0x1
692			MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC		0x1
693			MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0		0x1
694			MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1		0x1
695			MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2		0x1
696			MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3		0x1
697			MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL		0x1
698		>;
699	};
700
701	pinctrl_enet2: enet2grp {
702		fsl,pins = <
703			MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC			0x1
704			MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0			0x1
705			MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1			0x1
706			MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2			0x1
707			MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3			0x1
708			MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL			0x1
709			MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC			0x1
710			MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0			0x1
711			MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1			0x1
712			MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2			0x1
713			MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3			0x1
714			MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL			0x1
715			MX7D_PAD_UART1_TX_DATA__ENET2_1588_EVENT0_OUT		0x1
716		>;
717	};
718
719	pinctrl_flexcan1: flexcan1grp {
720		fsl,pins = <
721			MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX	0x59
722			MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX	0x59
723		>;
724	};
725
726	pinctrl_flexcan1_stby: flexcan1stbygrp {
727		fsl,pins = <
728			MX7D_PAD_GPIO1_IO08__GPIO1_IO8		0x59
729		>;
730	};
731
732	pinctrl_flexcan2: flexcan2grp {
733		fsl,pins = <
734			MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX	0x59
735			MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX	0x59
736		>;
737	};
738
739	pinctrl_flexcan2_stby: flexcan2stbygrp {
740		fsl,pins = <
741			MX7D_PAD_GPIO1_IO09__GPIO1_IO9		0x59
742		>;
743	};
744
745	pinctrl_gpio1: gpio1grp {
746		fsl,pins = <
747			MX7D_PAD_GPIO1_IO10__GPIO1_IO10		0x00
748			MX7D_PAD_GPIO1_IO11__GPIO1_IO11		0x00
749		>;
750	};
751
752	pinctrl_gpio2: gpio2grp {
753		fsl,pins = <
754			MX7D_PAD_EPDC_DATA00__GPIO2_IO0		0x00
755			MX7D_PAD_EPDC_DATA01__GPIO2_IO1		0x00
756			MX7D_PAD_EPDC_DATA02__GPIO2_IO2		0x00
757			MX7D_PAD_EPDC_DATA03__GPIO2_IO3		0x03
758			MX7D_PAD_EPDC_DATA04__GPIO2_IO4		0x03
759			MX7D_PAD_EPDC_DATA05__GPIO2_IO5		0x03
760			MX7D_PAD_EPDC_DATA06__GPIO2_IO6		0x03
761			MX7D_PAD_EPDC_DATA07__GPIO2_IO7		0x03
762			MX7D_PAD_EPDC_DATA10__GPIO2_IO10	0x00
763			MX7D_PAD_EPDC_DATA11__GPIO2_IO11	0x00
764		>;
765	};
766
767	pinctrl_i2c1: i2c1grp {
768		fsl,pins = <
769			MX7D_PAD_I2C1_SDA__I2C1_SDA		0x4000007f
770			MX7D_PAD_I2C1_SCL__I2C1_SCL		0x4000007f
771		>;
772	};
773
774	pinctrl_i2c2: i2c2grp {
775		fsl,pins = <
776			MX7D_PAD_I2C2_SDA__I2C2_SDA		0x4000007f
777			MX7D_PAD_I2C2_SCL__I2C2_SCL		0x4000007f
778		>;
779	};
780
781	pinctrl_i2c3: i2c3grp {
782		fsl,pins = <
783			MX7D_PAD_I2C3_SDA__I2C3_SDA		0x4000007f
784			MX7D_PAD_I2C3_SCL__I2C3_SCL		0x4000007f
785		>;
786	};
787
788	pinctrl_i2c3_gpio: i2c3gpiogrp {
789		fsl,pins = <
790			MX7D_PAD_I2C3_SDA__GPIO4_IO13		0x4000007f
791			MX7D_PAD_I2C3_SCL__GPIO4_IO12		0x4000007f
792		>;
793	};
794
795	pinctrl_i2c4: i2c4grp {
796		fsl,pins = <
797			MX7D_PAD_I2C4_SDA__I2C4_SDA		0x4000007f
798			MX7D_PAD_I2C4_SCL__I2C4_SCL		0x4000007f
799		>;
800	};
801
802	pinctrl_i2c4_gpio: i2c4gpiogrp {
803		fsl,pins = <
804			MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17	0x4000007f
805			MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16	0x4000007f
806		>;
807	};
808
809	pinctrl_leds_debug: debuggrp {
810		fsl,pins = <
811			MX7D_PAD_EPDC_DATA08__GPIO2_IO8		0x59
812		>;
813	};
814
815	pinctrl_sai1: sai1grp {
816		fsl,pins = <
817			MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK	0x1f
818			MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC	0x1f
819			MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0	0x30
820		>;
821	};
822
823	pinctrl_sai2: sai2grp {
824		fsl,pins = <
825			MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK	0x1f
826			MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC	0x1f
827			MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0	0x30
828		>;
829	};
830
831	pinctrl_sai3: sai3grp {
832		fsl,pins = <
833			MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK	0x1f
834			MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC	0x1f
835			MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0	0x30
836		>;
837	};
838
839	pinctrl_tpa1: tpa6130-1grp {
840		fsl,pins = <
841			MX7D_PAD_LCD_DATA21__GPIO3_IO26		0x40000038
842		>;
843	};
844
845	pinctrl_tpa2: tpa6130-2grp {
846		fsl,pins = <
847			MX7D_PAD_LCD_DATA22__GPIO3_IO27		0x40000038
848		>;
849	};
850
851	pinctrl_tpa3: tpa6130-3grp {
852		fsl,pins = <
853			MX7D_PAD_LCD_DATA23__GPIO3_IO28		0x40000038
854		>;
855	};
856
857	pinctrl_uart2: uart2grp {
858		fsl,pins = <
859			MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX	0x79
860			MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX	0x79
861		>;
862	};
863
864	pinctrl_uart4: uart4grp {
865		fsl,pins = <
866			MX7D_PAD_SD2_DATA0__UART4_DCE_RX	0x79
867			MX7D_PAD_SD2_DATA1__UART4_DCE_TX	0x79
868		>;
869	};
870
871	pinctrl_usdhc1: usdhc1grp {
872		fsl,pins = <
873			MX7D_PAD_SD1_CMD__SD1_CMD		0x59
874			MX7D_PAD_SD1_CLK__SD1_CLK		0x19
875			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x59
876			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x59
877			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x59
878			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x59
879		>;
880	};
881
882	pinctrl_usdhc3: usdhc3grp {
883		fsl,pins = <
884			MX7D_PAD_SD3_CMD__SD3_CMD		0x59
885			MX7D_PAD_SD3_CLK__SD3_CLK		0x19
886			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x59
887			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x59
888			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x59
889			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x59
890			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x59
891			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x59
892			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x59
893			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x59
894			MX7D_PAD_SD3_RESET_B__SD3_RESET_B	0x59
895		>;
896	};
897};
898
899&iomuxc_lpsr {
900	pinctrl_codec1: dac1grp {
901		fsl,pins = <
902			MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5	0x40000038
903		>;
904	};
905
906	pinctrl_codec2: dac2grp {
907		fsl,pins = <
908			MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6	0x40000038
909		>;
910	};
911
912	pinctrl_codec3: dac3grp {
913		fsl,pins = <
914			MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7	0x40000038
915		>;
916	};
917
918	pinctrl_switch: switchgrp {
919		fsl,pins = <
920			MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2	0x08
921		>;
922	};
923};
924