1*f126890aSEmmanuel Vadot// SPDX-License-Identifier: GPL-2.0+ 2*f126890aSEmmanuel Vadot/* 3*f126890aSEmmanuel Vadot * NXP LPC32xx SoC 4*f126890aSEmmanuel Vadot * 5*f126890aSEmmanuel Vadot * Copyright (C) 2015-2019 Vladimir Zapolskiy <vz@mleia.com> 6*f126890aSEmmanuel Vadot * Copyright 2012 Roland Stigge <stigge@antcom.de> 7*f126890aSEmmanuel Vadot */ 8*f126890aSEmmanuel Vadot 9*f126890aSEmmanuel Vadot#include <dt-bindings/clock/lpc32xx-clock.h> 10*f126890aSEmmanuel Vadot#include <dt-bindings/interrupt-controller/irq.h> 11*f126890aSEmmanuel Vadot 12*f126890aSEmmanuel Vadot/ { 13*f126890aSEmmanuel Vadot #address-cells = <1>; 14*f126890aSEmmanuel Vadot #size-cells = <1>; 15*f126890aSEmmanuel Vadot compatible = "nxp,lpc3220"; 16*f126890aSEmmanuel Vadot interrupt-parent = <&mic>; 17*f126890aSEmmanuel Vadot 18*f126890aSEmmanuel Vadot cpus { 19*f126890aSEmmanuel Vadot #address-cells = <1>; 20*f126890aSEmmanuel Vadot #size-cells = <0>; 21*f126890aSEmmanuel Vadot 22*f126890aSEmmanuel Vadot cpu@0 { 23*f126890aSEmmanuel Vadot compatible = "arm,arm926ej-s"; 24*f126890aSEmmanuel Vadot device_type = "cpu"; 25*f126890aSEmmanuel Vadot reg = <0x0>; 26*f126890aSEmmanuel Vadot }; 27*f126890aSEmmanuel Vadot }; 28*f126890aSEmmanuel Vadot 29*f126890aSEmmanuel Vadot clocks { 30*f126890aSEmmanuel Vadot xtal_32k: xtal_32k { 31*f126890aSEmmanuel Vadot compatible = "fixed-clock"; 32*f126890aSEmmanuel Vadot #clock-cells = <0>; 33*f126890aSEmmanuel Vadot clock-frequency = <32768>; 34*f126890aSEmmanuel Vadot clock-output-names = "xtal_32k"; 35*f126890aSEmmanuel Vadot }; 36*f126890aSEmmanuel Vadot 37*f126890aSEmmanuel Vadot xtal: xtal { 38*f126890aSEmmanuel Vadot compatible = "fixed-clock"; 39*f126890aSEmmanuel Vadot #clock-cells = <0>; 40*f126890aSEmmanuel Vadot clock-frequency = <13000000>; 41*f126890aSEmmanuel Vadot clock-output-names = "xtal"; 42*f126890aSEmmanuel Vadot }; 43*f126890aSEmmanuel Vadot }; 44*f126890aSEmmanuel Vadot 45*f126890aSEmmanuel Vadot ahb { 46*f126890aSEmmanuel Vadot #address-cells = <1>; 47*f126890aSEmmanuel Vadot #size-cells = <1>; 48*f126890aSEmmanuel Vadot compatible = "simple-bus"; 49*f126890aSEmmanuel Vadot ranges = <0x00000000 0x00000000 0x10000000>, 50*f126890aSEmmanuel Vadot <0x20000000 0x20000000 0x30000000>, 51*f126890aSEmmanuel Vadot <0xe0000000 0xe0000000 0x04000000>; 52*f126890aSEmmanuel Vadot 53*f126890aSEmmanuel Vadot iram: sram@8000000 { 54*f126890aSEmmanuel Vadot compatible = "mmio-sram"; 55*f126890aSEmmanuel Vadot reg = <0x08000000 0x20000>; 56*f126890aSEmmanuel Vadot 57*f126890aSEmmanuel Vadot #address-cells = <1>; 58*f126890aSEmmanuel Vadot #size-cells = <1>; 59*f126890aSEmmanuel Vadot ranges = <0x00000000 0x08000000 0x20000>; 60*f126890aSEmmanuel Vadot }; 61*f126890aSEmmanuel Vadot 62*f126890aSEmmanuel Vadot /* 63*f126890aSEmmanuel Vadot * Enable either SLC or MLC 64*f126890aSEmmanuel Vadot */ 65*f126890aSEmmanuel Vadot slc: flash@20020000 { 66*f126890aSEmmanuel Vadot compatible = "nxp,lpc3220-slc"; 67*f126890aSEmmanuel Vadot reg = <0x20020000 0x1000>; 68*f126890aSEmmanuel Vadot clocks = <&clk LPC32XX_CLK_SLC>; 69*f126890aSEmmanuel Vadot status = "disabled"; 70*f126890aSEmmanuel Vadot }; 71*f126890aSEmmanuel Vadot 72*f126890aSEmmanuel Vadot mlc: flash@200a8000 { 73*f126890aSEmmanuel Vadot compatible = "nxp,lpc3220-mlc"; 74*f126890aSEmmanuel Vadot reg = <0x200a8000 0x11000>; 75*f126890aSEmmanuel Vadot interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; 76*f126890aSEmmanuel Vadot clocks = <&clk LPC32XX_CLK_MLC>; 77*f126890aSEmmanuel Vadot status = "disabled"; 78*f126890aSEmmanuel Vadot }; 79*f126890aSEmmanuel Vadot 80*f126890aSEmmanuel Vadot dma: dma@31000000 { 81*f126890aSEmmanuel Vadot compatible = "arm,pl080", "arm,primecell"; 82*f126890aSEmmanuel Vadot reg = <0x31000000 0x1000>; 83*f126890aSEmmanuel Vadot interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; 84*f126890aSEmmanuel Vadot clocks = <&clk LPC32XX_CLK_DMA>; 85*f126890aSEmmanuel Vadot clock-names = "apb_pclk"; 86*f126890aSEmmanuel Vadot }; 87*f126890aSEmmanuel Vadot 88*f126890aSEmmanuel Vadot usb { 89*f126890aSEmmanuel Vadot #address-cells = <1>; 90*f126890aSEmmanuel Vadot #size-cells = <1>; 91*f126890aSEmmanuel Vadot compatible = "simple-bus"; 92*f126890aSEmmanuel Vadot ranges = <0x0 0x31020000 0x00001000>; 93*f126890aSEmmanuel Vadot 94*f126890aSEmmanuel Vadot /* 95*f126890aSEmmanuel Vadot * Enable either ohci or usbd (gadget)! 96*f126890aSEmmanuel Vadot */ 97*f126890aSEmmanuel Vadot ohci: ohci@0 { 98*f126890aSEmmanuel Vadot compatible = "nxp,ohci-nxp", "usb-ohci"; 99*f126890aSEmmanuel Vadot reg = <0x0 0x300>; 100*f126890aSEmmanuel Vadot interrupt-parent = <&sic1>; 101*f126890aSEmmanuel Vadot interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; 102*f126890aSEmmanuel Vadot clocks = <&usbclk LPC32XX_USB_CLK_HOST>; 103*f126890aSEmmanuel Vadot status = "disabled"; 104*f126890aSEmmanuel Vadot }; 105*f126890aSEmmanuel Vadot 106*f126890aSEmmanuel Vadot usbd: usbd@0 { 107*f126890aSEmmanuel Vadot compatible = "nxp,lpc3220-udc"; 108*f126890aSEmmanuel Vadot reg = <0x0 0x300>; 109*f126890aSEmmanuel Vadot interrupt-parent = <&sic1>; 110*f126890aSEmmanuel Vadot interrupts = <29 IRQ_TYPE_LEVEL_HIGH>, 111*f126890aSEmmanuel Vadot <30 IRQ_TYPE_LEVEL_HIGH>, 112*f126890aSEmmanuel Vadot <28 IRQ_TYPE_LEVEL_HIGH>, 113*f126890aSEmmanuel Vadot <26 IRQ_TYPE_LEVEL_LOW>; 114*f126890aSEmmanuel Vadot clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>; 115*f126890aSEmmanuel Vadot status = "disabled"; 116*f126890aSEmmanuel Vadot }; 117*f126890aSEmmanuel Vadot 118*f126890aSEmmanuel Vadot i2cusb: i2c@300 { 119*f126890aSEmmanuel Vadot compatible = "nxp,pnx-i2c"; 120*f126890aSEmmanuel Vadot reg = <0x300 0x100>; 121*f126890aSEmmanuel Vadot interrupt-parent = <&sic1>; 122*f126890aSEmmanuel Vadot interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; 123*f126890aSEmmanuel Vadot clocks = <&usbclk LPC32XX_USB_CLK_I2C>; 124*f126890aSEmmanuel Vadot #address-cells = <1>; 125*f126890aSEmmanuel Vadot #size-cells = <0>; 126*f126890aSEmmanuel Vadot }; 127*f126890aSEmmanuel Vadot 128*f126890aSEmmanuel Vadot usbclk: clock-controller@f00 { 129*f126890aSEmmanuel Vadot compatible = "nxp,lpc3220-usb-clk"; 130*f126890aSEmmanuel Vadot reg = <0xf00 0x100>; 131*f126890aSEmmanuel Vadot #clock-cells = <1>; 132*f126890aSEmmanuel Vadot }; 133*f126890aSEmmanuel Vadot }; 134*f126890aSEmmanuel Vadot 135*f126890aSEmmanuel Vadot clcd: clcd@31040000 { 136*f126890aSEmmanuel Vadot compatible = "arm,pl111", "arm,primecell"; 137*f126890aSEmmanuel Vadot reg = <0x31040000 0x1000>; 138*f126890aSEmmanuel Vadot interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; 139*f126890aSEmmanuel Vadot clocks = <&clk LPC32XX_CLK_LCD>, <&clk LPC32XX_CLK_LCD>; 140*f126890aSEmmanuel Vadot clock-names = "clcdclk", "apb_pclk"; 141*f126890aSEmmanuel Vadot status = "disabled"; 142*f126890aSEmmanuel Vadot }; 143*f126890aSEmmanuel Vadot 144*f126890aSEmmanuel Vadot mac: ethernet@31060000 { 145*f126890aSEmmanuel Vadot compatible = "nxp,lpc-eth"; 146*f126890aSEmmanuel Vadot reg = <0x31060000 0x1000>; 147*f126890aSEmmanuel Vadot interrupts = <29 IRQ_TYPE_LEVEL_HIGH>; 148*f126890aSEmmanuel Vadot clocks = <&clk LPC32XX_CLK_MAC>; 149*f126890aSEmmanuel Vadot status = "disabled"; 150*f126890aSEmmanuel Vadot }; 151*f126890aSEmmanuel Vadot 152*f126890aSEmmanuel Vadot emc: memory-controller@31080000 { 153*f126890aSEmmanuel Vadot compatible = "arm,pl175", "arm,primecell"; 154*f126890aSEmmanuel Vadot reg = <0x31080000 0x1000>; 155*f126890aSEmmanuel Vadot clocks = <&clk LPC32XX_CLK_DDRAM>, <&clk LPC32XX_CLK_DDRAM>; 156*f126890aSEmmanuel Vadot clock-names = "mpmcclk", "apb_pclk"; 157*f126890aSEmmanuel Vadot #address-cells = <1>; 158*f126890aSEmmanuel Vadot #size-cells = <1>; 159*f126890aSEmmanuel Vadot 160*f126890aSEmmanuel Vadot ranges = <0 0xe0000000 0x01000000>, 161*f126890aSEmmanuel Vadot <1 0xe1000000 0x01000000>, 162*f126890aSEmmanuel Vadot <2 0xe2000000 0x01000000>, 163*f126890aSEmmanuel Vadot <3 0xe3000000 0x01000000>; 164*f126890aSEmmanuel Vadot status = "disabled"; 165*f126890aSEmmanuel Vadot }; 166*f126890aSEmmanuel Vadot 167*f126890aSEmmanuel Vadot apb { 168*f126890aSEmmanuel Vadot #address-cells = <1>; 169*f126890aSEmmanuel Vadot #size-cells = <1>; 170*f126890aSEmmanuel Vadot compatible = "simple-bus"; 171*f126890aSEmmanuel Vadot ranges = <0x20000000 0x20000000 0x30000000>; 172*f126890aSEmmanuel Vadot 173*f126890aSEmmanuel Vadot /* 174*f126890aSEmmanuel Vadot * ssp0 and spi1 are shared pins; 175*f126890aSEmmanuel Vadot * enable one in your board dts, as needed. 176*f126890aSEmmanuel Vadot */ 177*f126890aSEmmanuel Vadot ssp0: spi@20084000 { 178*f126890aSEmmanuel Vadot compatible = "arm,pl022", "arm,primecell"; 179*f126890aSEmmanuel Vadot reg = <0x20084000 0x1000>; 180*f126890aSEmmanuel Vadot interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; 181*f126890aSEmmanuel Vadot clocks = <&clk LPC32XX_CLK_SSP0>; 182*f126890aSEmmanuel Vadot clock-names = "apb_pclk"; 183*f126890aSEmmanuel Vadot #address-cells = <1>; 184*f126890aSEmmanuel Vadot #size-cells = <0>; 185*f126890aSEmmanuel Vadot status = "disabled"; 186*f126890aSEmmanuel Vadot }; 187*f126890aSEmmanuel Vadot 188*f126890aSEmmanuel Vadot spi1: spi@20088000 { 189*f126890aSEmmanuel Vadot compatible = "nxp,lpc3220-spi"; 190*f126890aSEmmanuel Vadot reg = <0x20088000 0x1000>; 191*f126890aSEmmanuel Vadot clocks = <&clk LPC32XX_CLK_SPI1>; 192*f126890aSEmmanuel Vadot #address-cells = <1>; 193*f126890aSEmmanuel Vadot #size-cells = <0>; 194*f126890aSEmmanuel Vadot status = "disabled"; 195*f126890aSEmmanuel Vadot }; 196*f126890aSEmmanuel Vadot 197*f126890aSEmmanuel Vadot /* 198*f126890aSEmmanuel Vadot * ssp1 and spi2 are shared pins; 199*f126890aSEmmanuel Vadot * enable one in your board dts, as needed. 200*f126890aSEmmanuel Vadot */ 201*f126890aSEmmanuel Vadot ssp1: spi@2008c000 { 202*f126890aSEmmanuel Vadot compatible = "arm,pl022", "arm,primecell"; 203*f126890aSEmmanuel Vadot reg = <0x2008c000 0x1000>; 204*f126890aSEmmanuel Vadot interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; 205*f126890aSEmmanuel Vadot clocks = <&clk LPC32XX_CLK_SSP1>; 206*f126890aSEmmanuel Vadot clock-names = "apb_pclk"; 207*f126890aSEmmanuel Vadot #address-cells = <1>; 208*f126890aSEmmanuel Vadot #size-cells = <0>; 209*f126890aSEmmanuel Vadot status = "disabled"; 210*f126890aSEmmanuel Vadot }; 211*f126890aSEmmanuel Vadot 212*f126890aSEmmanuel Vadot spi2: spi@20090000 { 213*f126890aSEmmanuel Vadot compatible = "nxp,lpc3220-spi"; 214*f126890aSEmmanuel Vadot reg = <0x20090000 0x1000>; 215*f126890aSEmmanuel Vadot clocks = <&clk LPC32XX_CLK_SPI2>; 216*f126890aSEmmanuel Vadot #address-cells = <1>; 217*f126890aSEmmanuel Vadot #size-cells = <0>; 218*f126890aSEmmanuel Vadot status = "disabled"; 219*f126890aSEmmanuel Vadot }; 220*f126890aSEmmanuel Vadot 221*f126890aSEmmanuel Vadot i2s0: i2s@20094000 { 222*f126890aSEmmanuel Vadot compatible = "nxp,lpc3220-i2s"; 223*f126890aSEmmanuel Vadot reg = <0x20094000 0x1000>; 224*f126890aSEmmanuel Vadot status = "disabled"; 225*f126890aSEmmanuel Vadot }; 226*f126890aSEmmanuel Vadot 227*f126890aSEmmanuel Vadot sd: sd@20098000 { 228*f126890aSEmmanuel Vadot compatible = "arm,pl18x", "arm,primecell"; 229*f126890aSEmmanuel Vadot reg = <0x20098000 0x1000>; 230*f126890aSEmmanuel Vadot interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, 231*f126890aSEmmanuel Vadot <13 IRQ_TYPE_LEVEL_HIGH>; 232*f126890aSEmmanuel Vadot clocks = <&clk LPC32XX_CLK_SD>; 233*f126890aSEmmanuel Vadot clock-names = "apb_pclk"; 234*f126890aSEmmanuel Vadot status = "disabled"; 235*f126890aSEmmanuel Vadot }; 236*f126890aSEmmanuel Vadot 237*f126890aSEmmanuel Vadot i2s1: i2s@2009c000 { 238*f126890aSEmmanuel Vadot compatible = "nxp,lpc3220-i2s"; 239*f126890aSEmmanuel Vadot reg = <0x2009c000 0x1000>; 240*f126890aSEmmanuel Vadot status = "disabled"; 241*f126890aSEmmanuel Vadot }; 242*f126890aSEmmanuel Vadot 243*f126890aSEmmanuel Vadot /* UART5 first since it is the default console, ttyS0 */ 244*f126890aSEmmanuel Vadot uart5: serial@40090000 { 245*f126890aSEmmanuel Vadot /* actually, ns16550a w/ 64 byte fifos! */ 246*f126890aSEmmanuel Vadot compatible = "nxp,lpc3220-uart"; 247*f126890aSEmmanuel Vadot reg = <0x40090000 0x1000>; 248*f126890aSEmmanuel Vadot interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; 249*f126890aSEmmanuel Vadot reg-shift = <2>; 250*f126890aSEmmanuel Vadot clocks = <&clk LPC32XX_CLK_UART5>; 251*f126890aSEmmanuel Vadot status = "disabled"; 252*f126890aSEmmanuel Vadot }; 253*f126890aSEmmanuel Vadot 254*f126890aSEmmanuel Vadot uart3: serial@40080000 { 255*f126890aSEmmanuel Vadot compatible = "nxp,lpc3220-uart"; 256*f126890aSEmmanuel Vadot reg = <0x40080000 0x1000>; 257*f126890aSEmmanuel Vadot interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; 258*f126890aSEmmanuel Vadot reg-shift = <2>; 259*f126890aSEmmanuel Vadot clocks = <&clk LPC32XX_CLK_UART3>; 260*f126890aSEmmanuel Vadot status = "disabled"; 261*f126890aSEmmanuel Vadot }; 262*f126890aSEmmanuel Vadot 263*f126890aSEmmanuel Vadot uart4: serial@40088000 { 264*f126890aSEmmanuel Vadot compatible = "nxp,lpc3220-uart"; 265*f126890aSEmmanuel Vadot reg = <0x40088000 0x1000>; 266*f126890aSEmmanuel Vadot interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 267*f126890aSEmmanuel Vadot reg-shift = <2>; 268*f126890aSEmmanuel Vadot clocks = <&clk LPC32XX_CLK_UART4>; 269*f126890aSEmmanuel Vadot status = "disabled"; 270*f126890aSEmmanuel Vadot }; 271*f126890aSEmmanuel Vadot 272*f126890aSEmmanuel Vadot uart6: serial@40098000 { 273*f126890aSEmmanuel Vadot compatible = "nxp,lpc3220-uart"; 274*f126890aSEmmanuel Vadot reg = <0x40098000 0x1000>; 275*f126890aSEmmanuel Vadot interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; 276*f126890aSEmmanuel Vadot reg-shift = <2>; 277*f126890aSEmmanuel Vadot clocks = <&clk LPC32XX_CLK_UART6>; 278*f126890aSEmmanuel Vadot status = "disabled"; 279*f126890aSEmmanuel Vadot }; 280*f126890aSEmmanuel Vadot 281*f126890aSEmmanuel Vadot i2c1: i2c@400a0000 { 282*f126890aSEmmanuel Vadot compatible = "nxp,pnx-i2c"; 283*f126890aSEmmanuel Vadot reg = <0x400a0000 0x100>; 284*f126890aSEmmanuel Vadot interrupt-parent = <&sic1>; 285*f126890aSEmmanuel Vadot interrupts = <19 IRQ_TYPE_LEVEL_LOW>; 286*f126890aSEmmanuel Vadot #address-cells = <1>; 287*f126890aSEmmanuel Vadot #size-cells = <0>; 288*f126890aSEmmanuel Vadot clocks = <&clk LPC32XX_CLK_I2C1>; 289*f126890aSEmmanuel Vadot }; 290*f126890aSEmmanuel Vadot 291*f126890aSEmmanuel Vadot i2c2: i2c@400a8000 { 292*f126890aSEmmanuel Vadot compatible = "nxp,pnx-i2c"; 293*f126890aSEmmanuel Vadot reg = <0x400a8000 0x100>; 294*f126890aSEmmanuel Vadot interrupt-parent = <&sic1>; 295*f126890aSEmmanuel Vadot interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 296*f126890aSEmmanuel Vadot #address-cells = <1>; 297*f126890aSEmmanuel Vadot #size-cells = <0>; 298*f126890aSEmmanuel Vadot clocks = <&clk LPC32XX_CLK_I2C2>; 299*f126890aSEmmanuel Vadot }; 300*f126890aSEmmanuel Vadot 301*f126890aSEmmanuel Vadot mpwm: mpwm@400e8000 { 302*f126890aSEmmanuel Vadot compatible = "nxp,lpc3220-motor-pwm"; 303*f126890aSEmmanuel Vadot reg = <0x400e8000 0x78>; 304*f126890aSEmmanuel Vadot status = "disabled"; 305*f126890aSEmmanuel Vadot #pwm-cells = <2>; 306*f126890aSEmmanuel Vadot }; 307*f126890aSEmmanuel Vadot }; 308*f126890aSEmmanuel Vadot 309*f126890aSEmmanuel Vadot fab { 310*f126890aSEmmanuel Vadot #address-cells = <1>; 311*f126890aSEmmanuel Vadot #size-cells = <1>; 312*f126890aSEmmanuel Vadot compatible = "simple-bus"; 313*f126890aSEmmanuel Vadot ranges = <0x20000000 0x20000000 0x30000000>; 314*f126890aSEmmanuel Vadot 315*f126890aSEmmanuel Vadot /* System Control Block */ 316*f126890aSEmmanuel Vadot scb { 317*f126890aSEmmanuel Vadot compatible = "simple-bus"; 318*f126890aSEmmanuel Vadot ranges = <0x0 0x40004000 0x00001000>; 319*f126890aSEmmanuel Vadot #address-cells = <1>; 320*f126890aSEmmanuel Vadot #size-cells = <1>; 321*f126890aSEmmanuel Vadot 322*f126890aSEmmanuel Vadot clk: clock-controller@0 { 323*f126890aSEmmanuel Vadot compatible = "nxp,lpc3220-clk"; 324*f126890aSEmmanuel Vadot reg = <0x00 0x114>; 325*f126890aSEmmanuel Vadot #clock-cells = <1>; 326*f126890aSEmmanuel Vadot 327*f126890aSEmmanuel Vadot clocks = <&xtal_32k>, <&xtal>; 328*f126890aSEmmanuel Vadot clock-names = "xtal_32k", "xtal"; 329*f126890aSEmmanuel Vadot }; 330*f126890aSEmmanuel Vadot }; 331*f126890aSEmmanuel Vadot 332*f126890aSEmmanuel Vadot mic: interrupt-controller@40008000 { 333*f126890aSEmmanuel Vadot compatible = "nxp,lpc3220-mic"; 334*f126890aSEmmanuel Vadot reg = <0x40008000 0x4000>; 335*f126890aSEmmanuel Vadot interrupt-controller; 336*f126890aSEmmanuel Vadot #interrupt-cells = <2>; 337*f126890aSEmmanuel Vadot }; 338*f126890aSEmmanuel Vadot 339*f126890aSEmmanuel Vadot sic1: interrupt-controller@4000c000 { 340*f126890aSEmmanuel Vadot compatible = "nxp,lpc3220-sic"; 341*f126890aSEmmanuel Vadot reg = <0x4000c000 0x4000>; 342*f126890aSEmmanuel Vadot interrupt-controller; 343*f126890aSEmmanuel Vadot #interrupt-cells = <2>; 344*f126890aSEmmanuel Vadot 345*f126890aSEmmanuel Vadot interrupt-parent = <&mic>; 346*f126890aSEmmanuel Vadot interrupts = <0 IRQ_TYPE_LEVEL_LOW>, 347*f126890aSEmmanuel Vadot <30 IRQ_TYPE_LEVEL_LOW>; 348*f126890aSEmmanuel Vadot }; 349*f126890aSEmmanuel Vadot 350*f126890aSEmmanuel Vadot sic2: interrupt-controller@40010000 { 351*f126890aSEmmanuel Vadot compatible = "nxp,lpc3220-sic"; 352*f126890aSEmmanuel Vadot reg = <0x40010000 0x4000>; 353*f126890aSEmmanuel Vadot interrupt-controller; 354*f126890aSEmmanuel Vadot #interrupt-cells = <2>; 355*f126890aSEmmanuel Vadot 356*f126890aSEmmanuel Vadot interrupt-parent = <&mic>; 357*f126890aSEmmanuel Vadot interrupts = <1 IRQ_TYPE_LEVEL_LOW>, 358*f126890aSEmmanuel Vadot <31 IRQ_TYPE_LEVEL_LOW>; 359*f126890aSEmmanuel Vadot }; 360*f126890aSEmmanuel Vadot 361*f126890aSEmmanuel Vadot uart1: serial@40014000 { 362*f126890aSEmmanuel Vadot compatible = "nxp,lpc3220-hsuart"; 363*f126890aSEmmanuel Vadot reg = <0x40014000 0x1000>; 364*f126890aSEmmanuel Vadot interrupts = <26 IRQ_TYPE_LEVEL_HIGH>; 365*f126890aSEmmanuel Vadot status = "disabled"; 366*f126890aSEmmanuel Vadot }; 367*f126890aSEmmanuel Vadot 368*f126890aSEmmanuel Vadot uart2: serial@40018000 { 369*f126890aSEmmanuel Vadot compatible = "nxp,lpc3220-hsuart"; 370*f126890aSEmmanuel Vadot reg = <0x40018000 0x1000>; 371*f126890aSEmmanuel Vadot interrupts = <25 IRQ_TYPE_LEVEL_HIGH>; 372*f126890aSEmmanuel Vadot status = "disabled"; 373*f126890aSEmmanuel Vadot }; 374*f126890aSEmmanuel Vadot 375*f126890aSEmmanuel Vadot uart7: serial@4001c000 { 376*f126890aSEmmanuel Vadot compatible = "nxp,lpc3220-hsuart"; 377*f126890aSEmmanuel Vadot reg = <0x4001c000 0x1000>; 378*f126890aSEmmanuel Vadot interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; 379*f126890aSEmmanuel Vadot status = "disabled"; 380*f126890aSEmmanuel Vadot }; 381*f126890aSEmmanuel Vadot 382*f126890aSEmmanuel Vadot rtc: rtc@40024000 { 383*f126890aSEmmanuel Vadot compatible = "nxp,lpc3220-rtc"; 384*f126890aSEmmanuel Vadot reg = <0x40024000 0x1000>; 385*f126890aSEmmanuel Vadot interrupt-parent = <&sic1>; 386*f126890aSEmmanuel Vadot interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; 387*f126890aSEmmanuel Vadot clocks = <&clk LPC32XX_CLK_RTC>; 388*f126890aSEmmanuel Vadot }; 389*f126890aSEmmanuel Vadot 390*f126890aSEmmanuel Vadot gpio: gpio@40028000 { 391*f126890aSEmmanuel Vadot compatible = "nxp,lpc3220-gpio"; 392*f126890aSEmmanuel Vadot reg = <0x40028000 0x1000>; 393*f126890aSEmmanuel Vadot gpio-controller; 394*f126890aSEmmanuel Vadot #gpio-cells = <3>; /* bank, pin, flags */ 395*f126890aSEmmanuel Vadot }; 396*f126890aSEmmanuel Vadot 397*f126890aSEmmanuel Vadot timer4: timer@4002c000 { 398*f126890aSEmmanuel Vadot compatible = "nxp,lpc3220-timer"; 399*f126890aSEmmanuel Vadot reg = <0x4002c000 0x1000>; 400*f126890aSEmmanuel Vadot interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 401*f126890aSEmmanuel Vadot clocks = <&clk LPC32XX_CLK_TIMER4>; 402*f126890aSEmmanuel Vadot clock-names = "timerclk"; 403*f126890aSEmmanuel Vadot status = "disabled"; 404*f126890aSEmmanuel Vadot }; 405*f126890aSEmmanuel Vadot 406*f126890aSEmmanuel Vadot timer5: timer@40030000 { 407*f126890aSEmmanuel Vadot compatible = "nxp,lpc3220-timer"; 408*f126890aSEmmanuel Vadot reg = <0x40030000 0x1000>; 409*f126890aSEmmanuel Vadot interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 410*f126890aSEmmanuel Vadot clocks = <&clk LPC32XX_CLK_TIMER5>; 411*f126890aSEmmanuel Vadot clock-names = "timerclk"; 412*f126890aSEmmanuel Vadot status = "disabled"; 413*f126890aSEmmanuel Vadot }; 414*f126890aSEmmanuel Vadot 415*f126890aSEmmanuel Vadot watchdog: watchdog@4003c000 { 416*f126890aSEmmanuel Vadot compatible = "nxp,pnx4008-wdt"; 417*f126890aSEmmanuel Vadot reg = <0x4003c000 0x1000>; 418*f126890aSEmmanuel Vadot clocks = <&clk LPC32XX_CLK_WDOG>; 419*f126890aSEmmanuel Vadot }; 420*f126890aSEmmanuel Vadot 421*f126890aSEmmanuel Vadot timer0: timer@40044000 { 422*f126890aSEmmanuel Vadot compatible = "nxp,lpc3220-timer"; 423*f126890aSEmmanuel Vadot reg = <0x40044000 0x1000>; 424*f126890aSEmmanuel Vadot clocks = <&clk LPC32XX_CLK_TIMER0>; 425*f126890aSEmmanuel Vadot clock-names = "timerclk"; 426*f126890aSEmmanuel Vadot interrupts = <16 IRQ_TYPE_LEVEL_LOW>; 427*f126890aSEmmanuel Vadot }; 428*f126890aSEmmanuel Vadot 429*f126890aSEmmanuel Vadot /* 430*f126890aSEmmanuel Vadot * TSC vs. ADC: Since those two share the same 431*f126890aSEmmanuel Vadot * hardware, you need to choose from one of the 432*f126890aSEmmanuel Vadot * following two and do 'status = "okay";' for one of 433*f126890aSEmmanuel Vadot * them 434*f126890aSEmmanuel Vadot */ 435*f126890aSEmmanuel Vadot 436*f126890aSEmmanuel Vadot adc: adc@40048000 { 437*f126890aSEmmanuel Vadot compatible = "nxp,lpc3220-adc"; 438*f126890aSEmmanuel Vadot reg = <0x40048000 0x1000>; 439*f126890aSEmmanuel Vadot interrupt-parent = <&sic1>; 440*f126890aSEmmanuel Vadot interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; 441*f126890aSEmmanuel Vadot clocks = <&clk LPC32XX_CLK_ADC>; 442*f126890aSEmmanuel Vadot status = "disabled"; 443*f126890aSEmmanuel Vadot }; 444*f126890aSEmmanuel Vadot 445*f126890aSEmmanuel Vadot tsc: tsc@40048000 { 446*f126890aSEmmanuel Vadot compatible = "nxp,lpc3220-tsc"; 447*f126890aSEmmanuel Vadot reg = <0x40048000 0x1000>; 448*f126890aSEmmanuel Vadot interrupt-parent = <&sic1>; 449*f126890aSEmmanuel Vadot interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; 450*f126890aSEmmanuel Vadot clocks = <&clk LPC32XX_CLK_ADC>; 451*f126890aSEmmanuel Vadot status = "disabled"; 452*f126890aSEmmanuel Vadot }; 453*f126890aSEmmanuel Vadot 454*f126890aSEmmanuel Vadot timer1: timer@4004c000 { 455*f126890aSEmmanuel Vadot compatible = "nxp,lpc3220-timer"; 456*f126890aSEmmanuel Vadot reg = <0x4004c000 0x1000>; 457*f126890aSEmmanuel Vadot interrupts = <17 IRQ_TYPE_LEVEL_LOW>; 458*f126890aSEmmanuel Vadot clocks = <&clk LPC32XX_CLK_TIMER1>; 459*f126890aSEmmanuel Vadot clock-names = "timerclk"; 460*f126890aSEmmanuel Vadot }; 461*f126890aSEmmanuel Vadot 462*f126890aSEmmanuel Vadot key: key@40050000 { 463*f126890aSEmmanuel Vadot compatible = "nxp,lpc3220-key"; 464*f126890aSEmmanuel Vadot reg = <0x40050000 0x1000>; 465*f126890aSEmmanuel Vadot clocks = <&clk LPC32XX_CLK_KEY>; 466*f126890aSEmmanuel Vadot interrupt-parent = <&sic1>; 467*f126890aSEmmanuel Vadot interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; 468*f126890aSEmmanuel Vadot status = "disabled"; 469*f126890aSEmmanuel Vadot }; 470*f126890aSEmmanuel Vadot 471*f126890aSEmmanuel Vadot timer2: timer@40058000 { 472*f126890aSEmmanuel Vadot compatible = "nxp,lpc3220-timer"; 473*f126890aSEmmanuel Vadot reg = <0x40058000 0x1000>; 474*f126890aSEmmanuel Vadot interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 475*f126890aSEmmanuel Vadot clocks = <&clk LPC32XX_CLK_TIMER2>; 476*f126890aSEmmanuel Vadot clock-names = "timerclk"; 477*f126890aSEmmanuel Vadot status = "disabled"; 478*f126890aSEmmanuel Vadot }; 479*f126890aSEmmanuel Vadot 480*f126890aSEmmanuel Vadot pwm1: pwm@4005c000 { 481*f126890aSEmmanuel Vadot compatible = "nxp,lpc3220-pwm"; 482*f126890aSEmmanuel Vadot reg = <0x4005c000 0x4>; 483*f126890aSEmmanuel Vadot clocks = <&clk LPC32XX_CLK_PWM1>; 484*f126890aSEmmanuel Vadot assigned-clocks = <&clk LPC32XX_CLK_PWM1>; 485*f126890aSEmmanuel Vadot assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>; 486*f126890aSEmmanuel Vadot status = "disabled"; 487*f126890aSEmmanuel Vadot }; 488*f126890aSEmmanuel Vadot 489*f126890aSEmmanuel Vadot pwm2: pwm@4005c004 { 490*f126890aSEmmanuel Vadot compatible = "nxp,lpc3220-pwm"; 491*f126890aSEmmanuel Vadot reg = <0x4005c004 0x4>; 492*f126890aSEmmanuel Vadot clocks = <&clk LPC32XX_CLK_PWM2>; 493*f126890aSEmmanuel Vadot assigned-clocks = <&clk LPC32XX_CLK_PWM2>; 494*f126890aSEmmanuel Vadot assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>; 495*f126890aSEmmanuel Vadot status = "disabled"; 496*f126890aSEmmanuel Vadot }; 497*f126890aSEmmanuel Vadot 498*f126890aSEmmanuel Vadot timer3: timer@40060000 { 499*f126890aSEmmanuel Vadot compatible = "nxp,lpc3220-timer"; 500*f126890aSEmmanuel Vadot reg = <0x40060000 0x1000>; 501*f126890aSEmmanuel Vadot interrupts = <19 IRQ_TYPE_LEVEL_LOW>; 502*f126890aSEmmanuel Vadot clocks = <&clk LPC32XX_CLK_TIMER3>; 503*f126890aSEmmanuel Vadot clock-names = "timerclk"; 504*f126890aSEmmanuel Vadot status = "disabled"; 505*f126890aSEmmanuel Vadot }; 506*f126890aSEmmanuel Vadot }; 507*f126890aSEmmanuel Vadot }; 508*f126890aSEmmanuel Vadot}; 509