1f126890aSEmmanuel Vadot// SPDX-License-Identifier: GPL-2.0+ OR MIT 2f126890aSEmmanuel Vadot/* 3f126890aSEmmanuel Vadot * Device Tree Source for Qualcomm MDM9615 SoC 4f126890aSEmmanuel Vadot * 5f126890aSEmmanuel Vadot * Copyright (C) 2016 BayLibre, SAS. 6f126890aSEmmanuel Vadot * Author : Neil Armstrong <narmstrong@baylibre.com> 7f126890aSEmmanuel Vadot */ 8f126890aSEmmanuel Vadot 9f126890aSEmmanuel Vadot/dts-v1/; 10f126890aSEmmanuel Vadot 11f126890aSEmmanuel Vadot#include <dt-bindings/interrupt-controller/arm-gic.h> 12f126890aSEmmanuel Vadot#include <dt-bindings/clock/qcom,gcc-mdm9615.h> 13aa1a8ff2SEmmanuel Vadot#include <dt-bindings/clock/qcom,lcc-msm8960.h> 14f126890aSEmmanuel Vadot#include <dt-bindings/reset/qcom,gcc-mdm9615.h> 15f126890aSEmmanuel Vadot#include <dt-bindings/mfd/qcom-rpm.h> 16f126890aSEmmanuel Vadot#include <dt-bindings/soc/qcom,gsbi.h> 17f126890aSEmmanuel Vadot 18f126890aSEmmanuel Vadot/ { 19f126890aSEmmanuel Vadot #address-cells = <1>; 20f126890aSEmmanuel Vadot #size-cells = <1>; 21f126890aSEmmanuel Vadot model = "Qualcomm MDM9615"; 22f126890aSEmmanuel Vadot compatible = "qcom,mdm9615"; 23f126890aSEmmanuel Vadot interrupt-parent = <&intc>; 24f126890aSEmmanuel Vadot 25f126890aSEmmanuel Vadot cpus { 26f126890aSEmmanuel Vadot #address-cells = <1>; 27f126890aSEmmanuel Vadot #size-cells = <0>; 28f126890aSEmmanuel Vadot 29f126890aSEmmanuel Vadot cpu0: cpu@0 { 30f126890aSEmmanuel Vadot compatible = "arm,cortex-a5"; 31f126890aSEmmanuel Vadot reg = <0>; 32f126890aSEmmanuel Vadot device_type = "cpu"; 33f126890aSEmmanuel Vadot next-level-cache = <&L2>; 34f126890aSEmmanuel Vadot }; 35f126890aSEmmanuel Vadot }; 36f126890aSEmmanuel Vadot 37f126890aSEmmanuel Vadot cpu-pmu { 38f126890aSEmmanuel Vadot compatible = "arm,cortex-a5-pmu"; 39f126890aSEmmanuel Vadot interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 40f126890aSEmmanuel Vadot }; 41f126890aSEmmanuel Vadot 42f126890aSEmmanuel Vadot clocks { 43aa1a8ff2SEmmanuel Vadot cxo_board: cxo_board { 44f126890aSEmmanuel Vadot compatible = "fixed-clock"; 45f126890aSEmmanuel Vadot #clock-cells = <0>; 46f126890aSEmmanuel Vadot clock-frequency = <19200000>; 47f126890aSEmmanuel Vadot }; 48f126890aSEmmanuel Vadot }; 49f126890aSEmmanuel Vadot 50f126890aSEmmanuel Vadot vsdcc_fixed: vsdcc-regulator { 51f126890aSEmmanuel Vadot compatible = "regulator-fixed"; 52f126890aSEmmanuel Vadot regulator-name = "SDCC Power"; 53f126890aSEmmanuel Vadot regulator-min-microvolt = <2700000>; 54f126890aSEmmanuel Vadot regulator-max-microvolt = <2700000>; 55f126890aSEmmanuel Vadot regulator-always-on; 56f126890aSEmmanuel Vadot }; 57f126890aSEmmanuel Vadot 58f126890aSEmmanuel Vadot soc: soc { 59f126890aSEmmanuel Vadot #address-cells = <1>; 60f126890aSEmmanuel Vadot #size-cells = <1>; 61f126890aSEmmanuel Vadot ranges; 62f126890aSEmmanuel Vadot compatible = "simple-bus"; 63f126890aSEmmanuel Vadot 64f126890aSEmmanuel Vadot L2: cache-controller@2040000 { 65f126890aSEmmanuel Vadot compatible = "arm,pl310-cache"; 66f126890aSEmmanuel Vadot reg = <0x02040000 0x1000>; 67f126890aSEmmanuel Vadot arm,data-latency = <2 2 0>; 68f126890aSEmmanuel Vadot cache-unified; 69f126890aSEmmanuel Vadot cache-level = <2>; 70f126890aSEmmanuel Vadot }; 71f126890aSEmmanuel Vadot 72f126890aSEmmanuel Vadot intc: interrupt-controller@2000000 { 73f126890aSEmmanuel Vadot compatible = "qcom,msm-qgic2"; 74f126890aSEmmanuel Vadot interrupt-controller; 75f126890aSEmmanuel Vadot #interrupt-cells = <3>; 76f126890aSEmmanuel Vadot reg = <0x02000000 0x1000>, 77f126890aSEmmanuel Vadot <0x02002000 0x1000>; 78f126890aSEmmanuel Vadot }; 79f126890aSEmmanuel Vadot 80f126890aSEmmanuel Vadot timer@200a000 { 81f126890aSEmmanuel Vadot compatible = "qcom,kpss-wdt-mdm9615", "qcom,kpss-timer", 82f126890aSEmmanuel Vadot "qcom,msm-timer"; 83f126890aSEmmanuel Vadot interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>, 84f126890aSEmmanuel Vadot <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>, 85f126890aSEmmanuel Vadot <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>; 86f126890aSEmmanuel Vadot reg = <0x0200a000 0x100>; 87f126890aSEmmanuel Vadot clock-frequency = <27000000>; 88f126890aSEmmanuel Vadot cpu-offset = <0x80000>; 89f126890aSEmmanuel Vadot }; 90f126890aSEmmanuel Vadot 91f126890aSEmmanuel Vadot msmgpio: pinctrl@800000 { 92f126890aSEmmanuel Vadot compatible = "qcom,mdm9615-pinctrl"; 93f126890aSEmmanuel Vadot gpio-controller; 94f126890aSEmmanuel Vadot gpio-ranges = <&msmgpio 0 0 88>; 95f126890aSEmmanuel Vadot #gpio-cells = <2>; 96f126890aSEmmanuel Vadot interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 97f126890aSEmmanuel Vadot interrupt-controller; 98f126890aSEmmanuel Vadot #interrupt-cells = <2>; 99f126890aSEmmanuel Vadot reg = <0x800000 0x4000>; 100f126890aSEmmanuel Vadot }; 101f126890aSEmmanuel Vadot 102f126890aSEmmanuel Vadot gcc: clock-controller@900000 { 103f126890aSEmmanuel Vadot compatible = "qcom,gcc-mdm9615"; 104f126890aSEmmanuel Vadot #clock-cells = <1>; 105f126890aSEmmanuel Vadot #power-domain-cells = <1>; 106f126890aSEmmanuel Vadot #reset-cells = <1>; 107f126890aSEmmanuel Vadot reg = <0x900000 0x4000>; 108aa1a8ff2SEmmanuel Vadot clocks = <&cxo_board>, 109aa1a8ff2SEmmanuel Vadot <&lcc PLL4>; 110f126890aSEmmanuel Vadot }; 111f126890aSEmmanuel Vadot 112f126890aSEmmanuel Vadot lcc: clock-controller@28000000 { 113f126890aSEmmanuel Vadot compatible = "qcom,lcc-mdm9615"; 114f126890aSEmmanuel Vadot reg = <0x28000000 0x1000>; 115f126890aSEmmanuel Vadot #clock-cells = <1>; 116f126890aSEmmanuel Vadot #reset-cells = <1>; 117aa1a8ff2SEmmanuel Vadot clocks = <&cxo_board>, 118aa1a8ff2SEmmanuel Vadot <&gcc PLL4_VOTE>, 119aa1a8ff2SEmmanuel Vadot <0>, 120aa1a8ff2SEmmanuel Vadot <0>, <0>, 121aa1a8ff2SEmmanuel Vadot <0>, <0>, 122aa1a8ff2SEmmanuel Vadot <0>; 123aa1a8ff2SEmmanuel Vadot clock-names = "cxo", 124aa1a8ff2SEmmanuel Vadot "pll4_vote", 125aa1a8ff2SEmmanuel Vadot "mi2s_codec_clk", 126aa1a8ff2SEmmanuel Vadot "codec_i2s_mic_codec_clk", 127aa1a8ff2SEmmanuel Vadot "spare_i2s_mic_codec_clk", 128aa1a8ff2SEmmanuel Vadot "codec_i2s_spkr_codec_clk", 129aa1a8ff2SEmmanuel Vadot "spare_i2s_spkr_codec_clk", 130aa1a8ff2SEmmanuel Vadot "pcm_codec_clk"; 131f126890aSEmmanuel Vadot }; 132f126890aSEmmanuel Vadot 133f126890aSEmmanuel Vadot l2cc: clock-controller@2011000 { 134f126890aSEmmanuel Vadot compatible = "qcom,kpss-gcc-mdm9615", "qcom,kpss-gcc", "syscon"; 135f126890aSEmmanuel Vadot reg = <0x02011000 0x1000>; 136f126890aSEmmanuel Vadot }; 137f126890aSEmmanuel Vadot 138f126890aSEmmanuel Vadot rng@1a500000 { 139f126890aSEmmanuel Vadot compatible = "qcom,prng"; 140f126890aSEmmanuel Vadot reg = <0x1a500000 0x200>; 141f126890aSEmmanuel Vadot clocks = <&gcc PRNG_CLK>; 142f126890aSEmmanuel Vadot clock-names = "core"; 143f126890aSEmmanuel Vadot assigned-clocks = <&gcc PRNG_CLK>; 144f126890aSEmmanuel Vadot assigned-clock-rates = <32000000>; 145f126890aSEmmanuel Vadot }; 146f126890aSEmmanuel Vadot 147f126890aSEmmanuel Vadot gsbi2: gsbi@16100000 { 148f126890aSEmmanuel Vadot compatible = "qcom,gsbi-v1.0.0"; 149f126890aSEmmanuel Vadot cell-index = <2>; 150f126890aSEmmanuel Vadot reg = <0x16100000 0x100>; 151f126890aSEmmanuel Vadot clocks = <&gcc GSBI2_H_CLK>; 152f126890aSEmmanuel Vadot clock-names = "iface"; 153f126890aSEmmanuel Vadot status = "disabled"; 154f126890aSEmmanuel Vadot #address-cells = <1>; 155f126890aSEmmanuel Vadot #size-cells = <1>; 156f126890aSEmmanuel Vadot ranges; 157f126890aSEmmanuel Vadot 158f126890aSEmmanuel Vadot gsbi2_i2c: i2c@16180000 { 159f126890aSEmmanuel Vadot compatible = "qcom,i2c-qup-v1.1.1"; 160f126890aSEmmanuel Vadot #address-cells = <1>; 161f126890aSEmmanuel Vadot #size-cells = <0>; 162f126890aSEmmanuel Vadot reg = <0x16180000 0x1000>; 163f126890aSEmmanuel Vadot interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 164f126890aSEmmanuel Vadot 165f126890aSEmmanuel Vadot clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; 166f126890aSEmmanuel Vadot clock-names = "core", "iface"; 167f126890aSEmmanuel Vadot status = "disabled"; 168f126890aSEmmanuel Vadot }; 169f126890aSEmmanuel Vadot }; 170f126890aSEmmanuel Vadot 171f126890aSEmmanuel Vadot gsbi3: gsbi@16200000 { 172f126890aSEmmanuel Vadot compatible = "qcom,gsbi-v1.0.0"; 173f126890aSEmmanuel Vadot cell-index = <3>; 174f126890aSEmmanuel Vadot reg = <0x16200000 0x100>; 175f126890aSEmmanuel Vadot clocks = <&gcc GSBI3_H_CLK>; 176f126890aSEmmanuel Vadot clock-names = "iface"; 177f126890aSEmmanuel Vadot status = "disabled"; 178f126890aSEmmanuel Vadot #address-cells = <1>; 179f126890aSEmmanuel Vadot #size-cells = <1>; 180f126890aSEmmanuel Vadot ranges; 181f126890aSEmmanuel Vadot 182f126890aSEmmanuel Vadot gsbi3_spi: spi@16280000 { 183f126890aSEmmanuel Vadot compatible = "qcom,spi-qup-v1.1.1"; 184f126890aSEmmanuel Vadot #address-cells = <1>; 185f126890aSEmmanuel Vadot #size-cells = <0>; 186f126890aSEmmanuel Vadot reg = <0x16280000 0x1000>; 187f126890aSEmmanuel Vadot interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 188f126890aSEmmanuel Vadot 189f126890aSEmmanuel Vadot clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>; 190f126890aSEmmanuel Vadot clock-names = "core", "iface"; 191f126890aSEmmanuel Vadot status = "disabled"; 192f126890aSEmmanuel Vadot }; 193f126890aSEmmanuel Vadot }; 194f126890aSEmmanuel Vadot 195f126890aSEmmanuel Vadot gsbi4: gsbi@16300000 { 196f126890aSEmmanuel Vadot compatible = "qcom,gsbi-v1.0.0"; 197f126890aSEmmanuel Vadot cell-index = <4>; 198f126890aSEmmanuel Vadot reg = <0x16300000 0x100>; 199f126890aSEmmanuel Vadot clocks = <&gcc GSBI4_H_CLK>; 200f126890aSEmmanuel Vadot clock-names = "iface"; 201f126890aSEmmanuel Vadot status = "disabled"; 202f126890aSEmmanuel Vadot #address-cells = <1>; 203f126890aSEmmanuel Vadot #size-cells = <1>; 204f126890aSEmmanuel Vadot ranges; 205f126890aSEmmanuel Vadot 206f126890aSEmmanuel Vadot syscon-tcsr = <&tcsr>; 207f126890aSEmmanuel Vadot 208f126890aSEmmanuel Vadot gsbi4_serial: serial@16340000 { 209f126890aSEmmanuel Vadot compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 210f126890aSEmmanuel Vadot reg = <0x16340000 0x1000>, 211f126890aSEmmanuel Vadot <0x16300000 0x1000>; 212f126890aSEmmanuel Vadot interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 213f126890aSEmmanuel Vadot clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; 214f126890aSEmmanuel Vadot clock-names = "core", "iface"; 215f126890aSEmmanuel Vadot status = "disabled"; 216f126890aSEmmanuel Vadot }; 217f126890aSEmmanuel Vadot }; 218f126890aSEmmanuel Vadot 219f126890aSEmmanuel Vadot gsbi5: gsbi@16400000 { 220f126890aSEmmanuel Vadot compatible = "qcom,gsbi-v1.0.0"; 221f126890aSEmmanuel Vadot cell-index = <5>; 222f126890aSEmmanuel Vadot reg = <0x16400000 0x100>; 223f126890aSEmmanuel Vadot clocks = <&gcc GSBI5_H_CLK>; 224f126890aSEmmanuel Vadot clock-names = "iface"; 225f126890aSEmmanuel Vadot status = "disabled"; 226f126890aSEmmanuel Vadot #address-cells = <1>; 227f126890aSEmmanuel Vadot #size-cells = <1>; 228f126890aSEmmanuel Vadot ranges; 229f126890aSEmmanuel Vadot 230f126890aSEmmanuel Vadot syscon-tcsr = <&tcsr>; 231f126890aSEmmanuel Vadot 232f126890aSEmmanuel Vadot gsbi5_i2c: i2c@16480000 { 233f126890aSEmmanuel Vadot compatible = "qcom,i2c-qup-v1.1.1"; 234f126890aSEmmanuel Vadot #address-cells = <1>; 235f126890aSEmmanuel Vadot #size-cells = <0>; 236f126890aSEmmanuel Vadot reg = <0x16480000 0x1000>; 237f126890aSEmmanuel Vadot interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 238f126890aSEmmanuel Vadot 239f126890aSEmmanuel Vadot /* QUP clock is not initialized, set rate */ 240f126890aSEmmanuel Vadot assigned-clocks = <&gcc GSBI5_QUP_CLK>; 241f126890aSEmmanuel Vadot assigned-clock-rates = <24000000>; 242f126890aSEmmanuel Vadot 243f126890aSEmmanuel Vadot clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; 244f126890aSEmmanuel Vadot clock-names = "core", "iface"; 245f126890aSEmmanuel Vadot status = "disabled"; 246f126890aSEmmanuel Vadot }; 247f126890aSEmmanuel Vadot 248f126890aSEmmanuel Vadot gsbi5_serial: serial@16440000 { 249f126890aSEmmanuel Vadot compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 250f126890aSEmmanuel Vadot reg = <0x16440000 0x1000>, 251f126890aSEmmanuel Vadot <0x16400000 0x1000>; 252f126890aSEmmanuel Vadot interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 253f126890aSEmmanuel Vadot clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; 254f126890aSEmmanuel Vadot clock-names = "core", "iface"; 255f126890aSEmmanuel Vadot status = "disabled"; 256f126890aSEmmanuel Vadot }; 257f126890aSEmmanuel Vadot }; 258f126890aSEmmanuel Vadot 259*8d13bc63SEmmanuel Vadot ssbi: ssbi@500000 { 260f126890aSEmmanuel Vadot compatible = "qcom,ssbi"; 261f126890aSEmmanuel Vadot reg = <0x500000 0x1000>; 262f126890aSEmmanuel Vadot qcom,controller-type = "pmic-arbiter"; 263f126890aSEmmanuel Vadot }; 264f126890aSEmmanuel Vadot 265f126890aSEmmanuel Vadot sdcc1bam: dma-controller@12182000 { 266f126890aSEmmanuel Vadot compatible = "qcom,bam-v1.3.0"; 267f126890aSEmmanuel Vadot reg = <0x12182000 0x8000>; 268f126890aSEmmanuel Vadot interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 269f126890aSEmmanuel Vadot clocks = <&gcc SDC1_H_CLK>; 270f126890aSEmmanuel Vadot clock-names = "bam_clk"; 271f126890aSEmmanuel Vadot #dma-cells = <1>; 272f126890aSEmmanuel Vadot qcom,ee = <0>; 273f126890aSEmmanuel Vadot }; 274f126890aSEmmanuel Vadot 275f126890aSEmmanuel Vadot sdcc2bam: dma-controller@12142000 { 276f126890aSEmmanuel Vadot compatible = "qcom,bam-v1.3.0"; 277f126890aSEmmanuel Vadot reg = <0x12142000 0x8000>; 278f126890aSEmmanuel Vadot interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 279f126890aSEmmanuel Vadot clocks = <&gcc SDC2_H_CLK>; 280f126890aSEmmanuel Vadot clock-names = "bam_clk"; 281f126890aSEmmanuel Vadot #dma-cells = <1>; 282f126890aSEmmanuel Vadot qcom,ee = <0>; 283f126890aSEmmanuel Vadot }; 284f126890aSEmmanuel Vadot 285f126890aSEmmanuel Vadot sdcc1: mmc@12180000 { 286f126890aSEmmanuel Vadot status = "disabled"; 287f126890aSEmmanuel Vadot compatible = "arm,pl18x", "arm,primecell"; 288f126890aSEmmanuel Vadot arm,primecell-periphid = <0x00051180>; 289f126890aSEmmanuel Vadot reg = <0x12180000 0x2000>; 290f126890aSEmmanuel Vadot interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 291f126890aSEmmanuel Vadot clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 292f126890aSEmmanuel Vadot clock-names = "mclk", "apb_pclk"; 293f126890aSEmmanuel Vadot bus-width = <8>; 294f126890aSEmmanuel Vadot max-frequency = <48000000>; 295f126890aSEmmanuel Vadot cap-sd-highspeed; 296f126890aSEmmanuel Vadot cap-mmc-highspeed; 297f126890aSEmmanuel Vadot vmmc-supply = <&vsdcc_fixed>; 298f126890aSEmmanuel Vadot dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; 299f126890aSEmmanuel Vadot dma-names = "tx", "rx"; 300f126890aSEmmanuel Vadot assigned-clocks = <&gcc SDC1_CLK>; 301f126890aSEmmanuel Vadot assigned-clock-rates = <400000>; 302f126890aSEmmanuel Vadot }; 303f126890aSEmmanuel Vadot 304f126890aSEmmanuel Vadot sdcc2: mmc@12140000 { 305f126890aSEmmanuel Vadot compatible = "arm,pl18x", "arm,primecell"; 306f126890aSEmmanuel Vadot arm,primecell-periphid = <0x00051180>; 307f126890aSEmmanuel Vadot status = "disabled"; 308f126890aSEmmanuel Vadot reg = <0x12140000 0x2000>; 309f126890aSEmmanuel Vadot interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 310f126890aSEmmanuel Vadot clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; 311f126890aSEmmanuel Vadot clock-names = "mclk", "apb_pclk"; 312f126890aSEmmanuel Vadot bus-width = <4>; 313f126890aSEmmanuel Vadot cap-sd-highspeed; 314f126890aSEmmanuel Vadot cap-mmc-highspeed; 315f126890aSEmmanuel Vadot max-frequency = <48000000>; 316f126890aSEmmanuel Vadot no-1-8-v; 317f126890aSEmmanuel Vadot vmmc-supply = <&vsdcc_fixed>; 318f126890aSEmmanuel Vadot dmas = <&sdcc2bam 2>, <&sdcc2bam 1>; 319f126890aSEmmanuel Vadot dma-names = "tx", "rx"; 320f126890aSEmmanuel Vadot assigned-clocks = <&gcc SDC2_CLK>; 321f126890aSEmmanuel Vadot assigned-clock-rates = <400000>; 322f126890aSEmmanuel Vadot }; 323f126890aSEmmanuel Vadot 324f126890aSEmmanuel Vadot tcsr: syscon@1a400000 { 325f126890aSEmmanuel Vadot compatible = "qcom,tcsr-mdm9615", "syscon"; 326f126890aSEmmanuel Vadot reg = <0x1a400000 0x100>; 327f126890aSEmmanuel Vadot }; 328f126890aSEmmanuel Vadot 329f126890aSEmmanuel Vadot rpm: rpm@108000 { 330f126890aSEmmanuel Vadot compatible = "qcom,rpm-mdm9615"; 331f126890aSEmmanuel Vadot reg = <0x108000 0x1000>; 332f126890aSEmmanuel Vadot 333f126890aSEmmanuel Vadot qcom,ipc = <&l2cc 0x8 2>; 334f126890aSEmmanuel Vadot 335f126890aSEmmanuel Vadot interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, 336f126890aSEmmanuel Vadot <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 337f126890aSEmmanuel Vadot <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 338f126890aSEmmanuel Vadot interrupt-names = "ack", "err", "wakeup"; 339f126890aSEmmanuel Vadot }; 340f126890aSEmmanuel Vadot }; 341f126890aSEmmanuel Vadot}; 342