1*f126890aSEmmanuel Vadot// SPDX-License-Identifier: GPL-2.0 2*f126890aSEmmanuel Vadot/* 3*f126890aSEmmanuel Vadot * Device Tree Source for the iWave-RZ/G1H Qseven board development 4*f126890aSEmmanuel Vadot * platform with camera daughter board 5*f126890aSEmmanuel Vadot * 6*f126890aSEmmanuel Vadot * Copyright (C) 2020 Renesas Electronics Corp. 7*f126890aSEmmanuel Vadot */ 8*f126890aSEmmanuel Vadot 9*f126890aSEmmanuel Vadot/dts-v1/; 10*f126890aSEmmanuel Vadot 11*f126890aSEmmanuel Vadot#include <dt-bindings/media/video-interfaces.h> 12*f126890aSEmmanuel Vadot 13*f126890aSEmmanuel Vadot#include "r8a7742-iwg21d-q7.dts" 14*f126890aSEmmanuel Vadot 15*f126890aSEmmanuel Vadot/ { 16*f126890aSEmmanuel Vadot model = "iWave Systems RZ/G1H Qseven development platform with camera add-on"; 17*f126890aSEmmanuel Vadot compatible = "iwave,g21d", "iwave,g21m", "renesas,r8a7742"; 18*f126890aSEmmanuel Vadot 19*f126890aSEmmanuel Vadot aliases { 20*f126890aSEmmanuel Vadot serial0 = &scif0; 21*f126890aSEmmanuel Vadot serial1 = &scif1; 22*f126890aSEmmanuel Vadot serial3 = &scifb1; 23*f126890aSEmmanuel Vadot serial5 = &hscif0; 24*f126890aSEmmanuel Vadot ethernet1 = ðer; 25*f126890aSEmmanuel Vadot }; 26*f126890aSEmmanuel Vadot 27*f126890aSEmmanuel Vadot mclk_cam1: mclk-cam1 { 28*f126890aSEmmanuel Vadot compatible = "fixed-clock"; 29*f126890aSEmmanuel Vadot #clock-cells = <0>; 30*f126890aSEmmanuel Vadot clock-frequency = <26000000>; 31*f126890aSEmmanuel Vadot }; 32*f126890aSEmmanuel Vadot 33*f126890aSEmmanuel Vadot mclk_cam2: mclk-cam2 { 34*f126890aSEmmanuel Vadot compatible = "fixed-clock"; 35*f126890aSEmmanuel Vadot #clock-cells = <0>; 36*f126890aSEmmanuel Vadot clock-frequency = <26000000>; 37*f126890aSEmmanuel Vadot }; 38*f126890aSEmmanuel Vadot 39*f126890aSEmmanuel Vadot mclk_cam3: mclk-cam3 { 40*f126890aSEmmanuel Vadot compatible = "fixed-clock"; 41*f126890aSEmmanuel Vadot #clock-cells = <0>; 42*f126890aSEmmanuel Vadot clock-frequency = <26000000>; 43*f126890aSEmmanuel Vadot }; 44*f126890aSEmmanuel Vadot 45*f126890aSEmmanuel Vadot mclk_cam4: mclk-cam4 { 46*f126890aSEmmanuel Vadot compatible = "fixed-clock"; 47*f126890aSEmmanuel Vadot #clock-cells = <0>; 48*f126890aSEmmanuel Vadot clock-frequency = <26000000>; 49*f126890aSEmmanuel Vadot }; 50*f126890aSEmmanuel Vadot 51*f126890aSEmmanuel Vadot reg_1p8v: 1p8v { 52*f126890aSEmmanuel Vadot compatible = "regulator-fixed"; 53*f126890aSEmmanuel Vadot regulator-name = "1P8V"; 54*f126890aSEmmanuel Vadot regulator-min-microvolt = <1800000>; 55*f126890aSEmmanuel Vadot regulator-max-microvolt = <1800000>; 56*f126890aSEmmanuel Vadot regulator-always-on; 57*f126890aSEmmanuel Vadot }; 58*f126890aSEmmanuel Vadot 59*f126890aSEmmanuel Vadot reg_2p8v: 2p8v { 60*f126890aSEmmanuel Vadot compatible = "regulator-fixed"; 61*f126890aSEmmanuel Vadot regulator-name = "2P8V"; 62*f126890aSEmmanuel Vadot regulator-min-microvolt = <2800000>; 63*f126890aSEmmanuel Vadot regulator-max-microvolt = <2800000>; 64*f126890aSEmmanuel Vadot regulator-always-on; 65*f126890aSEmmanuel Vadot }; 66*f126890aSEmmanuel Vadot}; 67*f126890aSEmmanuel Vadot 68*f126890aSEmmanuel Vadot&avb { 69*f126890aSEmmanuel Vadot /* Pins shared with VIN0, keep status disabled */ 70*f126890aSEmmanuel Vadot status = "disabled"; 71*f126890aSEmmanuel Vadot}; 72*f126890aSEmmanuel Vadot 73*f126890aSEmmanuel Vadot&can0 { 74*f126890aSEmmanuel Vadot pinctrl-0 = <&can0_pins>; 75*f126890aSEmmanuel Vadot pinctrl-names = "default"; 76*f126890aSEmmanuel Vadot status = "okay"; 77*f126890aSEmmanuel Vadot}; 78*f126890aSEmmanuel Vadot 79*f126890aSEmmanuel Vadotðer { 80*f126890aSEmmanuel Vadot pinctrl-0 = <ðer_pins>; 81*f126890aSEmmanuel Vadot pinctrl-names = "default"; 82*f126890aSEmmanuel Vadot 83*f126890aSEmmanuel Vadot phy-handle = <&phy1>; 84*f126890aSEmmanuel Vadot renesas,ether-link-active-low; 85*f126890aSEmmanuel Vadot status = "okay"; 86*f126890aSEmmanuel Vadot 87*f126890aSEmmanuel Vadot phy1: ethernet-phy@1 { 88*f126890aSEmmanuel Vadot compatible = "ethernet-phy-id0022.1560", 89*f126890aSEmmanuel Vadot "ethernet-phy-ieee802.3-c22"; 90*f126890aSEmmanuel Vadot reg = <1>; 91*f126890aSEmmanuel Vadot micrel,led-mode = <1>; 92*f126890aSEmmanuel Vadot }; 93*f126890aSEmmanuel Vadot}; 94*f126890aSEmmanuel Vadot 95*f126890aSEmmanuel Vadot&gpio0 { 96*f126890aSEmmanuel Vadot /* Disable hogging GP0_18 to output LOW */ 97*f126890aSEmmanuel Vadot /delete-node/ qspi-en-hog; 98*f126890aSEmmanuel Vadot 99*f126890aSEmmanuel Vadot /* Hog GP0_18 to output HIGH to enable VIN2 */ 100*f126890aSEmmanuel Vadot vin2-en-hog { 101*f126890aSEmmanuel Vadot gpio-hog; 102*f126890aSEmmanuel Vadot gpios = <18 GPIO_ACTIVE_HIGH>; 103*f126890aSEmmanuel Vadot output-high; 104*f126890aSEmmanuel Vadot line-name = "VIN2_EN"; 105*f126890aSEmmanuel Vadot }; 106*f126890aSEmmanuel Vadot}; 107*f126890aSEmmanuel Vadot 108*f126890aSEmmanuel Vadot&hscif0 { 109*f126890aSEmmanuel Vadot pinctrl-0 = <&hscif0_pins>; 110*f126890aSEmmanuel Vadot pinctrl-names = "default"; 111*f126890aSEmmanuel Vadot uart-has-rtscts; 112*f126890aSEmmanuel Vadot status = "okay"; 113*f126890aSEmmanuel Vadot}; 114*f126890aSEmmanuel Vadot 115*f126890aSEmmanuel Vadot&i2c1 { 116*f126890aSEmmanuel Vadot pinctrl-0 = <&i2c1_pins>; 117*f126890aSEmmanuel Vadot pinctrl-names = "default"; 118*f126890aSEmmanuel Vadot 119*f126890aSEmmanuel Vadot /* status set to "okay" when needed by camera configuration below */ 120*f126890aSEmmanuel Vadot clock-frequency = <400000>; 121*f126890aSEmmanuel Vadot}; 122*f126890aSEmmanuel Vadot 123*f126890aSEmmanuel Vadot&i2c3 { 124*f126890aSEmmanuel Vadot pinctrl-0 = <&i2c3_pins>; 125*f126890aSEmmanuel Vadot pinctrl-names = "default"; 126*f126890aSEmmanuel Vadot 127*f126890aSEmmanuel Vadot /* status set to "okay" when needed by camera configuration below */ 128*f126890aSEmmanuel Vadot clock-frequency = <400000>; 129*f126890aSEmmanuel Vadot}; 130*f126890aSEmmanuel Vadot 131*f126890aSEmmanuel Vadot&pfc { 132*f126890aSEmmanuel Vadot can0_pins: can0 { 133*f126890aSEmmanuel Vadot groups = "can0_data_d"; 134*f126890aSEmmanuel Vadot function = "can0"; 135*f126890aSEmmanuel Vadot }; 136*f126890aSEmmanuel Vadot 137*f126890aSEmmanuel Vadot ether_pins: ether { 138*f126890aSEmmanuel Vadot groups = "eth_mdio", "eth_rmii"; 139*f126890aSEmmanuel Vadot function = "eth"; 140*f126890aSEmmanuel Vadot }; 141*f126890aSEmmanuel Vadot 142*f126890aSEmmanuel Vadot hscif0_pins: hscif0 { 143*f126890aSEmmanuel Vadot groups = "hscif0_data", "hscif0_ctrl"; 144*f126890aSEmmanuel Vadot function = "hscif0"; 145*f126890aSEmmanuel Vadot }; 146*f126890aSEmmanuel Vadot 147*f126890aSEmmanuel Vadot i2c1_pins: i2c1 { 148*f126890aSEmmanuel Vadot groups = "i2c1_c"; 149*f126890aSEmmanuel Vadot function = "i2c1"; 150*f126890aSEmmanuel Vadot }; 151*f126890aSEmmanuel Vadot 152*f126890aSEmmanuel Vadot i2c3_pins: i2c3 { 153*f126890aSEmmanuel Vadot groups = "i2c3"; 154*f126890aSEmmanuel Vadot function = "i2c3"; 155*f126890aSEmmanuel Vadot }; 156*f126890aSEmmanuel Vadot 157*f126890aSEmmanuel Vadot scif0_pins: scif0 { 158*f126890aSEmmanuel Vadot groups = "scif0_data"; 159*f126890aSEmmanuel Vadot function = "scif0"; 160*f126890aSEmmanuel Vadot }; 161*f126890aSEmmanuel Vadot 162*f126890aSEmmanuel Vadot scif1_pins: scif1 { 163*f126890aSEmmanuel Vadot groups = "scif1_data"; 164*f126890aSEmmanuel Vadot function = "scif1"; 165*f126890aSEmmanuel Vadot }; 166*f126890aSEmmanuel Vadot 167*f126890aSEmmanuel Vadot scifb1_pins: scifb1 { 168*f126890aSEmmanuel Vadot groups = "scifb1_data"; 169*f126890aSEmmanuel Vadot function = "scifb1"; 170*f126890aSEmmanuel Vadot }; 171*f126890aSEmmanuel Vadot 172*f126890aSEmmanuel Vadot vin0_8bit_pins: vin0 { 173*f126890aSEmmanuel Vadot groups = "vin0_data8", "vin0_clk", "vin0_sync"; 174*f126890aSEmmanuel Vadot function = "vin0"; 175*f126890aSEmmanuel Vadot }; 176*f126890aSEmmanuel Vadot 177*f126890aSEmmanuel Vadot vin1_8bit_pins: vin1 { 178*f126890aSEmmanuel Vadot groups = "vin1_data8_b", "vin1_clk_b", "vin1_sync_b"; 179*f126890aSEmmanuel Vadot function = "vin1"; 180*f126890aSEmmanuel Vadot }; 181*f126890aSEmmanuel Vadot 182*f126890aSEmmanuel Vadot vin2_pins: vin2 { 183*f126890aSEmmanuel Vadot groups = "vin2_g8", "vin2_clk"; 184*f126890aSEmmanuel Vadot function = "vin2"; 185*f126890aSEmmanuel Vadot }; 186*f126890aSEmmanuel Vadot 187*f126890aSEmmanuel Vadot vin3_pins: vin3 { 188*f126890aSEmmanuel Vadot groups = "vin3_data8", "vin3_clk", "vin3_sync"; 189*f126890aSEmmanuel Vadot function = "vin3"; 190*f126890aSEmmanuel Vadot }; 191*f126890aSEmmanuel Vadot}; 192*f126890aSEmmanuel Vadot 193*f126890aSEmmanuel Vadot&qspi { 194*f126890aSEmmanuel Vadot /* Pins shared with VIN2, keep status disabled */ 195*f126890aSEmmanuel Vadot status = "disabled"; 196*f126890aSEmmanuel Vadot}; 197*f126890aSEmmanuel Vadot 198*f126890aSEmmanuel Vadot&scif0 { 199*f126890aSEmmanuel Vadot pinctrl-0 = <&scif0_pins>; 200*f126890aSEmmanuel Vadot pinctrl-names = "default"; 201*f126890aSEmmanuel Vadot status = "okay"; 202*f126890aSEmmanuel Vadot}; 203*f126890aSEmmanuel Vadot 204*f126890aSEmmanuel Vadot&scif1 { 205*f126890aSEmmanuel Vadot pinctrl-0 = <&scif1_pins>; 206*f126890aSEmmanuel Vadot pinctrl-names = "default"; 207*f126890aSEmmanuel Vadot status = "okay"; 208*f126890aSEmmanuel Vadot}; 209*f126890aSEmmanuel Vadot 210*f126890aSEmmanuel Vadot&scifb1 { 211*f126890aSEmmanuel Vadot pinctrl-0 = <&scifb1_pins>; 212*f126890aSEmmanuel Vadot pinctrl-names = "default"; 213*f126890aSEmmanuel Vadot status = "okay"; 214*f126890aSEmmanuel Vadot 215*f126890aSEmmanuel Vadot rts-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; 216*f126890aSEmmanuel Vadot cts-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; 217*f126890aSEmmanuel Vadot}; 218*f126890aSEmmanuel Vadot 219*f126890aSEmmanuel Vadot/* 220*f126890aSEmmanuel Vadot * Below configuration ties VINx endpoints to ov5640/ov7725 camera endpoints 221*f126890aSEmmanuel Vadot * 222*f126890aSEmmanuel Vadot * (un)comment the #include statements to change configuration 223*f126890aSEmmanuel Vadot */ 224*f126890aSEmmanuel Vadot 225*f126890aSEmmanuel Vadot/* 8bit CMOS Camera 1 (J13) */ 226*f126890aSEmmanuel Vadot#define CAM_PARENT_I2C i2c0 227*f126890aSEmmanuel Vadot#define MCLK_CAM mclk_cam1 228*f126890aSEmmanuel Vadot#define CAM_EP cam0ep 229*f126890aSEmmanuel Vadot#define VIN_EP vin0ep 230*f126890aSEmmanuel Vadot#undef CAM_ENABLED 231*f126890aSEmmanuel Vadot#include "r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi" 232*f126890aSEmmanuel Vadot//#include "r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi" 233*f126890aSEmmanuel Vadot 234*f126890aSEmmanuel Vadot#ifdef CAM_ENABLED 235*f126890aSEmmanuel Vadot&vin0 { 236*f126890aSEmmanuel Vadot /* 237*f126890aSEmmanuel Vadot * Set SW2 switch on the SOM to 'ON' 238*f126890aSEmmanuel Vadot * Set SW1 switch on camera board to 'OFF' as we are using 8bit mode 239*f126890aSEmmanuel Vadot */ 240*f126890aSEmmanuel Vadot status = "okay"; 241*f126890aSEmmanuel Vadot pinctrl-0 = <&vin0_8bit_pins>; 242*f126890aSEmmanuel Vadot pinctrl-names = "default"; 243*f126890aSEmmanuel Vadot 244*f126890aSEmmanuel Vadot port { 245*f126890aSEmmanuel Vadot vin0ep: endpoint { 246*f126890aSEmmanuel Vadot remote-endpoint = <&cam0ep>; 247*f126890aSEmmanuel Vadot bus-width = <8>; 248*f126890aSEmmanuel Vadot bus-type = <MEDIA_BUS_TYPE_BT656>; 249*f126890aSEmmanuel Vadot }; 250*f126890aSEmmanuel Vadot }; 251*f126890aSEmmanuel Vadot}; 252*f126890aSEmmanuel Vadot#endif /* CAM_ENABLED */ 253*f126890aSEmmanuel Vadot 254*f126890aSEmmanuel Vadot#undef CAM_PARENT_I2C 255*f126890aSEmmanuel Vadot#undef MCLK_CAM 256*f126890aSEmmanuel Vadot#undef CAM_EP 257*f126890aSEmmanuel Vadot#undef VIN_EP 258*f126890aSEmmanuel Vadot 259*f126890aSEmmanuel Vadot/* 8bit CMOS Camera 2 (J14) */ 260*f126890aSEmmanuel Vadot#define CAM_PARENT_I2C i2c1 261*f126890aSEmmanuel Vadot#define MCLK_CAM mclk_cam2 262*f126890aSEmmanuel Vadot#define CAM_EP cam1ep 263*f126890aSEmmanuel Vadot#define VIN_EP vin1ep 264*f126890aSEmmanuel Vadot#undef CAM_ENABLED 265*f126890aSEmmanuel Vadot#include "r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi" 266*f126890aSEmmanuel Vadot//#include "r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi" 267*f126890aSEmmanuel Vadot 268*f126890aSEmmanuel Vadot#ifdef CAM_ENABLED 269*f126890aSEmmanuel Vadot&vin1 { 270*f126890aSEmmanuel Vadot /* Set SW1 switch on the SOM to 'ON' */ 271*f126890aSEmmanuel Vadot status = "okay"; 272*f126890aSEmmanuel Vadot pinctrl-0 = <&vin1_8bit_pins>; 273*f126890aSEmmanuel Vadot pinctrl-names = "default"; 274*f126890aSEmmanuel Vadot 275*f126890aSEmmanuel Vadot port { 276*f126890aSEmmanuel Vadot vin1ep: endpoint { 277*f126890aSEmmanuel Vadot remote-endpoint = <&cam1ep>; 278*f126890aSEmmanuel Vadot bus-width = <8>; 279*f126890aSEmmanuel Vadot bus-type = <MEDIA_BUS_TYPE_BT656>; 280*f126890aSEmmanuel Vadot }; 281*f126890aSEmmanuel Vadot }; 282*f126890aSEmmanuel Vadot}; 283*f126890aSEmmanuel Vadot 284*f126890aSEmmanuel Vadot#endif /* CAM_ENABLED */ 285*f126890aSEmmanuel Vadot 286*f126890aSEmmanuel Vadot#undef CAM_PARENT_I2C 287*f126890aSEmmanuel Vadot#undef MCLK_CAM 288*f126890aSEmmanuel Vadot#undef CAM_EP 289*f126890aSEmmanuel Vadot#undef VIN_EP 290*f126890aSEmmanuel Vadot 291*f126890aSEmmanuel Vadot/* 8bit CMOS Camera 3 (J12) */ 292*f126890aSEmmanuel Vadot#define CAM_PARENT_I2C i2c2 293*f126890aSEmmanuel Vadot#define MCLK_CAM mclk_cam3 294*f126890aSEmmanuel Vadot#define CAM_EP cam2ep 295*f126890aSEmmanuel Vadot#define VIN_EP vin2ep 296*f126890aSEmmanuel Vadot#undef CAM_ENABLED 297*f126890aSEmmanuel Vadot#include "r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi" 298*f126890aSEmmanuel Vadot//#include "r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi" 299*f126890aSEmmanuel Vadot 300*f126890aSEmmanuel Vadot#ifdef CAM_ENABLED 301*f126890aSEmmanuel Vadot&vin2 { 302*f126890aSEmmanuel Vadot status = "okay"; 303*f126890aSEmmanuel Vadot pinctrl-0 = <&vin2_pins>; 304*f126890aSEmmanuel Vadot pinctrl-names = "default"; 305*f126890aSEmmanuel Vadot 306*f126890aSEmmanuel Vadot port { 307*f126890aSEmmanuel Vadot vin2ep: endpoint { 308*f126890aSEmmanuel Vadot remote-endpoint = <&cam2ep>; 309*f126890aSEmmanuel Vadot bus-width = <8>; 310*f126890aSEmmanuel Vadot data-shift = <8>; 311*f126890aSEmmanuel Vadot bus-type = <MEDIA_BUS_TYPE_BT656>; 312*f126890aSEmmanuel Vadot }; 313*f126890aSEmmanuel Vadot }; 314*f126890aSEmmanuel Vadot}; 315*f126890aSEmmanuel Vadot#endif /* CAM_ENABLED */ 316*f126890aSEmmanuel Vadot 317*f126890aSEmmanuel Vadot#undef CAM_PARENT_I2C 318*f126890aSEmmanuel Vadot#undef MCLK_CAM 319*f126890aSEmmanuel Vadot#undef CAM_EP 320*f126890aSEmmanuel Vadot#undef VIN_EP 321*f126890aSEmmanuel Vadot 322*f126890aSEmmanuel Vadot/* 8bit CMOS Camera 4 (J11) */ 323*f126890aSEmmanuel Vadot#define CAM_PARENT_I2C i2c3 324*f126890aSEmmanuel Vadot#define MCLK_CAM mclk_cam4 325*f126890aSEmmanuel Vadot#define CAM_EP cam3ep 326*f126890aSEmmanuel Vadot#define VIN_EP vin3ep 327*f126890aSEmmanuel Vadot#undef CAM_ENABLED 328*f126890aSEmmanuel Vadot#include "r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi" 329*f126890aSEmmanuel Vadot//#include "r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi" 330*f126890aSEmmanuel Vadot 331*f126890aSEmmanuel Vadot#ifdef CAM_ENABLED 332*f126890aSEmmanuel Vadot&vin3 { 333*f126890aSEmmanuel Vadot status = "okay"; 334*f126890aSEmmanuel Vadot pinctrl-0 = <&vin3_pins>; 335*f126890aSEmmanuel Vadot pinctrl-names = "default"; 336*f126890aSEmmanuel Vadot 337*f126890aSEmmanuel Vadot port { 338*f126890aSEmmanuel Vadot vin3ep: endpoint { 339*f126890aSEmmanuel Vadot remote-endpoint = <&cam3ep>; 340*f126890aSEmmanuel Vadot bus-width = <8>; 341*f126890aSEmmanuel Vadot bus-type = <MEDIA_BUS_TYPE_BT656>; 342*f126890aSEmmanuel Vadot }; 343*f126890aSEmmanuel Vadot }; 344*f126890aSEmmanuel Vadot}; 345*f126890aSEmmanuel Vadot#endif /* CAM_ENABLED */ 346*f126890aSEmmanuel Vadot 347*f126890aSEmmanuel Vadot#undef CAM_PARENT_I2C 348*f126890aSEmmanuel Vadot#undef MCLK_CAM 349*f126890aSEmmanuel Vadot#undef CAM_EP 350*f126890aSEmmanuel Vadot#undef VIN_EP 351