1f126890aSEmmanuel Vadot// SPDX-License-Identifier: GPL-2.0+ 2f126890aSEmmanuel Vadot/* 3f126890aSEmmanuel Vadot * (C) Copyright 2017 Rockchip Electronics Co., Ltd 4f126890aSEmmanuel Vadot */ 5f126890aSEmmanuel Vadot 6f126890aSEmmanuel Vadot#include <dt-bindings/clock/rk3128-cru.h> 7f126890aSEmmanuel Vadot#include <dt-bindings/gpio/gpio.h> 8f126890aSEmmanuel Vadot#include <dt-bindings/interrupt-controller/arm-gic.h> 9f126890aSEmmanuel Vadot#include <dt-bindings/interrupt-controller/irq.h> 10f126890aSEmmanuel Vadot#include <dt-bindings/pinctrl/rockchip.h> 11*8d13bc63SEmmanuel Vadot#include <dt-bindings/power/rk3128-power.h> 12f126890aSEmmanuel Vadot 13f126890aSEmmanuel Vadot/ { 14f126890aSEmmanuel Vadot compatible = "rockchip,rk3128"; 15f126890aSEmmanuel Vadot interrupt-parent = <&gic>; 16f126890aSEmmanuel Vadot #address-cells = <1>; 17f126890aSEmmanuel Vadot #size-cells = <1>; 18f126890aSEmmanuel Vadot 19*8d13bc63SEmmanuel Vadot aliases { 20*8d13bc63SEmmanuel Vadot gpio0 = &gpio0; 21*8d13bc63SEmmanuel Vadot gpio1 = &gpio1; 22*8d13bc63SEmmanuel Vadot gpio2 = &gpio2; 23*8d13bc63SEmmanuel Vadot gpio3 = &gpio3; 24*8d13bc63SEmmanuel Vadot i2c0 = &i2c0; 25*8d13bc63SEmmanuel Vadot i2c1 = &i2c1; 26*8d13bc63SEmmanuel Vadot i2c2 = &i2c2; 27*8d13bc63SEmmanuel Vadot i2c3 = &i2c3; 28*8d13bc63SEmmanuel Vadot serial0 = &uart0; 29*8d13bc63SEmmanuel Vadot serial1 = &uart1; 30*8d13bc63SEmmanuel Vadot serial2 = &uart2; 31*8d13bc63SEmmanuel Vadot }; 32*8d13bc63SEmmanuel Vadot 33f126890aSEmmanuel Vadot arm-pmu { 34f126890aSEmmanuel Vadot compatible = "arm,cortex-a7-pmu"; 35f126890aSEmmanuel Vadot interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 36f126890aSEmmanuel Vadot <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 37f126890aSEmmanuel Vadot <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 38f126890aSEmmanuel Vadot <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 39f126890aSEmmanuel Vadot interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 40f126890aSEmmanuel Vadot }; 41f126890aSEmmanuel Vadot 42f126890aSEmmanuel Vadot cpus { 43f126890aSEmmanuel Vadot #address-cells = <1>; 44f126890aSEmmanuel Vadot #size-cells = <0>; 4584943d6fSEmmanuel Vadot enable-method = "rockchip,rk3036-smp"; 46f126890aSEmmanuel Vadot 47f126890aSEmmanuel Vadot cpu0: cpu@f00 { 48f126890aSEmmanuel Vadot device_type = "cpu"; 49f126890aSEmmanuel Vadot compatible = "arm,cortex-a7"; 50f126890aSEmmanuel Vadot reg = <0xf00>; 51f126890aSEmmanuel Vadot clock-latency = <40000>; 52f126890aSEmmanuel Vadot clocks = <&cru ARMCLK>; 5384943d6fSEmmanuel Vadot resets = <&cru SRST_CORE0>; 5484943d6fSEmmanuel Vadot operating-points-v2 = <&cpu_opp_table>; 55f126890aSEmmanuel Vadot #cooling-cells = <2>; /* min followed by max */ 56f126890aSEmmanuel Vadot }; 57f126890aSEmmanuel Vadot 58f126890aSEmmanuel Vadot cpu1: cpu@f01 { 59f126890aSEmmanuel Vadot device_type = "cpu"; 60f126890aSEmmanuel Vadot compatible = "arm,cortex-a7"; 61f126890aSEmmanuel Vadot reg = <0xf01>; 6284943d6fSEmmanuel Vadot resets = <&cru SRST_CORE1>; 6384943d6fSEmmanuel Vadot operating-points-v2 = <&cpu_opp_table>; 64f126890aSEmmanuel Vadot }; 65f126890aSEmmanuel Vadot 66f126890aSEmmanuel Vadot cpu2: cpu@f02 { 67f126890aSEmmanuel Vadot device_type = "cpu"; 68f126890aSEmmanuel Vadot compatible = "arm,cortex-a7"; 69f126890aSEmmanuel Vadot reg = <0xf02>; 7084943d6fSEmmanuel Vadot resets = <&cru SRST_CORE2>; 7184943d6fSEmmanuel Vadot operating-points-v2 = <&cpu_opp_table>; 72f126890aSEmmanuel Vadot }; 73f126890aSEmmanuel Vadot 74f126890aSEmmanuel Vadot cpu3: cpu@f03 { 75f126890aSEmmanuel Vadot device_type = "cpu"; 76f126890aSEmmanuel Vadot compatible = "arm,cortex-a7"; 77f126890aSEmmanuel Vadot reg = <0xf03>; 7884943d6fSEmmanuel Vadot resets = <&cru SRST_CORE3>; 7984943d6fSEmmanuel Vadot operating-points-v2 = <&cpu_opp_table>; 8084943d6fSEmmanuel Vadot }; 8184943d6fSEmmanuel Vadot }; 8284943d6fSEmmanuel Vadot 8384943d6fSEmmanuel Vadot cpu_opp_table: opp-table-0 { 8484943d6fSEmmanuel Vadot compatible = "operating-points-v2"; 8584943d6fSEmmanuel Vadot opp-shared; 8684943d6fSEmmanuel Vadot 8784943d6fSEmmanuel Vadot opp-216000000 { 8884943d6fSEmmanuel Vadot opp-hz = /bits/ 64 <216000000>; 8984943d6fSEmmanuel Vadot opp-microvolt = <950000 950000 1325000>; 9084943d6fSEmmanuel Vadot }; 9184943d6fSEmmanuel Vadot opp-408000000 { 9284943d6fSEmmanuel Vadot opp-hz = /bits/ 64 <408000000>; 9384943d6fSEmmanuel Vadot opp-microvolt = <950000 950000 1325000>; 9484943d6fSEmmanuel Vadot }; 9584943d6fSEmmanuel Vadot opp-600000000 { 9684943d6fSEmmanuel Vadot opp-hz = /bits/ 64 <600000000>; 9784943d6fSEmmanuel Vadot opp-microvolt = <950000 950000 1325000>; 9884943d6fSEmmanuel Vadot }; 9984943d6fSEmmanuel Vadot opp-696000000 { 10084943d6fSEmmanuel Vadot opp-hz = /bits/ 64 <696000000>; 10184943d6fSEmmanuel Vadot opp-microvolt = <975000 975000 1325000>; 10284943d6fSEmmanuel Vadot }; 10384943d6fSEmmanuel Vadot opp-816000000 { 10484943d6fSEmmanuel Vadot opp-hz = /bits/ 64 <816000000>; 10584943d6fSEmmanuel Vadot opp-microvolt = <1075000 1075000 1325000>; 10684943d6fSEmmanuel Vadot opp-suspend; 10784943d6fSEmmanuel Vadot }; 10884943d6fSEmmanuel Vadot opp-1008000000 { 10984943d6fSEmmanuel Vadot opp-hz = /bits/ 64 <1008000000>; 11084943d6fSEmmanuel Vadot opp-microvolt = <1200000 1200000 1325000>; 11184943d6fSEmmanuel Vadot }; 11284943d6fSEmmanuel Vadot opp-1200000000 { 11384943d6fSEmmanuel Vadot opp-hz = /bits/ 64 <1200000000>; 11484943d6fSEmmanuel Vadot opp-microvolt = <1325000 1325000 1325000>; 115f126890aSEmmanuel Vadot }; 116f126890aSEmmanuel Vadot }; 117f126890aSEmmanuel Vadot 118*8d13bc63SEmmanuel Vadot gpu_opp_table: opp-table-1 { 119*8d13bc63SEmmanuel Vadot compatible = "operating-points-v2"; 120*8d13bc63SEmmanuel Vadot 121*8d13bc63SEmmanuel Vadot opp-200000000 { 122*8d13bc63SEmmanuel Vadot opp-hz = /bits/ 64 <200000000>; 123*8d13bc63SEmmanuel Vadot opp-microvolt = <975000 975000 1250000>; 124*8d13bc63SEmmanuel Vadot }; 125*8d13bc63SEmmanuel Vadot opp-300000000 { 126*8d13bc63SEmmanuel Vadot opp-hz = /bits/ 64 <300000000>; 127*8d13bc63SEmmanuel Vadot opp-microvolt = <1050000 1050000 1250000>; 128*8d13bc63SEmmanuel Vadot }; 129*8d13bc63SEmmanuel Vadot opp-400000000 { 130*8d13bc63SEmmanuel Vadot opp-hz = /bits/ 64 <400000000>; 131*8d13bc63SEmmanuel Vadot opp-microvolt = <1150000 1150000 1250000>; 132*8d13bc63SEmmanuel Vadot }; 133*8d13bc63SEmmanuel Vadot opp-480000000 { 134*8d13bc63SEmmanuel Vadot opp-hz = /bits/ 64 <480000000>; 135*8d13bc63SEmmanuel Vadot opp-microvolt = <1250000 1250000 1250000>; 136*8d13bc63SEmmanuel Vadot }; 137*8d13bc63SEmmanuel Vadot }; 138*8d13bc63SEmmanuel Vadot 139f126890aSEmmanuel Vadot timer { 140f126890aSEmmanuel Vadot compatible = "arm,armv7-timer"; 141f126890aSEmmanuel Vadot interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 142f126890aSEmmanuel Vadot <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 143aa1a8ff2SEmmanuel Vadot <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 144aa1a8ff2SEmmanuel Vadot <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 145f126890aSEmmanuel Vadot arm,cpu-registers-not-fw-configured; 146f126890aSEmmanuel Vadot clock-frequency = <24000000>; 147f126890aSEmmanuel Vadot }; 148f126890aSEmmanuel Vadot 149f126890aSEmmanuel Vadot xin24m: oscillator { 150f126890aSEmmanuel Vadot compatible = "fixed-clock"; 151f126890aSEmmanuel Vadot clock-frequency = <24000000>; 152f126890aSEmmanuel Vadot clock-output-names = "xin24m"; 153f126890aSEmmanuel Vadot #clock-cells = <0>; 154f126890aSEmmanuel Vadot }; 155f126890aSEmmanuel Vadot 15684943d6fSEmmanuel Vadot imem: sram@10080000 { 15784943d6fSEmmanuel Vadot compatible = "mmio-sram"; 15884943d6fSEmmanuel Vadot reg = <0x10080000 0x2000>; 15984943d6fSEmmanuel Vadot #address-cells = <1>; 16084943d6fSEmmanuel Vadot #size-cells = <1>; 16184943d6fSEmmanuel Vadot ranges = <0 0x10080000 0x2000>; 16284943d6fSEmmanuel Vadot 16384943d6fSEmmanuel Vadot smp-sram@0 { 16484943d6fSEmmanuel Vadot compatible = "rockchip,rk3066-smp-sram"; 16584943d6fSEmmanuel Vadot reg = <0x00 0x10>; 16684943d6fSEmmanuel Vadot }; 16784943d6fSEmmanuel Vadot }; 16884943d6fSEmmanuel Vadot 169*8d13bc63SEmmanuel Vadot gpu: gpu@10090000 { 170*8d13bc63SEmmanuel Vadot compatible = "rockchip,rk3128-mali", "arm,mali-400"; 171*8d13bc63SEmmanuel Vadot reg = <0x10090000 0x10000>; 172*8d13bc63SEmmanuel Vadot interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 173*8d13bc63SEmmanuel Vadot <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 174*8d13bc63SEmmanuel Vadot <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 175*8d13bc63SEmmanuel Vadot <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 176*8d13bc63SEmmanuel Vadot <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 177*8d13bc63SEmmanuel Vadot <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 178*8d13bc63SEmmanuel Vadot interrupt-names = "gp", 179*8d13bc63SEmmanuel Vadot "gpmmu", 180*8d13bc63SEmmanuel Vadot "pp0", 181*8d13bc63SEmmanuel Vadot "ppmmu0", 182*8d13bc63SEmmanuel Vadot "pp1", 183*8d13bc63SEmmanuel Vadot "ppmmu1"; 184*8d13bc63SEmmanuel Vadot clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 185*8d13bc63SEmmanuel Vadot clock-names = "bus", "core"; 186*8d13bc63SEmmanuel Vadot operating-points-v2 = <&gpu_opp_table>; 187*8d13bc63SEmmanuel Vadot resets = <&cru SRST_GPU>; 188*8d13bc63SEmmanuel Vadot power-domains = <&power RK3128_PD_GPU>; 189*8d13bc63SEmmanuel Vadot status = "disabled"; 190*8d13bc63SEmmanuel Vadot }; 191*8d13bc63SEmmanuel Vadot 192f126890aSEmmanuel Vadot pmu: syscon@100a0000 { 193f126890aSEmmanuel Vadot compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; 194f126890aSEmmanuel Vadot reg = <0x100a0000 0x1000>; 195*8d13bc63SEmmanuel Vadot 196*8d13bc63SEmmanuel Vadot power: power-controller { 197*8d13bc63SEmmanuel Vadot compatible = "rockchip,rk3128-power-controller"; 198*8d13bc63SEmmanuel Vadot #power-domain-cells = <1>; 199*8d13bc63SEmmanuel Vadot #address-cells = <1>; 200*8d13bc63SEmmanuel Vadot #size-cells = <0>; 201*8d13bc63SEmmanuel Vadot 202*8d13bc63SEmmanuel Vadot power-domain@RK3128_PD_VIO { 203*8d13bc63SEmmanuel Vadot reg = <RK3128_PD_VIO>; 204*8d13bc63SEmmanuel Vadot clocks = <&cru ACLK_CIF>, 205*8d13bc63SEmmanuel Vadot <&cru HCLK_CIF>, 206*8d13bc63SEmmanuel Vadot <&cru DCLK_EBC>, 207*8d13bc63SEmmanuel Vadot <&cru HCLK_EBC>, 208*8d13bc63SEmmanuel Vadot <&cru ACLK_IEP>, 209*8d13bc63SEmmanuel Vadot <&cru HCLK_IEP>, 210*8d13bc63SEmmanuel Vadot <&cru ACLK_LCDC0>, 211*8d13bc63SEmmanuel Vadot <&cru HCLK_LCDC0>, 212*8d13bc63SEmmanuel Vadot <&cru PCLK_MIPI>, 213*8d13bc63SEmmanuel Vadot <&cru ACLK_RGA>, 214*8d13bc63SEmmanuel Vadot <&cru HCLK_RGA>, 215*8d13bc63SEmmanuel Vadot <&cru ACLK_VIO0>, 216*8d13bc63SEmmanuel Vadot <&cru ACLK_VIO1>, 217*8d13bc63SEmmanuel Vadot <&cru HCLK_VIO>, 218*8d13bc63SEmmanuel Vadot <&cru HCLK_VIO_H2P>, 219*8d13bc63SEmmanuel Vadot <&cru DCLK_VOP>, 220*8d13bc63SEmmanuel Vadot <&cru SCLK_VOP>; 221*8d13bc63SEmmanuel Vadot pm_qos = <&qos_ebc>, 222*8d13bc63SEmmanuel Vadot <&qos_iep>, 223*8d13bc63SEmmanuel Vadot <&qos_lcdc>, 224*8d13bc63SEmmanuel Vadot <&qos_rga>, 225*8d13bc63SEmmanuel Vadot <&qos_vip>; 226*8d13bc63SEmmanuel Vadot #power-domain-cells = <0>; 227*8d13bc63SEmmanuel Vadot }; 228*8d13bc63SEmmanuel Vadot 229*8d13bc63SEmmanuel Vadot power-domain@RK3128_PD_VIDEO { 230*8d13bc63SEmmanuel Vadot reg = <RK3128_PD_VIDEO>; 231*8d13bc63SEmmanuel Vadot clocks = <&cru ACLK_VDPU>, 232*8d13bc63SEmmanuel Vadot <&cru HCLK_VDPU>, 233*8d13bc63SEmmanuel Vadot <&cru ACLK_VEPU>, 234*8d13bc63SEmmanuel Vadot <&cru HCLK_VEPU>, 235*8d13bc63SEmmanuel Vadot <&cru SCLK_HEVC_CORE>; 236*8d13bc63SEmmanuel Vadot pm_qos = <&qos_vpu>; 237*8d13bc63SEmmanuel Vadot #power-domain-cells = <0>; 238*8d13bc63SEmmanuel Vadot }; 239*8d13bc63SEmmanuel Vadot 240*8d13bc63SEmmanuel Vadot power-domain@RK3128_PD_GPU { 241*8d13bc63SEmmanuel Vadot reg = <RK3128_PD_GPU>; 242*8d13bc63SEmmanuel Vadot clocks = <&cru ACLK_GPU>; 243*8d13bc63SEmmanuel Vadot pm_qos = <&qos_gpu>; 244*8d13bc63SEmmanuel Vadot #power-domain-cells = <0>; 245*8d13bc63SEmmanuel Vadot }; 246*8d13bc63SEmmanuel Vadot }; 247*8d13bc63SEmmanuel Vadot }; 248*8d13bc63SEmmanuel Vadot 249*8d13bc63SEmmanuel Vadot qos_gpu: qos@1012d000 { 250*8d13bc63SEmmanuel Vadot compatible = "rockchip,rk3128-qos", "syscon"; 251*8d13bc63SEmmanuel Vadot reg = <0x1012d000 0x20>; 252*8d13bc63SEmmanuel Vadot }; 253*8d13bc63SEmmanuel Vadot 254*8d13bc63SEmmanuel Vadot qos_vpu: qos@1012e000 { 255*8d13bc63SEmmanuel Vadot compatible = "rockchip,rk3128-qos", "syscon"; 256*8d13bc63SEmmanuel Vadot reg = <0x1012e000 0x20>; 257*8d13bc63SEmmanuel Vadot }; 258*8d13bc63SEmmanuel Vadot 259*8d13bc63SEmmanuel Vadot qos_rga: qos@1012f000 { 260*8d13bc63SEmmanuel Vadot compatible = "rockchip,rk3128-qos", "syscon"; 261*8d13bc63SEmmanuel Vadot reg = <0x1012f000 0x20>; 262*8d13bc63SEmmanuel Vadot }; 263*8d13bc63SEmmanuel Vadot 264*8d13bc63SEmmanuel Vadot qos_ebc: qos@1012f080 { 265*8d13bc63SEmmanuel Vadot compatible = "rockchip,rk3128-qos", "syscon"; 266*8d13bc63SEmmanuel Vadot reg = <0x1012f080 0x20>; 267*8d13bc63SEmmanuel Vadot }; 268*8d13bc63SEmmanuel Vadot 269*8d13bc63SEmmanuel Vadot qos_iep: qos@1012f100 { 270*8d13bc63SEmmanuel Vadot compatible = "rockchip,rk3128-qos", "syscon"; 271*8d13bc63SEmmanuel Vadot reg = <0x1012f100 0x20>; 272*8d13bc63SEmmanuel Vadot }; 273*8d13bc63SEmmanuel Vadot 274*8d13bc63SEmmanuel Vadot qos_lcdc: qos@1012f180 { 275*8d13bc63SEmmanuel Vadot compatible = "rockchip,rk3128-qos", "syscon"; 276*8d13bc63SEmmanuel Vadot reg = <0x1012f180 0x20>; 277*8d13bc63SEmmanuel Vadot }; 278*8d13bc63SEmmanuel Vadot 279*8d13bc63SEmmanuel Vadot qos_vip: qos@1012f200 { 280*8d13bc63SEmmanuel Vadot compatible = "rockchip,rk3128-qos", "syscon"; 281*8d13bc63SEmmanuel Vadot reg = <0x1012f200 0x20>; 282f126890aSEmmanuel Vadot }; 283f126890aSEmmanuel Vadot 284f126890aSEmmanuel Vadot gic: interrupt-controller@10139000 { 285f126890aSEmmanuel Vadot compatible = "arm,cortex-a7-gic"; 286f126890aSEmmanuel Vadot reg = <0x10139000 0x1000>, 287f126890aSEmmanuel Vadot <0x1013a000 0x1000>, 288f126890aSEmmanuel Vadot <0x1013c000 0x2000>, 289f126890aSEmmanuel Vadot <0x1013e000 0x2000>; 290f126890aSEmmanuel Vadot interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 291f126890aSEmmanuel Vadot interrupt-controller; 292f126890aSEmmanuel Vadot #interrupt-cells = <3>; 293f126890aSEmmanuel Vadot #address-cells = <0>; 294f126890aSEmmanuel Vadot }; 295f126890aSEmmanuel Vadot 296f126890aSEmmanuel Vadot usb_otg: usb@10180000 { 297f126890aSEmmanuel Vadot compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2"; 298f126890aSEmmanuel Vadot reg = <0x10180000 0x40000>; 299f126890aSEmmanuel Vadot interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 300f126890aSEmmanuel Vadot clocks = <&cru HCLK_OTG>; 301f126890aSEmmanuel Vadot clock-names = "otg"; 302f126890aSEmmanuel Vadot dr_mode = "otg"; 303*8d13bc63SEmmanuel Vadot g-np-tx-fifo-size = <16>; 304*8d13bc63SEmmanuel Vadot g-rx-fifo-size = <280>; 305*8d13bc63SEmmanuel Vadot g-tx-fifo-size = <256 128 128 64 32 16>; 306f126890aSEmmanuel Vadot phys = <&usb2phy_otg>; 307f126890aSEmmanuel Vadot phy-names = "usb2-phy"; 308f126890aSEmmanuel Vadot status = "disabled"; 309f126890aSEmmanuel Vadot }; 310f126890aSEmmanuel Vadot 311f126890aSEmmanuel Vadot usb_host_ehci: usb@101c0000 { 312f126890aSEmmanuel Vadot compatible = "generic-ehci"; 313f126890aSEmmanuel Vadot reg = <0x101c0000 0x20000>; 314f126890aSEmmanuel Vadot interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 315*8d13bc63SEmmanuel Vadot clocks = <&cru HCLK_HOST2>; 316f126890aSEmmanuel Vadot phys = <&usb2phy_host>; 317f126890aSEmmanuel Vadot phy-names = "usb"; 318f126890aSEmmanuel Vadot status = "disabled"; 319f126890aSEmmanuel Vadot }; 320f126890aSEmmanuel Vadot 321f126890aSEmmanuel Vadot usb_host_ohci: usb@101e0000 { 322f126890aSEmmanuel Vadot compatible = "generic-ohci"; 323f126890aSEmmanuel Vadot reg = <0x101e0000 0x20000>; 324f126890aSEmmanuel Vadot interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 325*8d13bc63SEmmanuel Vadot clocks = <&cru HCLK_HOST2>; 326f126890aSEmmanuel Vadot phys = <&usb2phy_host>; 327f126890aSEmmanuel Vadot phy-names = "usb"; 328f126890aSEmmanuel Vadot status = "disabled"; 329f126890aSEmmanuel Vadot }; 330f126890aSEmmanuel Vadot 331f126890aSEmmanuel Vadot sdmmc: mmc@10214000 { 332f126890aSEmmanuel Vadot compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 333f126890aSEmmanuel Vadot reg = <0x10214000 0x4000>; 334f126890aSEmmanuel Vadot interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 335f126890aSEmmanuel Vadot clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 336f126890aSEmmanuel Vadot <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 337f126890aSEmmanuel Vadot clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 338f126890aSEmmanuel Vadot dmas = <&pdma 10>; 339f126890aSEmmanuel Vadot dma-names = "rx-tx"; 340f126890aSEmmanuel Vadot fifo-depth = <256>; 341f126890aSEmmanuel Vadot max-frequency = <150000000>; 342f126890aSEmmanuel Vadot resets = <&cru SRST_SDMMC>; 343f126890aSEmmanuel Vadot reset-names = "reset"; 344f126890aSEmmanuel Vadot status = "disabled"; 345f126890aSEmmanuel Vadot }; 346f126890aSEmmanuel Vadot 347f126890aSEmmanuel Vadot sdio: mmc@10218000 { 348f126890aSEmmanuel Vadot compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 349f126890aSEmmanuel Vadot reg = <0x10218000 0x4000>; 350f126890aSEmmanuel Vadot interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 351f126890aSEmmanuel Vadot clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 352f126890aSEmmanuel Vadot <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 353f126890aSEmmanuel Vadot clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 354f126890aSEmmanuel Vadot dmas = <&pdma 11>; 355f126890aSEmmanuel Vadot dma-names = "rx-tx"; 356f126890aSEmmanuel Vadot fifo-depth = <256>; 357f126890aSEmmanuel Vadot max-frequency = <150000000>; 358f126890aSEmmanuel Vadot resets = <&cru SRST_SDIO>; 359f126890aSEmmanuel Vadot reset-names = "reset"; 360f126890aSEmmanuel Vadot status = "disabled"; 361f126890aSEmmanuel Vadot }; 362f126890aSEmmanuel Vadot 363f126890aSEmmanuel Vadot emmc: mmc@1021c000 { 364f126890aSEmmanuel Vadot compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 365f126890aSEmmanuel Vadot reg = <0x1021c000 0x4000>; 366f126890aSEmmanuel Vadot interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 367f126890aSEmmanuel Vadot clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 368f126890aSEmmanuel Vadot <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 369f126890aSEmmanuel Vadot clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 370f126890aSEmmanuel Vadot dmas = <&pdma 12>; 371f126890aSEmmanuel Vadot dma-names = "rx-tx"; 372f126890aSEmmanuel Vadot fifo-depth = <256>; 373f126890aSEmmanuel Vadot max-frequency = <150000000>; 374f126890aSEmmanuel Vadot resets = <&cru SRST_EMMC>; 375f126890aSEmmanuel Vadot reset-names = "reset"; 376f126890aSEmmanuel Vadot status = "disabled"; 377f126890aSEmmanuel Vadot }; 378f126890aSEmmanuel Vadot 379f126890aSEmmanuel Vadot nfc: nand-controller@10500000 { 380f126890aSEmmanuel Vadot compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc"; 381f126890aSEmmanuel Vadot reg = <0x10500000 0x4000>; 382f126890aSEmmanuel Vadot interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 383f126890aSEmmanuel Vadot clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; 384f126890aSEmmanuel Vadot clock-names = "ahb", "nfc"; 385f126890aSEmmanuel Vadot pinctrl-names = "default"; 386f126890aSEmmanuel Vadot pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0 387f126890aSEmmanuel Vadot &flash_dqs &flash_rdn &flash_rdy &flash_wrn>; 388f126890aSEmmanuel Vadot status = "disabled"; 389f126890aSEmmanuel Vadot }; 390f126890aSEmmanuel Vadot 391f126890aSEmmanuel Vadot cru: clock-controller@20000000 { 392f126890aSEmmanuel Vadot compatible = "rockchip,rk3128-cru"; 393f126890aSEmmanuel Vadot reg = <0x20000000 0x1000>; 394f126890aSEmmanuel Vadot clocks = <&xin24m>; 395f126890aSEmmanuel Vadot clock-names = "xin24m"; 396f126890aSEmmanuel Vadot rockchip,grf = <&grf>; 397f126890aSEmmanuel Vadot #clock-cells = <1>; 398f126890aSEmmanuel Vadot #reset-cells = <1>; 399f126890aSEmmanuel Vadot assigned-clocks = <&cru PLL_GPLL>; 400f126890aSEmmanuel Vadot assigned-clock-rates = <594000000>; 401f126890aSEmmanuel Vadot }; 402f126890aSEmmanuel Vadot 403f126890aSEmmanuel Vadot grf: syscon@20008000 { 404f126890aSEmmanuel Vadot compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd"; 405f126890aSEmmanuel Vadot reg = <0x20008000 0x1000>; 406f126890aSEmmanuel Vadot #address-cells = <1>; 407f126890aSEmmanuel Vadot #size-cells = <1>; 408f126890aSEmmanuel Vadot 409f126890aSEmmanuel Vadot usb2phy: usb2phy@17c { 410f126890aSEmmanuel Vadot compatible = "rockchip,rk3128-usb2phy"; 411f126890aSEmmanuel Vadot reg = <0x017c 0x0c>; 412f126890aSEmmanuel Vadot clocks = <&cru SCLK_OTGPHY0>; 413f126890aSEmmanuel Vadot clock-names = "phyclk"; 414f126890aSEmmanuel Vadot clock-output-names = "usb480m_phy"; 415*8d13bc63SEmmanuel Vadot assigned-clocks = <&cru SCLK_USB480M>; 416*8d13bc63SEmmanuel Vadot assigned-clock-parents = <&usb2phy>; 417f126890aSEmmanuel Vadot #clock-cells = <0>; 418f126890aSEmmanuel Vadot status = "disabled"; 419f126890aSEmmanuel Vadot 420f126890aSEmmanuel Vadot usb2phy_host: host-port { 421f126890aSEmmanuel Vadot interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 422f126890aSEmmanuel Vadot interrupt-names = "linestate"; 423f126890aSEmmanuel Vadot #phy-cells = <0>; 424f126890aSEmmanuel Vadot status = "disabled"; 425f126890aSEmmanuel Vadot }; 426f126890aSEmmanuel Vadot 427f126890aSEmmanuel Vadot usb2phy_otg: otg-port { 428f126890aSEmmanuel Vadot interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 429f126890aSEmmanuel Vadot <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 430f126890aSEmmanuel Vadot <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 431f126890aSEmmanuel Vadot interrupt-names = "otg-bvalid", "otg-id", 432f126890aSEmmanuel Vadot "linestate"; 433f126890aSEmmanuel Vadot #phy-cells = <0>; 434f126890aSEmmanuel Vadot status = "disabled"; 435f126890aSEmmanuel Vadot }; 436f126890aSEmmanuel Vadot }; 437f126890aSEmmanuel Vadot }; 438f126890aSEmmanuel Vadot 439f126890aSEmmanuel Vadot timer0: timer@20044000 { 440f126890aSEmmanuel Vadot compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 441f126890aSEmmanuel Vadot reg = <0x20044000 0x20>; 442f126890aSEmmanuel Vadot interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 443aa1a8ff2SEmmanuel Vadot clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 444f126890aSEmmanuel Vadot clock-names = "pclk", "timer"; 445f126890aSEmmanuel Vadot }; 446f126890aSEmmanuel Vadot 447f126890aSEmmanuel Vadot timer1: timer@20044020 { 448f126890aSEmmanuel Vadot compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 449f126890aSEmmanuel Vadot reg = <0x20044020 0x20>; 450f126890aSEmmanuel Vadot interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 451aa1a8ff2SEmmanuel Vadot clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER1>; 452f126890aSEmmanuel Vadot clock-names = "pclk", "timer"; 453f126890aSEmmanuel Vadot }; 454f126890aSEmmanuel Vadot 455f126890aSEmmanuel Vadot timer2: timer@20044040 { 456f126890aSEmmanuel Vadot compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 457f126890aSEmmanuel Vadot reg = <0x20044040 0x20>; 458f126890aSEmmanuel Vadot interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 459aa1a8ff2SEmmanuel Vadot clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER2>; 460f126890aSEmmanuel Vadot clock-names = "pclk", "timer"; 461f126890aSEmmanuel Vadot }; 462f126890aSEmmanuel Vadot 463f126890aSEmmanuel Vadot timer3: timer@20044060 { 464f126890aSEmmanuel Vadot compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 465f126890aSEmmanuel Vadot reg = <0x20044060 0x20>; 466f126890aSEmmanuel Vadot interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 467aa1a8ff2SEmmanuel Vadot clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER3>; 468f126890aSEmmanuel Vadot clock-names = "pclk", "timer"; 469f126890aSEmmanuel Vadot }; 470f126890aSEmmanuel Vadot 471f126890aSEmmanuel Vadot timer4: timer@20044080 { 472f126890aSEmmanuel Vadot compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 473f126890aSEmmanuel Vadot reg = <0x20044080 0x20>; 474f126890aSEmmanuel Vadot interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 475aa1a8ff2SEmmanuel Vadot clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER4>; 476f126890aSEmmanuel Vadot clock-names = "pclk", "timer"; 477f126890aSEmmanuel Vadot }; 478f126890aSEmmanuel Vadot 479f126890aSEmmanuel Vadot timer5: timer@200440a0 { 480f126890aSEmmanuel Vadot compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 481f126890aSEmmanuel Vadot reg = <0x200440a0 0x20>; 482f126890aSEmmanuel Vadot interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 483aa1a8ff2SEmmanuel Vadot clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER5>; 484f126890aSEmmanuel Vadot clock-names = "pclk", "timer"; 485f126890aSEmmanuel Vadot }; 486f126890aSEmmanuel Vadot 487f126890aSEmmanuel Vadot watchdog: watchdog@2004c000 { 488f126890aSEmmanuel Vadot compatible = "rockchip,rk3128-wdt", "snps,dw-wdt"; 489f126890aSEmmanuel Vadot reg = <0x2004c000 0x100>; 490f126890aSEmmanuel Vadot interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 491f126890aSEmmanuel Vadot clocks = <&cru PCLK_WDT>; 492f126890aSEmmanuel Vadot status = "disabled"; 493f126890aSEmmanuel Vadot }; 494f126890aSEmmanuel Vadot 495f126890aSEmmanuel Vadot pwm0: pwm@20050000 { 496f126890aSEmmanuel Vadot compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 497f126890aSEmmanuel Vadot reg = <0x20050000 0x10>; 498f126890aSEmmanuel Vadot clocks = <&cru PCLK_PWM>; 499f126890aSEmmanuel Vadot pinctrl-names = "default"; 500f126890aSEmmanuel Vadot pinctrl-0 = <&pwm0_pin>; 501f126890aSEmmanuel Vadot #pwm-cells = <3>; 502f126890aSEmmanuel Vadot status = "disabled"; 503f126890aSEmmanuel Vadot }; 504f126890aSEmmanuel Vadot 505f126890aSEmmanuel Vadot pwm1: pwm@20050010 { 506f126890aSEmmanuel Vadot compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 507f126890aSEmmanuel Vadot reg = <0x20050010 0x10>; 508f126890aSEmmanuel Vadot clocks = <&cru PCLK_PWM>; 509f126890aSEmmanuel Vadot pinctrl-names = "default"; 510f126890aSEmmanuel Vadot pinctrl-0 = <&pwm1_pin>; 511f126890aSEmmanuel Vadot #pwm-cells = <3>; 512f126890aSEmmanuel Vadot status = "disabled"; 513f126890aSEmmanuel Vadot }; 514f126890aSEmmanuel Vadot 515f126890aSEmmanuel Vadot pwm2: pwm@20050020 { 516f126890aSEmmanuel Vadot compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 517f126890aSEmmanuel Vadot reg = <0x20050020 0x10>; 518f126890aSEmmanuel Vadot clocks = <&cru PCLK_PWM>; 519f126890aSEmmanuel Vadot pinctrl-names = "default"; 520f126890aSEmmanuel Vadot pinctrl-0 = <&pwm2_pin>; 521f126890aSEmmanuel Vadot #pwm-cells = <3>; 522f126890aSEmmanuel Vadot status = "disabled"; 523f126890aSEmmanuel Vadot }; 524f126890aSEmmanuel Vadot 525f126890aSEmmanuel Vadot pwm3: pwm@20050030 { 526f126890aSEmmanuel Vadot compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 527f126890aSEmmanuel Vadot reg = <0x20050030 0x10>; 528f126890aSEmmanuel Vadot clocks = <&cru PCLK_PWM>; 529f126890aSEmmanuel Vadot pinctrl-names = "default"; 530f126890aSEmmanuel Vadot pinctrl-0 = <&pwm3_pin>; 531f126890aSEmmanuel Vadot #pwm-cells = <3>; 532f126890aSEmmanuel Vadot status = "disabled"; 533f126890aSEmmanuel Vadot }; 534f126890aSEmmanuel Vadot 535f126890aSEmmanuel Vadot i2c1: i2c@20056000 { 536f126890aSEmmanuel Vadot compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 537f126890aSEmmanuel Vadot reg = <0x20056000 0x1000>; 538f126890aSEmmanuel Vadot interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 539f126890aSEmmanuel Vadot clock-names = "i2c"; 540f126890aSEmmanuel Vadot clocks = <&cru PCLK_I2C1>; 541f126890aSEmmanuel Vadot pinctrl-names = "default"; 542f126890aSEmmanuel Vadot pinctrl-0 = <&i2c1_xfer>; 543f126890aSEmmanuel Vadot #address-cells = <1>; 544f126890aSEmmanuel Vadot #size-cells = <0>; 545f126890aSEmmanuel Vadot status = "disabled"; 546f126890aSEmmanuel Vadot }; 547f126890aSEmmanuel Vadot 548f126890aSEmmanuel Vadot i2c2: i2c@2005a000 { 549f126890aSEmmanuel Vadot compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 550f126890aSEmmanuel Vadot reg = <0x2005a000 0x1000>; 551f126890aSEmmanuel Vadot interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 552f126890aSEmmanuel Vadot clock-names = "i2c"; 553f126890aSEmmanuel Vadot clocks = <&cru PCLK_I2C2>; 554f126890aSEmmanuel Vadot pinctrl-names = "default"; 555f126890aSEmmanuel Vadot pinctrl-0 = <&i2c2_xfer>; 556f126890aSEmmanuel Vadot #address-cells = <1>; 557f126890aSEmmanuel Vadot #size-cells = <0>; 558f126890aSEmmanuel Vadot status = "disabled"; 559f126890aSEmmanuel Vadot }; 560f126890aSEmmanuel Vadot 561f126890aSEmmanuel Vadot i2c3: i2c@2005e000 { 562f126890aSEmmanuel Vadot compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 563f126890aSEmmanuel Vadot reg = <0x2005e000 0x1000>; 564f126890aSEmmanuel Vadot interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 565f126890aSEmmanuel Vadot clock-names = "i2c"; 566f126890aSEmmanuel Vadot clocks = <&cru PCLK_I2C3>; 567f126890aSEmmanuel Vadot pinctrl-names = "default"; 568f126890aSEmmanuel Vadot pinctrl-0 = <&i2c3_xfer>; 569f126890aSEmmanuel Vadot #address-cells = <1>; 570f126890aSEmmanuel Vadot #size-cells = <0>; 571f126890aSEmmanuel Vadot status = "disabled"; 572f126890aSEmmanuel Vadot }; 573f126890aSEmmanuel Vadot 574f126890aSEmmanuel Vadot uart0: serial@20060000 { 575f126890aSEmmanuel Vadot compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 576f126890aSEmmanuel Vadot reg = <0x20060000 0x100>; 577f126890aSEmmanuel Vadot interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 578f126890aSEmmanuel Vadot clock-frequency = <24000000>; 579f126890aSEmmanuel Vadot clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 580f126890aSEmmanuel Vadot clock-names = "baudclk", "apb_pclk"; 581f126890aSEmmanuel Vadot dmas = <&pdma 2>, <&pdma 3>; 582f126890aSEmmanuel Vadot dma-names = "tx", "rx"; 583f126890aSEmmanuel Vadot pinctrl-names = "default"; 584f126890aSEmmanuel Vadot pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 585f126890aSEmmanuel Vadot reg-io-width = <4>; 586f126890aSEmmanuel Vadot reg-shift = <2>; 587f126890aSEmmanuel Vadot status = "disabled"; 588f126890aSEmmanuel Vadot }; 589f126890aSEmmanuel Vadot 590f126890aSEmmanuel Vadot uart1: serial@20064000 { 591f126890aSEmmanuel Vadot compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 592f126890aSEmmanuel Vadot reg = <0x20064000 0x100>; 593f126890aSEmmanuel Vadot interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 594f126890aSEmmanuel Vadot clock-frequency = <24000000>; 595f126890aSEmmanuel Vadot clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 596f126890aSEmmanuel Vadot clock-names = "baudclk", "apb_pclk"; 597f126890aSEmmanuel Vadot dmas = <&pdma 4>, <&pdma 5>; 598f126890aSEmmanuel Vadot dma-names = "tx", "rx"; 599f126890aSEmmanuel Vadot pinctrl-names = "default"; 600f126890aSEmmanuel Vadot pinctrl-0 = <&uart1_xfer>; 601f126890aSEmmanuel Vadot reg-io-width = <4>; 602f126890aSEmmanuel Vadot reg-shift = <2>; 603f126890aSEmmanuel Vadot status = "disabled"; 604f126890aSEmmanuel Vadot }; 605f126890aSEmmanuel Vadot 606f126890aSEmmanuel Vadot uart2: serial@20068000 { 607f126890aSEmmanuel Vadot compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 608f126890aSEmmanuel Vadot reg = <0x20068000 0x100>; 609f126890aSEmmanuel Vadot interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 610f126890aSEmmanuel Vadot clock-frequency = <24000000>; 611f126890aSEmmanuel Vadot clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 612f126890aSEmmanuel Vadot clock-names = "baudclk", "apb_pclk"; 613f126890aSEmmanuel Vadot dmas = <&pdma 6>, <&pdma 7>; 614f126890aSEmmanuel Vadot dma-names = "tx", "rx"; 615f126890aSEmmanuel Vadot pinctrl-names = "default"; 616f126890aSEmmanuel Vadot pinctrl-0 = <&uart2_xfer>; 617f126890aSEmmanuel Vadot reg-io-width = <4>; 618f126890aSEmmanuel Vadot reg-shift = <2>; 619f126890aSEmmanuel Vadot status = "disabled"; 620f126890aSEmmanuel Vadot }; 621f126890aSEmmanuel Vadot 622f126890aSEmmanuel Vadot saradc: saradc@2006c000 { 623f126890aSEmmanuel Vadot compatible = "rockchip,saradc"; 624f126890aSEmmanuel Vadot reg = <0x2006c000 0x100>; 625f126890aSEmmanuel Vadot interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 626f126890aSEmmanuel Vadot clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 627f126890aSEmmanuel Vadot clock-names = "saradc", "apb_pclk"; 628f126890aSEmmanuel Vadot resets = <&cru SRST_SARADC>; 629f126890aSEmmanuel Vadot reset-names = "saradc-apb"; 630f126890aSEmmanuel Vadot #io-channel-cells = <1>; 631f126890aSEmmanuel Vadot status = "disabled"; 632f126890aSEmmanuel Vadot }; 633f126890aSEmmanuel Vadot 634f126890aSEmmanuel Vadot i2c0: i2c@20072000 { 635f126890aSEmmanuel Vadot compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 636aa1a8ff2SEmmanuel Vadot reg = <0x20072000 0x1000>; 637f126890aSEmmanuel Vadot interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 638f126890aSEmmanuel Vadot clock-names = "i2c"; 639f126890aSEmmanuel Vadot clocks = <&cru PCLK_I2C0>; 640f126890aSEmmanuel Vadot pinctrl-names = "default"; 641f126890aSEmmanuel Vadot pinctrl-0 = <&i2c0_xfer>; 642f126890aSEmmanuel Vadot #address-cells = <1>; 643f126890aSEmmanuel Vadot #size-cells = <0>; 644f126890aSEmmanuel Vadot status = "disabled"; 645f126890aSEmmanuel Vadot }; 646f126890aSEmmanuel Vadot 647f126890aSEmmanuel Vadot spi0: spi@20074000 { 648f126890aSEmmanuel Vadot compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi"; 649f126890aSEmmanuel Vadot reg = <0x20074000 0x1000>; 650f126890aSEmmanuel Vadot interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 651f126890aSEmmanuel Vadot clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 652f126890aSEmmanuel Vadot clock-names = "spiclk", "apb_pclk"; 653f126890aSEmmanuel Vadot dmas = <&pdma 8>, <&pdma 9>; 654f126890aSEmmanuel Vadot dma-names = "tx", "rx"; 655f126890aSEmmanuel Vadot pinctrl-names = "default"; 656f126890aSEmmanuel Vadot pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>; 657f126890aSEmmanuel Vadot #address-cells = <1>; 658f126890aSEmmanuel Vadot #size-cells = <0>; 659f126890aSEmmanuel Vadot status = "disabled"; 660f126890aSEmmanuel Vadot }; 661f126890aSEmmanuel Vadot 662f126890aSEmmanuel Vadot pdma: dma-controller@20078000 { 663f126890aSEmmanuel Vadot compatible = "arm,pl330", "arm,primecell"; 664f126890aSEmmanuel Vadot reg = <0x20078000 0x4000>; 665f126890aSEmmanuel Vadot interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 666f126890aSEmmanuel Vadot <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 667f126890aSEmmanuel Vadot arm,pl330-broken-no-flushp; 668aa1a8ff2SEmmanuel Vadot arm,pl330-periph-burst; 669f126890aSEmmanuel Vadot clocks = <&cru ACLK_DMAC>; 670f126890aSEmmanuel Vadot clock-names = "apb_pclk"; 671f126890aSEmmanuel Vadot #dma-cells = <1>; 672f126890aSEmmanuel Vadot }; 673f126890aSEmmanuel Vadot 674*8d13bc63SEmmanuel Vadot gmac: ethernet@2008c000 { 675*8d13bc63SEmmanuel Vadot compatible = "rockchip,rk3128-gmac"; 676*8d13bc63SEmmanuel Vadot reg = <0x2008c000 0x4000>; 677*8d13bc63SEmmanuel Vadot interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 678*8d13bc63SEmmanuel Vadot <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 679*8d13bc63SEmmanuel Vadot interrupt-names = "macirq", "eth_wake_irq"; 680*8d13bc63SEmmanuel Vadot clocks = <&cru SCLK_MAC>, 681*8d13bc63SEmmanuel Vadot <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 682*8d13bc63SEmmanuel Vadot <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>, 683*8d13bc63SEmmanuel Vadot <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 684*8d13bc63SEmmanuel Vadot clock-names = "stmmaceth", 685*8d13bc63SEmmanuel Vadot "mac_clk_rx", "mac_clk_tx", 686*8d13bc63SEmmanuel Vadot "clk_mac_ref", "clk_mac_refout", 687*8d13bc63SEmmanuel Vadot "aclk_mac", "pclk_mac"; 688*8d13bc63SEmmanuel Vadot resets = <&cru SRST_GMAC>; 689*8d13bc63SEmmanuel Vadot reset-names = "stmmaceth"; 690*8d13bc63SEmmanuel Vadot rockchip,grf = <&grf>; 691*8d13bc63SEmmanuel Vadot rx-fifo-depth = <4096>; 692*8d13bc63SEmmanuel Vadot tx-fifo-depth = <2048>; 693*8d13bc63SEmmanuel Vadot status = "disabled"; 694*8d13bc63SEmmanuel Vadot 695*8d13bc63SEmmanuel Vadot mdio: mdio { 696*8d13bc63SEmmanuel Vadot compatible = "snps,dwmac-mdio"; 697*8d13bc63SEmmanuel Vadot #address-cells = <0x1>; 698*8d13bc63SEmmanuel Vadot #size-cells = <0x0>; 699*8d13bc63SEmmanuel Vadot }; 700*8d13bc63SEmmanuel Vadot }; 701*8d13bc63SEmmanuel Vadot 702f126890aSEmmanuel Vadot pinctrl: pinctrl { 703f126890aSEmmanuel Vadot compatible = "rockchip,rk3128-pinctrl"; 704f126890aSEmmanuel Vadot rockchip,grf = <&grf>; 705f126890aSEmmanuel Vadot #address-cells = <1>; 706f126890aSEmmanuel Vadot #size-cells = <1>; 707f126890aSEmmanuel Vadot ranges; 708f126890aSEmmanuel Vadot 709f126890aSEmmanuel Vadot gpio0: gpio@2007c000 { 710f126890aSEmmanuel Vadot compatible = "rockchip,gpio-bank"; 711f126890aSEmmanuel Vadot reg = <0x2007c000 0x100>; 712f126890aSEmmanuel Vadot interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 713f126890aSEmmanuel Vadot clocks = <&cru PCLK_GPIO0>; 714f126890aSEmmanuel Vadot gpio-controller; 715f126890aSEmmanuel Vadot #gpio-cells = <2>; 716f126890aSEmmanuel Vadot interrupt-controller; 717f126890aSEmmanuel Vadot #interrupt-cells = <2>; 718f126890aSEmmanuel Vadot }; 719f126890aSEmmanuel Vadot 720f126890aSEmmanuel Vadot gpio1: gpio@20080000 { 721f126890aSEmmanuel Vadot compatible = "rockchip,gpio-bank"; 722f126890aSEmmanuel Vadot reg = <0x20080000 0x100>; 723f126890aSEmmanuel Vadot interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 724f126890aSEmmanuel Vadot clocks = <&cru PCLK_GPIO1>; 725f126890aSEmmanuel Vadot gpio-controller; 726f126890aSEmmanuel Vadot #gpio-cells = <2>; 727f126890aSEmmanuel Vadot interrupt-controller; 728f126890aSEmmanuel Vadot #interrupt-cells = <2>; 729f126890aSEmmanuel Vadot }; 730f126890aSEmmanuel Vadot 731f126890aSEmmanuel Vadot gpio2: gpio@20084000 { 732f126890aSEmmanuel Vadot compatible = "rockchip,gpio-bank"; 733f126890aSEmmanuel Vadot reg = <0x20084000 0x100>; 734f126890aSEmmanuel Vadot interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 735f126890aSEmmanuel Vadot clocks = <&cru PCLK_GPIO2>; 736f126890aSEmmanuel Vadot gpio-controller; 737f126890aSEmmanuel Vadot #gpio-cells = <2>; 738f126890aSEmmanuel Vadot interrupt-controller; 739f126890aSEmmanuel Vadot #interrupt-cells = <2>; 740f126890aSEmmanuel Vadot }; 741f126890aSEmmanuel Vadot 742f126890aSEmmanuel Vadot gpio3: gpio@20088000 { 743f126890aSEmmanuel Vadot compatible = "rockchip,gpio-bank"; 744f126890aSEmmanuel Vadot reg = <0x20088000 0x100>; 745f126890aSEmmanuel Vadot interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 746f126890aSEmmanuel Vadot clocks = <&cru PCLK_GPIO3>; 747f126890aSEmmanuel Vadot gpio-controller; 748f126890aSEmmanuel Vadot #gpio-cells = <2>; 749f126890aSEmmanuel Vadot interrupt-controller; 750f126890aSEmmanuel Vadot #interrupt-cells = <2>; 751f126890aSEmmanuel Vadot }; 752f126890aSEmmanuel Vadot 753f126890aSEmmanuel Vadot pcfg_pull_default: pcfg-pull-default { 754f126890aSEmmanuel Vadot bias-pull-pin-default; 755f126890aSEmmanuel Vadot }; 756f126890aSEmmanuel Vadot 757f126890aSEmmanuel Vadot pcfg_pull_none: pcfg-pull-none { 758f126890aSEmmanuel Vadot bias-disable; 759f126890aSEmmanuel Vadot }; 760f126890aSEmmanuel Vadot 761f126890aSEmmanuel Vadot emmc { 762f126890aSEmmanuel Vadot emmc_clk: emmc-clk { 763f126890aSEmmanuel Vadot rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; 764f126890aSEmmanuel Vadot }; 765f126890aSEmmanuel Vadot 766f126890aSEmmanuel Vadot emmc_cmd: emmc-cmd { 767f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>; 768f126890aSEmmanuel Vadot }; 769f126890aSEmmanuel Vadot 770f126890aSEmmanuel Vadot emmc_cmd1: emmc-cmd1 { 771f126890aSEmmanuel Vadot rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>; 772f126890aSEmmanuel Vadot }; 773f126890aSEmmanuel Vadot 774f126890aSEmmanuel Vadot emmc_pwr: emmc-pwr { 775f126890aSEmmanuel Vadot rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>; 776f126890aSEmmanuel Vadot }; 777f126890aSEmmanuel Vadot 778f126890aSEmmanuel Vadot emmc_bus1: emmc-bus1 { 779f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>; 780f126890aSEmmanuel Vadot }; 781f126890aSEmmanuel Vadot 782f126890aSEmmanuel Vadot emmc_bus4: emmc-bus4 { 783f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 784f126890aSEmmanuel Vadot <1 RK_PD1 2 &pcfg_pull_default>, 785f126890aSEmmanuel Vadot <1 RK_PD2 2 &pcfg_pull_default>, 786f126890aSEmmanuel Vadot <1 RK_PD3 2 &pcfg_pull_default>; 787f126890aSEmmanuel Vadot }; 788f126890aSEmmanuel Vadot 789f126890aSEmmanuel Vadot emmc_bus8: emmc-bus8 { 790f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 791f126890aSEmmanuel Vadot <1 RK_PD1 2 &pcfg_pull_default>, 792f126890aSEmmanuel Vadot <1 RK_PD2 2 &pcfg_pull_default>, 793f126890aSEmmanuel Vadot <1 RK_PD3 2 &pcfg_pull_default>, 794f126890aSEmmanuel Vadot <1 RK_PD4 2 &pcfg_pull_default>, 795f126890aSEmmanuel Vadot <1 RK_PD5 2 &pcfg_pull_default>, 796f126890aSEmmanuel Vadot <1 RK_PD6 2 &pcfg_pull_default>, 797f126890aSEmmanuel Vadot <1 RK_PD7 2 &pcfg_pull_default>; 798f126890aSEmmanuel Vadot }; 799f126890aSEmmanuel Vadot }; 800f126890aSEmmanuel Vadot 801f126890aSEmmanuel Vadot gmac { 802f126890aSEmmanuel Vadot rgmii_pins: rgmii-pins { 803f126890aSEmmanuel Vadot rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 804f126890aSEmmanuel Vadot <2 RK_PB1 3 &pcfg_pull_default>, 805f126890aSEmmanuel Vadot <2 RK_PB3 3 &pcfg_pull_default>, 806f126890aSEmmanuel Vadot <2 RK_PB4 3 &pcfg_pull_default>, 807f126890aSEmmanuel Vadot <2 RK_PB5 3 &pcfg_pull_default>, 808f126890aSEmmanuel Vadot <2 RK_PB6 3 &pcfg_pull_default>, 809f126890aSEmmanuel Vadot <2 RK_PC0 3 &pcfg_pull_default>, 810f126890aSEmmanuel Vadot <2 RK_PC1 3 &pcfg_pull_default>, 811f126890aSEmmanuel Vadot <2 RK_PC2 3 &pcfg_pull_default>, 812f126890aSEmmanuel Vadot <2 RK_PC3 3 &pcfg_pull_default>, 813f126890aSEmmanuel Vadot <2 RK_PD1 3 &pcfg_pull_default>, 814f126890aSEmmanuel Vadot <2 RK_PC4 4 &pcfg_pull_default>, 815f126890aSEmmanuel Vadot <2 RK_PC5 4 &pcfg_pull_default>, 816f126890aSEmmanuel Vadot <2 RK_PC6 4 &pcfg_pull_default>, 817f126890aSEmmanuel Vadot <2 RK_PC7 4 &pcfg_pull_default>; 818f126890aSEmmanuel Vadot }; 819f126890aSEmmanuel Vadot 820f126890aSEmmanuel Vadot rmii_pins: rmii-pins { 821f126890aSEmmanuel Vadot rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 822f126890aSEmmanuel Vadot <2 RK_PB4 3 &pcfg_pull_default>, 823f126890aSEmmanuel Vadot <2 RK_PB5 3 &pcfg_pull_default>, 824f126890aSEmmanuel Vadot <2 RK_PB6 3 &pcfg_pull_default>, 825f126890aSEmmanuel Vadot <2 RK_PB7 3 &pcfg_pull_default>, 826f126890aSEmmanuel Vadot <2 RK_PC0 3 &pcfg_pull_default>, 827f126890aSEmmanuel Vadot <2 RK_PC1 3 &pcfg_pull_default>, 828f126890aSEmmanuel Vadot <2 RK_PC2 3 &pcfg_pull_default>, 829f126890aSEmmanuel Vadot <2 RK_PC3 3 &pcfg_pull_default>, 830f126890aSEmmanuel Vadot <2 RK_PD1 3 &pcfg_pull_default>; 831f126890aSEmmanuel Vadot }; 832f126890aSEmmanuel Vadot }; 833f126890aSEmmanuel Vadot 834f126890aSEmmanuel Vadot hdmi { 835f126890aSEmmanuel Vadot hdmii2c_xfer: hdmii2c-xfer { 836f126890aSEmmanuel Vadot rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, 837f126890aSEmmanuel Vadot <0 RK_PA7 2 &pcfg_pull_none>; 838f126890aSEmmanuel Vadot }; 839f126890aSEmmanuel Vadot 840f126890aSEmmanuel Vadot hdmi_hpd: hdmi-hpd { 841f126890aSEmmanuel Vadot rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>; 842f126890aSEmmanuel Vadot }; 843f126890aSEmmanuel Vadot 844f126890aSEmmanuel Vadot hdmi_cec: hdmi-cec { 845f126890aSEmmanuel Vadot rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; 846f126890aSEmmanuel Vadot }; 847f126890aSEmmanuel Vadot }; 848f126890aSEmmanuel Vadot 849f126890aSEmmanuel Vadot i2c0 { 850f126890aSEmmanuel Vadot i2c0_xfer: i2c0-xfer { 851f126890aSEmmanuel Vadot rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, 852f126890aSEmmanuel Vadot <0 RK_PA1 1 &pcfg_pull_none>; 853f126890aSEmmanuel Vadot }; 854f126890aSEmmanuel Vadot }; 855f126890aSEmmanuel Vadot 856f126890aSEmmanuel Vadot i2c1 { 857f126890aSEmmanuel Vadot i2c1_xfer: i2c1-xfer { 858f126890aSEmmanuel Vadot rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, 859f126890aSEmmanuel Vadot <0 RK_PA3 1 &pcfg_pull_none>; 860f126890aSEmmanuel Vadot }; 861f126890aSEmmanuel Vadot }; 862f126890aSEmmanuel Vadot 863f126890aSEmmanuel Vadot i2c2 { 864f126890aSEmmanuel Vadot i2c2_xfer: i2c2-xfer { 865f126890aSEmmanuel Vadot rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>, 866f126890aSEmmanuel Vadot <2 RK_PC5 3 &pcfg_pull_none>; 867f126890aSEmmanuel Vadot }; 868f126890aSEmmanuel Vadot }; 869f126890aSEmmanuel Vadot 870f126890aSEmmanuel Vadot i2c3 { 871f126890aSEmmanuel Vadot i2c3_xfer: i2c3-xfer { 872f126890aSEmmanuel Vadot rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, 873f126890aSEmmanuel Vadot <0 RK_PA7 1 &pcfg_pull_none>; 874f126890aSEmmanuel Vadot }; 875f126890aSEmmanuel Vadot }; 876f126890aSEmmanuel Vadot 877f126890aSEmmanuel Vadot i2s { 878f126890aSEmmanuel Vadot i2s_bus: i2s-bus { 879f126890aSEmmanuel Vadot rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, 880f126890aSEmmanuel Vadot <0 RK_PB1 1 &pcfg_pull_none>, 881f126890aSEmmanuel Vadot <0 RK_PB3 1 &pcfg_pull_none>, 882f126890aSEmmanuel Vadot <0 RK_PB4 1 &pcfg_pull_none>, 883f126890aSEmmanuel Vadot <0 RK_PB5 1 &pcfg_pull_none>, 884f126890aSEmmanuel Vadot <0 RK_PB6 1 &pcfg_pull_none>; 885f126890aSEmmanuel Vadot }; 886f126890aSEmmanuel Vadot 887f126890aSEmmanuel Vadot i2s1_bus: i2s1-bus { 888f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>, 889f126890aSEmmanuel Vadot <1 RK_PA1 1 &pcfg_pull_none>, 890f126890aSEmmanuel Vadot <1 RK_PA2 1 &pcfg_pull_none>, 891f126890aSEmmanuel Vadot <1 RK_PA3 1 &pcfg_pull_none>, 892f126890aSEmmanuel Vadot <1 RK_PA4 1 &pcfg_pull_none>, 893f126890aSEmmanuel Vadot <1 RK_PA5 1 &pcfg_pull_none>; 894f126890aSEmmanuel Vadot }; 895f126890aSEmmanuel Vadot }; 896f126890aSEmmanuel Vadot 897f126890aSEmmanuel Vadot lcdc { 898f126890aSEmmanuel Vadot lcdc_dclk: lcdc-dclk { 899f126890aSEmmanuel Vadot rockchip,pins = <2 RK_PB0 1 &pcfg_pull_none>; 900f126890aSEmmanuel Vadot }; 901f126890aSEmmanuel Vadot 902f126890aSEmmanuel Vadot lcdc_den: lcdc-den { 903f126890aSEmmanuel Vadot rockchip,pins = <2 RK_PB3 1 &pcfg_pull_none>; 904f126890aSEmmanuel Vadot }; 905f126890aSEmmanuel Vadot 906f126890aSEmmanuel Vadot lcdc_hsync: lcdc-hsync { 907f126890aSEmmanuel Vadot rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>; 908f126890aSEmmanuel Vadot }; 909f126890aSEmmanuel Vadot 910f126890aSEmmanuel Vadot lcdc_vsync: lcdc-vsync { 911f126890aSEmmanuel Vadot rockchip,pins = <2 RK_PB2 1 &pcfg_pull_none>; 912f126890aSEmmanuel Vadot }; 913f126890aSEmmanuel Vadot 914f126890aSEmmanuel Vadot lcdc_rgb24: lcdc-rgb24 { 915f126890aSEmmanuel Vadot rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>, 916f126890aSEmmanuel Vadot <2 RK_PB5 1 &pcfg_pull_none>, 917f126890aSEmmanuel Vadot <2 RK_PB6 1 &pcfg_pull_none>, 918f126890aSEmmanuel Vadot <2 RK_PB7 1 &pcfg_pull_none>, 919f126890aSEmmanuel Vadot <2 RK_PC0 1 &pcfg_pull_none>, 920f126890aSEmmanuel Vadot <2 RK_PC1 1 &pcfg_pull_none>, 921f126890aSEmmanuel Vadot <2 RK_PC2 1 &pcfg_pull_none>, 922f126890aSEmmanuel Vadot <2 RK_PC3 1 &pcfg_pull_none>, 923f126890aSEmmanuel Vadot <2 RK_PC4 1 &pcfg_pull_none>, 924f126890aSEmmanuel Vadot <2 RK_PC5 1 &pcfg_pull_none>, 925f126890aSEmmanuel Vadot <2 RK_PC6 1 &pcfg_pull_none>, 926f126890aSEmmanuel Vadot <2 RK_PC7 1 &pcfg_pull_none>, 927f126890aSEmmanuel Vadot <2 RK_PD0 1 &pcfg_pull_none>, 928f126890aSEmmanuel Vadot <2 RK_PD1 1 &pcfg_pull_none>; 929f126890aSEmmanuel Vadot }; 930f126890aSEmmanuel Vadot }; 931f126890aSEmmanuel Vadot 932f126890aSEmmanuel Vadot nfc { 933f126890aSEmmanuel Vadot flash_ale: flash-ale { 934f126890aSEmmanuel Vadot rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>; 935f126890aSEmmanuel Vadot }; 936f126890aSEmmanuel Vadot 937f126890aSEmmanuel Vadot flash_cle: flash-cle { 938f126890aSEmmanuel Vadot rockchip,pins = <2 RK_PA1 1 &pcfg_pull_none>; 939f126890aSEmmanuel Vadot }; 940f126890aSEmmanuel Vadot 941f126890aSEmmanuel Vadot flash_wrn: flash-wrn { 942f126890aSEmmanuel Vadot rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 943f126890aSEmmanuel Vadot }; 944f126890aSEmmanuel Vadot 945f126890aSEmmanuel Vadot flash_rdn: flash-rdn { 946f126890aSEmmanuel Vadot rockchip,pins = <2 RK_PA3 1 &pcfg_pull_none>; 947f126890aSEmmanuel Vadot }; 948f126890aSEmmanuel Vadot 949f126890aSEmmanuel Vadot flash_rdy: flash-rdy { 950f126890aSEmmanuel Vadot rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 951f126890aSEmmanuel Vadot }; 952f126890aSEmmanuel Vadot 953f126890aSEmmanuel Vadot flash_cs0: flash-cs0 { 954f126890aSEmmanuel Vadot rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 955f126890aSEmmanuel Vadot }; 956f126890aSEmmanuel Vadot 957f126890aSEmmanuel Vadot flash_dqs: flash-dqs { 958f126890aSEmmanuel Vadot rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>; 959f126890aSEmmanuel Vadot }; 960f126890aSEmmanuel Vadot 961f126890aSEmmanuel Vadot flash_bus8: flash-bus8 { 962f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, 963f126890aSEmmanuel Vadot <1 RK_PD1 1 &pcfg_pull_none>, 964f126890aSEmmanuel Vadot <1 RK_PD2 1 &pcfg_pull_none>, 965f126890aSEmmanuel Vadot <1 RK_PD3 1 &pcfg_pull_none>, 966f126890aSEmmanuel Vadot <1 RK_PD4 1 &pcfg_pull_none>, 967f126890aSEmmanuel Vadot <1 RK_PD5 1 &pcfg_pull_none>, 968f126890aSEmmanuel Vadot <1 RK_PD6 1 &pcfg_pull_none>, 969f126890aSEmmanuel Vadot <1 RK_PD7 1 &pcfg_pull_none>; 970f126890aSEmmanuel Vadot }; 971f126890aSEmmanuel Vadot }; 972f126890aSEmmanuel Vadot 973f126890aSEmmanuel Vadot pwm0 { 974f126890aSEmmanuel Vadot pwm0_pin: pwm0-pin { 975f126890aSEmmanuel Vadot rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>; 976f126890aSEmmanuel Vadot }; 977f126890aSEmmanuel Vadot }; 978f126890aSEmmanuel Vadot 979f126890aSEmmanuel Vadot pwm1 { 980f126890aSEmmanuel Vadot pwm1_pin: pwm1-pin { 981f126890aSEmmanuel Vadot rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 982f126890aSEmmanuel Vadot }; 983f126890aSEmmanuel Vadot }; 984f126890aSEmmanuel Vadot 985f126890aSEmmanuel Vadot pwm2 { 986f126890aSEmmanuel Vadot pwm2_pin: pwm2-pin { 987f126890aSEmmanuel Vadot rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>; 988f126890aSEmmanuel Vadot }; 989f126890aSEmmanuel Vadot }; 990f126890aSEmmanuel Vadot 991f126890aSEmmanuel Vadot pwm3 { 992f126890aSEmmanuel Vadot pwm3_pin: pwm3-pin { 993f126890aSEmmanuel Vadot rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>; 994f126890aSEmmanuel Vadot }; 995f126890aSEmmanuel Vadot }; 996f126890aSEmmanuel Vadot 997f126890aSEmmanuel Vadot sdio { 998f126890aSEmmanuel Vadot sdio_clk: sdio-clk { 999f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>; 1000f126890aSEmmanuel Vadot }; 1001f126890aSEmmanuel Vadot 1002f126890aSEmmanuel Vadot sdio_cmd: sdio-cmd { 1003f126890aSEmmanuel Vadot rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>; 1004f126890aSEmmanuel Vadot }; 1005f126890aSEmmanuel Vadot 1006f126890aSEmmanuel Vadot sdio_pwren: sdio-pwren { 1007f126890aSEmmanuel Vadot rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>; 1008f126890aSEmmanuel Vadot }; 1009f126890aSEmmanuel Vadot 1010f126890aSEmmanuel Vadot sdio_bus4: sdio-bus4 { 1011f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>, 1012f126890aSEmmanuel Vadot <1 RK_PA2 2 &pcfg_pull_default>, 1013f126890aSEmmanuel Vadot <1 RK_PA4 2 &pcfg_pull_default>, 1014f126890aSEmmanuel Vadot <1 RK_PA5 2 &pcfg_pull_default>; 1015f126890aSEmmanuel Vadot }; 1016f126890aSEmmanuel Vadot }; 1017f126890aSEmmanuel Vadot 1018f126890aSEmmanuel Vadot sdmmc { 1019f126890aSEmmanuel Vadot sdmmc_clk: sdmmc-clk { 1020f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; 1021f126890aSEmmanuel Vadot }; 1022f126890aSEmmanuel Vadot 1023f126890aSEmmanuel Vadot sdmmc_cmd: sdmmc-cmd { 1024f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>; 1025f126890aSEmmanuel Vadot }; 1026f126890aSEmmanuel Vadot 1027*8d13bc63SEmmanuel Vadot sdmmc_det: sdmmc-det { 1028*8d13bc63SEmmanuel Vadot rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>; 1029*8d13bc63SEmmanuel Vadot }; 1030*8d13bc63SEmmanuel Vadot 1031f126890aSEmmanuel Vadot sdmmc_wp: sdmmc-wp { 1032f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; 1033f126890aSEmmanuel Vadot }; 1034f126890aSEmmanuel Vadot 1035f126890aSEmmanuel Vadot sdmmc_pwren: sdmmc-pwren { 103684943d6fSEmmanuel Vadot rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_default>; 1037f126890aSEmmanuel Vadot }; 1038f126890aSEmmanuel Vadot 1039f126890aSEmmanuel Vadot sdmmc_bus4: sdmmc-bus4 { 1040f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>, 1041f126890aSEmmanuel Vadot <1 RK_PC3 1 &pcfg_pull_default>, 1042f126890aSEmmanuel Vadot <1 RK_PC4 1 &pcfg_pull_default>, 1043f126890aSEmmanuel Vadot <1 RK_PC5 1 &pcfg_pull_default>; 1044f126890aSEmmanuel Vadot }; 1045f126890aSEmmanuel Vadot }; 1046f126890aSEmmanuel Vadot 1047f126890aSEmmanuel Vadot spdif { 1048f126890aSEmmanuel Vadot spdif_tx: spdif-tx { 1049f126890aSEmmanuel Vadot rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; 1050f126890aSEmmanuel Vadot }; 1051f126890aSEmmanuel Vadot }; 1052f126890aSEmmanuel Vadot 1053f126890aSEmmanuel Vadot spi0 { 1054f126890aSEmmanuel Vadot spi0_clk: spi0-clk { 1055f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>; 1056f126890aSEmmanuel Vadot }; 1057f126890aSEmmanuel Vadot 1058f126890aSEmmanuel Vadot spi0_cs0: spi0-cs0 { 1059f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>; 1060f126890aSEmmanuel Vadot }; 1061f126890aSEmmanuel Vadot 1062f126890aSEmmanuel Vadot spi0_tx: spi0-tx { 1063f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>; 1064f126890aSEmmanuel Vadot }; 1065f126890aSEmmanuel Vadot 1066f126890aSEmmanuel Vadot spi0_rx: spi0-rx { 1067f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>; 1068f126890aSEmmanuel Vadot }; 1069f126890aSEmmanuel Vadot 1070f126890aSEmmanuel Vadot spi0_cs1: spi0-cs1 { 1071f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>; 1072f126890aSEmmanuel Vadot }; 1073f126890aSEmmanuel Vadot 1074f126890aSEmmanuel Vadot spi1_clk: spi1-clk { 1075f126890aSEmmanuel Vadot rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>; 1076f126890aSEmmanuel Vadot }; 1077f126890aSEmmanuel Vadot 1078f126890aSEmmanuel Vadot spi1_cs0: spi1-cs0 { 1079f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>; 1080f126890aSEmmanuel Vadot }; 1081f126890aSEmmanuel Vadot 1082f126890aSEmmanuel Vadot spi1_tx: spi1-tx { 1083f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>; 1084f126890aSEmmanuel Vadot }; 1085f126890aSEmmanuel Vadot 1086f126890aSEmmanuel Vadot spi1_rx: spi1-rx { 1087f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>; 1088f126890aSEmmanuel Vadot }; 1089f126890aSEmmanuel Vadot 1090f126890aSEmmanuel Vadot spi1_cs1: spi1-cs1 { 1091f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>; 1092f126890aSEmmanuel Vadot }; 1093f126890aSEmmanuel Vadot 1094f126890aSEmmanuel Vadot spi2_clk: spi2-clk { 1095f126890aSEmmanuel Vadot rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>; 1096f126890aSEmmanuel Vadot }; 1097f126890aSEmmanuel Vadot 1098f126890aSEmmanuel Vadot spi2_cs0: spi2-cs0 { 1099f126890aSEmmanuel Vadot rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>; 1100f126890aSEmmanuel Vadot }; 1101f126890aSEmmanuel Vadot 1102f126890aSEmmanuel Vadot spi2_tx: spi2-tx { 1103f126890aSEmmanuel Vadot rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>; 1104f126890aSEmmanuel Vadot }; 1105f126890aSEmmanuel Vadot 1106f126890aSEmmanuel Vadot spi2_rx: spi2-rx { 1107f126890aSEmmanuel Vadot rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>; 1108f126890aSEmmanuel Vadot }; 1109f126890aSEmmanuel Vadot }; 1110f126890aSEmmanuel Vadot 1111f126890aSEmmanuel Vadot uart0 { 1112f126890aSEmmanuel Vadot uart0_xfer: uart0-xfer { 1113f126890aSEmmanuel Vadot rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>, 1114f126890aSEmmanuel Vadot <2 RK_PD3 2 &pcfg_pull_none>; 1115f126890aSEmmanuel Vadot }; 1116f126890aSEmmanuel Vadot 1117f126890aSEmmanuel Vadot uart0_cts: uart0-cts { 1118f126890aSEmmanuel Vadot rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>; 1119f126890aSEmmanuel Vadot }; 1120f126890aSEmmanuel Vadot 1121f126890aSEmmanuel Vadot uart0_rts: uart0-rts { 1122f126890aSEmmanuel Vadot rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>; 1123f126890aSEmmanuel Vadot }; 1124f126890aSEmmanuel Vadot }; 1125f126890aSEmmanuel Vadot 1126f126890aSEmmanuel Vadot uart1 { 1127f126890aSEmmanuel Vadot uart1_xfer: uart1-xfer { 1128f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>, 1129f126890aSEmmanuel Vadot <1 RK_PB2 2 &pcfg_pull_default>; 1130f126890aSEmmanuel Vadot }; 1131f126890aSEmmanuel Vadot 1132f126890aSEmmanuel Vadot uart1_cts: uart1-cts { 1133f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>; 1134f126890aSEmmanuel Vadot }; 1135f126890aSEmmanuel Vadot 1136f126890aSEmmanuel Vadot uart1_rts: uart1-rts { 1137f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; 1138f126890aSEmmanuel Vadot }; 1139f126890aSEmmanuel Vadot }; 1140f126890aSEmmanuel Vadot 1141f126890aSEmmanuel Vadot uart2 { 1142f126890aSEmmanuel Vadot uart2_xfer: uart2-xfer { 1143f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>, 1144f126890aSEmmanuel Vadot <1 RK_PC3 2 &pcfg_pull_none>; 1145f126890aSEmmanuel Vadot }; 1146f126890aSEmmanuel Vadot 1147f126890aSEmmanuel Vadot uart2_cts: uart2-cts { 1148f126890aSEmmanuel Vadot rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; 1149f126890aSEmmanuel Vadot }; 1150f126890aSEmmanuel Vadot 1151f126890aSEmmanuel Vadot uart2_rts: uart2-rts { 1152f126890aSEmmanuel Vadot rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; 1153f126890aSEmmanuel Vadot }; 1154f126890aSEmmanuel Vadot }; 1155f126890aSEmmanuel Vadot }; 1156f126890aSEmmanuel Vadot}; 1157