1*f126890aSEmmanuel Vadot// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*f126890aSEmmanuel Vadot/* 3*f126890aSEmmanuel Vadot * Copyright (c) 2013 MundoReader S.L. 4*f126890aSEmmanuel Vadot * Author: Heiko Stuebner <heiko@sntech.de> 5*f126890aSEmmanuel Vadot */ 6*f126890aSEmmanuel Vadot 7*f126890aSEmmanuel Vadot#include <dt-bindings/gpio/gpio.h> 8*f126890aSEmmanuel Vadot#include <dt-bindings/pinctrl/rockchip.h> 9*f126890aSEmmanuel Vadot#include <dt-bindings/clock/rk3188-cru.h> 10*f126890aSEmmanuel Vadot#include <dt-bindings/power/rk3188-power.h> 11*f126890aSEmmanuel Vadot#include "rk3xxx.dtsi" 12*f126890aSEmmanuel Vadot 13*f126890aSEmmanuel Vadot/ { 14*f126890aSEmmanuel Vadot compatible = "rockchip,rk3188"; 15*f126890aSEmmanuel Vadot 16*f126890aSEmmanuel Vadot cpus { 17*f126890aSEmmanuel Vadot #address-cells = <1>; 18*f126890aSEmmanuel Vadot #size-cells = <0>; 19*f126890aSEmmanuel Vadot enable-method = "rockchip,rk3066-smp"; 20*f126890aSEmmanuel Vadot 21*f126890aSEmmanuel Vadot cpu0: cpu@0 { 22*f126890aSEmmanuel Vadot device_type = "cpu"; 23*f126890aSEmmanuel Vadot compatible = "arm,cortex-a9"; 24*f126890aSEmmanuel Vadot next-level-cache = <&L2>; 25*f126890aSEmmanuel Vadot reg = <0x0>; 26*f126890aSEmmanuel Vadot clock-latency = <40000>; 27*f126890aSEmmanuel Vadot clocks = <&cru ARMCLK>; 28*f126890aSEmmanuel Vadot operating-points-v2 = <&cpu0_opp_table>; 29*f126890aSEmmanuel Vadot resets = <&cru SRST_CORE0>; 30*f126890aSEmmanuel Vadot }; 31*f126890aSEmmanuel Vadot cpu1: cpu@1 { 32*f126890aSEmmanuel Vadot device_type = "cpu"; 33*f126890aSEmmanuel Vadot compatible = "arm,cortex-a9"; 34*f126890aSEmmanuel Vadot next-level-cache = <&L2>; 35*f126890aSEmmanuel Vadot reg = <0x1>; 36*f126890aSEmmanuel Vadot operating-points-v2 = <&cpu0_opp_table>; 37*f126890aSEmmanuel Vadot resets = <&cru SRST_CORE1>; 38*f126890aSEmmanuel Vadot }; 39*f126890aSEmmanuel Vadot cpu2: cpu@2 { 40*f126890aSEmmanuel Vadot device_type = "cpu"; 41*f126890aSEmmanuel Vadot compatible = "arm,cortex-a9"; 42*f126890aSEmmanuel Vadot next-level-cache = <&L2>; 43*f126890aSEmmanuel Vadot reg = <0x2>; 44*f126890aSEmmanuel Vadot operating-points-v2 = <&cpu0_opp_table>; 45*f126890aSEmmanuel Vadot resets = <&cru SRST_CORE2>; 46*f126890aSEmmanuel Vadot }; 47*f126890aSEmmanuel Vadot cpu3: cpu@3 { 48*f126890aSEmmanuel Vadot device_type = "cpu"; 49*f126890aSEmmanuel Vadot compatible = "arm,cortex-a9"; 50*f126890aSEmmanuel Vadot next-level-cache = <&L2>; 51*f126890aSEmmanuel Vadot reg = <0x3>; 52*f126890aSEmmanuel Vadot operating-points-v2 = <&cpu0_opp_table>; 53*f126890aSEmmanuel Vadot resets = <&cru SRST_CORE3>; 54*f126890aSEmmanuel Vadot }; 55*f126890aSEmmanuel Vadot }; 56*f126890aSEmmanuel Vadot 57*f126890aSEmmanuel Vadot cpu0_opp_table: opp-table-0 { 58*f126890aSEmmanuel Vadot compatible = "operating-points-v2"; 59*f126890aSEmmanuel Vadot opp-shared; 60*f126890aSEmmanuel Vadot 61*f126890aSEmmanuel Vadot opp-312000000 { 62*f126890aSEmmanuel Vadot opp-hz = /bits/ 64 <312000000>; 63*f126890aSEmmanuel Vadot opp-microvolt = <875000>; 64*f126890aSEmmanuel Vadot clock-latency-ns = <40000>; 65*f126890aSEmmanuel Vadot }; 66*f126890aSEmmanuel Vadot opp-504000000 { 67*f126890aSEmmanuel Vadot opp-hz = /bits/ 64 <504000000>; 68*f126890aSEmmanuel Vadot opp-microvolt = <925000>; 69*f126890aSEmmanuel Vadot }; 70*f126890aSEmmanuel Vadot opp-600000000 { 71*f126890aSEmmanuel Vadot opp-hz = /bits/ 64 <600000000>; 72*f126890aSEmmanuel Vadot opp-microvolt = <950000>; 73*f126890aSEmmanuel Vadot opp-suspend; 74*f126890aSEmmanuel Vadot }; 75*f126890aSEmmanuel Vadot opp-816000000 { 76*f126890aSEmmanuel Vadot opp-hz = /bits/ 64 <816000000>; 77*f126890aSEmmanuel Vadot opp-microvolt = <975000>; 78*f126890aSEmmanuel Vadot }; 79*f126890aSEmmanuel Vadot opp-1008000000 { 80*f126890aSEmmanuel Vadot opp-hz = /bits/ 64 <1008000000>; 81*f126890aSEmmanuel Vadot opp-microvolt = <1075000>; 82*f126890aSEmmanuel Vadot }; 83*f126890aSEmmanuel Vadot opp-1200000000 { 84*f126890aSEmmanuel Vadot opp-hz = /bits/ 64 <1200000000>; 85*f126890aSEmmanuel Vadot opp-microvolt = <1150000>; 86*f126890aSEmmanuel Vadot }; 87*f126890aSEmmanuel Vadot opp-1416000000 { 88*f126890aSEmmanuel Vadot opp-hz = /bits/ 64 <1416000000>; 89*f126890aSEmmanuel Vadot opp-microvolt = <1250000>; 90*f126890aSEmmanuel Vadot }; 91*f126890aSEmmanuel Vadot opp-1608000000 { 92*f126890aSEmmanuel Vadot opp-hz = /bits/ 64 <1608000000>; 93*f126890aSEmmanuel Vadot opp-microvolt = <1350000>; 94*f126890aSEmmanuel Vadot }; 95*f126890aSEmmanuel Vadot }; 96*f126890aSEmmanuel Vadot 97*f126890aSEmmanuel Vadot display-subsystem { 98*f126890aSEmmanuel Vadot compatible = "rockchip,display-subsystem"; 99*f126890aSEmmanuel Vadot ports = <&vop0_out>, <&vop1_out>; 100*f126890aSEmmanuel Vadot }; 101*f126890aSEmmanuel Vadot 102*f126890aSEmmanuel Vadot sram: sram@10080000 { 103*f126890aSEmmanuel Vadot compatible = "mmio-sram"; 104*f126890aSEmmanuel Vadot reg = <0x10080000 0x8000>; 105*f126890aSEmmanuel Vadot #address-cells = <1>; 106*f126890aSEmmanuel Vadot #size-cells = <1>; 107*f126890aSEmmanuel Vadot ranges = <0 0x10080000 0x8000>; 108*f126890aSEmmanuel Vadot 109*f126890aSEmmanuel Vadot smp-sram@0 { 110*f126890aSEmmanuel Vadot compatible = "rockchip,rk3066-smp-sram"; 111*f126890aSEmmanuel Vadot reg = <0x0 0x50>; 112*f126890aSEmmanuel Vadot }; 113*f126890aSEmmanuel Vadot }; 114*f126890aSEmmanuel Vadot 115*f126890aSEmmanuel Vadot vop0: vop@1010c000 { 116*f126890aSEmmanuel Vadot compatible = "rockchip,rk3188-vop"; 117*f126890aSEmmanuel Vadot reg = <0x1010c000 0x1000>; 118*f126890aSEmmanuel Vadot interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 119*f126890aSEmmanuel Vadot clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>; 120*f126890aSEmmanuel Vadot clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 121*f126890aSEmmanuel Vadot power-domains = <&power RK3188_PD_VIO>; 122*f126890aSEmmanuel Vadot resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; 123*f126890aSEmmanuel Vadot reset-names = "axi", "ahb", "dclk"; 124*f126890aSEmmanuel Vadot status = "disabled"; 125*f126890aSEmmanuel Vadot 126*f126890aSEmmanuel Vadot vop0_out: port { 127*f126890aSEmmanuel Vadot #address-cells = <1>; 128*f126890aSEmmanuel Vadot #size-cells = <0>; 129*f126890aSEmmanuel Vadot }; 130*f126890aSEmmanuel Vadot }; 131*f126890aSEmmanuel Vadot 132*f126890aSEmmanuel Vadot vop1: vop@1010e000 { 133*f126890aSEmmanuel Vadot compatible = "rockchip,rk3188-vop"; 134*f126890aSEmmanuel Vadot reg = <0x1010e000 0x1000>; 135*f126890aSEmmanuel Vadot interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 136*f126890aSEmmanuel Vadot clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>; 137*f126890aSEmmanuel Vadot clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 138*f126890aSEmmanuel Vadot power-domains = <&power RK3188_PD_VIO>; 139*f126890aSEmmanuel Vadot resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; 140*f126890aSEmmanuel Vadot reset-names = "axi", "ahb", "dclk"; 141*f126890aSEmmanuel Vadot status = "disabled"; 142*f126890aSEmmanuel Vadot 143*f126890aSEmmanuel Vadot vop1_out: port { 144*f126890aSEmmanuel Vadot #address-cells = <1>; 145*f126890aSEmmanuel Vadot #size-cells = <0>; 146*f126890aSEmmanuel Vadot }; 147*f126890aSEmmanuel Vadot }; 148*f126890aSEmmanuel Vadot 149*f126890aSEmmanuel Vadot timer3: timer@2000e000 { 150*f126890aSEmmanuel Vadot compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; 151*f126890aSEmmanuel Vadot reg = <0x2000e000 0x20>; 152*f126890aSEmmanuel Vadot interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 153*f126890aSEmmanuel Vadot clocks = <&cru PCLK_TIMER3>, <&cru SCLK_TIMER3>; 154*f126890aSEmmanuel Vadot clock-names = "pclk", "timer"; 155*f126890aSEmmanuel Vadot }; 156*f126890aSEmmanuel Vadot 157*f126890aSEmmanuel Vadot timer6: timer@200380a0 { 158*f126890aSEmmanuel Vadot compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; 159*f126890aSEmmanuel Vadot reg = <0x200380a0 0x20>; 160*f126890aSEmmanuel Vadot interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 161*f126890aSEmmanuel Vadot clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER6>; 162*f126890aSEmmanuel Vadot clock-names = "pclk", "timer"; 163*f126890aSEmmanuel Vadot }; 164*f126890aSEmmanuel Vadot 165*f126890aSEmmanuel Vadot i2s0: i2s@1011a000 { 166*f126890aSEmmanuel Vadot compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s"; 167*f126890aSEmmanuel Vadot reg = <0x1011a000 0x2000>; 168*f126890aSEmmanuel Vadot interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 169*f126890aSEmmanuel Vadot pinctrl-names = "default"; 170*f126890aSEmmanuel Vadot pinctrl-0 = <&i2s0_bus>; 171*f126890aSEmmanuel Vadot clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; 172*f126890aSEmmanuel Vadot clock-names = "i2s_clk", "i2s_hclk"; 173*f126890aSEmmanuel Vadot dmas = <&dmac1_s 6>, <&dmac1_s 7>; 174*f126890aSEmmanuel Vadot dma-names = "tx", "rx"; 175*f126890aSEmmanuel Vadot rockchip,playback-channels = <2>; 176*f126890aSEmmanuel Vadot rockchip,capture-channels = <2>; 177*f126890aSEmmanuel Vadot #sound-dai-cells = <0>; 178*f126890aSEmmanuel Vadot status = "disabled"; 179*f126890aSEmmanuel Vadot }; 180*f126890aSEmmanuel Vadot 181*f126890aSEmmanuel Vadot spdif: sound@1011e000 { 182*f126890aSEmmanuel Vadot compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif"; 183*f126890aSEmmanuel Vadot reg = <0x1011e000 0x2000>; 184*f126890aSEmmanuel Vadot #sound-dai-cells = <0>; 185*f126890aSEmmanuel Vadot clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>; 186*f126890aSEmmanuel Vadot clock-names = "mclk", "hclk"; 187*f126890aSEmmanuel Vadot dmas = <&dmac1_s 8>; 188*f126890aSEmmanuel Vadot dma-names = "tx"; 189*f126890aSEmmanuel Vadot interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 190*f126890aSEmmanuel Vadot pinctrl-names = "default"; 191*f126890aSEmmanuel Vadot pinctrl-0 = <&spdif_tx>; 192*f126890aSEmmanuel Vadot status = "disabled"; 193*f126890aSEmmanuel Vadot }; 194*f126890aSEmmanuel Vadot 195*f126890aSEmmanuel Vadot cru: clock-controller@20000000 { 196*f126890aSEmmanuel Vadot compatible = "rockchip,rk3188-cru"; 197*f126890aSEmmanuel Vadot reg = <0x20000000 0x1000>; 198*f126890aSEmmanuel Vadot clocks = <&xin24m>; 199*f126890aSEmmanuel Vadot clock-names = "xin24m"; 200*f126890aSEmmanuel Vadot rockchip,grf = <&grf>; 201*f126890aSEmmanuel Vadot #clock-cells = <1>; 202*f126890aSEmmanuel Vadot #reset-cells = <1>; 203*f126890aSEmmanuel Vadot }; 204*f126890aSEmmanuel Vadot 205*f126890aSEmmanuel Vadot efuse: efuse@20010000 { 206*f126890aSEmmanuel Vadot compatible = "rockchip,rk3188-efuse"; 207*f126890aSEmmanuel Vadot reg = <0x20010000 0x4000>; 208*f126890aSEmmanuel Vadot #address-cells = <1>; 209*f126890aSEmmanuel Vadot #size-cells = <1>; 210*f126890aSEmmanuel Vadot clocks = <&cru PCLK_EFUSE>; 211*f126890aSEmmanuel Vadot clock-names = "pclk_efuse"; 212*f126890aSEmmanuel Vadot 213*f126890aSEmmanuel Vadot cpu_leakage: cpu_leakage@17 { 214*f126890aSEmmanuel Vadot reg = <0x17 0x1>; 215*f126890aSEmmanuel Vadot }; 216*f126890aSEmmanuel Vadot }; 217*f126890aSEmmanuel Vadot 218*f126890aSEmmanuel Vadot pinctrl: pinctrl { 219*f126890aSEmmanuel Vadot compatible = "rockchip,rk3188-pinctrl"; 220*f126890aSEmmanuel Vadot rockchip,grf = <&grf>; 221*f126890aSEmmanuel Vadot rockchip,pmu = <&pmu>; 222*f126890aSEmmanuel Vadot 223*f126890aSEmmanuel Vadot #address-cells = <1>; 224*f126890aSEmmanuel Vadot #size-cells = <1>; 225*f126890aSEmmanuel Vadot ranges; 226*f126890aSEmmanuel Vadot 227*f126890aSEmmanuel Vadot gpio0: gpio@2000a000 { 228*f126890aSEmmanuel Vadot compatible = "rockchip,rk3188-gpio-bank0"; 229*f126890aSEmmanuel Vadot reg = <0x2000a000 0x100>; 230*f126890aSEmmanuel Vadot interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 231*f126890aSEmmanuel Vadot clocks = <&cru PCLK_GPIO0>; 232*f126890aSEmmanuel Vadot 233*f126890aSEmmanuel Vadot gpio-controller; 234*f126890aSEmmanuel Vadot #gpio-cells = <2>; 235*f126890aSEmmanuel Vadot 236*f126890aSEmmanuel Vadot interrupt-controller; 237*f126890aSEmmanuel Vadot #interrupt-cells = <2>; 238*f126890aSEmmanuel Vadot }; 239*f126890aSEmmanuel Vadot 240*f126890aSEmmanuel Vadot gpio1: gpio@2003c000 { 241*f126890aSEmmanuel Vadot compatible = "rockchip,gpio-bank"; 242*f126890aSEmmanuel Vadot reg = <0x2003c000 0x100>; 243*f126890aSEmmanuel Vadot interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 244*f126890aSEmmanuel Vadot clocks = <&cru PCLK_GPIO1>; 245*f126890aSEmmanuel Vadot 246*f126890aSEmmanuel Vadot gpio-controller; 247*f126890aSEmmanuel Vadot #gpio-cells = <2>; 248*f126890aSEmmanuel Vadot 249*f126890aSEmmanuel Vadot interrupt-controller; 250*f126890aSEmmanuel Vadot #interrupt-cells = <2>; 251*f126890aSEmmanuel Vadot }; 252*f126890aSEmmanuel Vadot 253*f126890aSEmmanuel Vadot gpio2: gpio@2003e000 { 254*f126890aSEmmanuel Vadot compatible = "rockchip,gpio-bank"; 255*f126890aSEmmanuel Vadot reg = <0x2003e000 0x100>; 256*f126890aSEmmanuel Vadot interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 257*f126890aSEmmanuel Vadot clocks = <&cru PCLK_GPIO2>; 258*f126890aSEmmanuel Vadot 259*f126890aSEmmanuel Vadot gpio-controller; 260*f126890aSEmmanuel Vadot #gpio-cells = <2>; 261*f126890aSEmmanuel Vadot 262*f126890aSEmmanuel Vadot interrupt-controller; 263*f126890aSEmmanuel Vadot #interrupt-cells = <2>; 264*f126890aSEmmanuel Vadot }; 265*f126890aSEmmanuel Vadot 266*f126890aSEmmanuel Vadot gpio3: gpio@20080000 { 267*f126890aSEmmanuel Vadot compatible = "rockchip,gpio-bank"; 268*f126890aSEmmanuel Vadot reg = <0x20080000 0x100>; 269*f126890aSEmmanuel Vadot interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 270*f126890aSEmmanuel Vadot clocks = <&cru PCLK_GPIO3>; 271*f126890aSEmmanuel Vadot 272*f126890aSEmmanuel Vadot gpio-controller; 273*f126890aSEmmanuel Vadot #gpio-cells = <2>; 274*f126890aSEmmanuel Vadot 275*f126890aSEmmanuel Vadot interrupt-controller; 276*f126890aSEmmanuel Vadot #interrupt-cells = <2>; 277*f126890aSEmmanuel Vadot }; 278*f126890aSEmmanuel Vadot 279*f126890aSEmmanuel Vadot pcfg_pull_up: pcfg-pull-up { 280*f126890aSEmmanuel Vadot bias-pull-up; 281*f126890aSEmmanuel Vadot }; 282*f126890aSEmmanuel Vadot 283*f126890aSEmmanuel Vadot pcfg_pull_down: pcfg-pull-down { 284*f126890aSEmmanuel Vadot bias-pull-down; 285*f126890aSEmmanuel Vadot }; 286*f126890aSEmmanuel Vadot 287*f126890aSEmmanuel Vadot pcfg_pull_none: pcfg-pull-none { 288*f126890aSEmmanuel Vadot bias-disable; 289*f126890aSEmmanuel Vadot }; 290*f126890aSEmmanuel Vadot 291*f126890aSEmmanuel Vadot emmc { 292*f126890aSEmmanuel Vadot emmc_clk: emmc-clk { 293*f126890aSEmmanuel Vadot rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>; 294*f126890aSEmmanuel Vadot }; 295*f126890aSEmmanuel Vadot 296*f126890aSEmmanuel Vadot emmc_cmd: emmc-cmd { 297*f126890aSEmmanuel Vadot rockchip,pins = <0 RK_PD2 2 &pcfg_pull_up>; 298*f126890aSEmmanuel Vadot }; 299*f126890aSEmmanuel Vadot 300*f126890aSEmmanuel Vadot emmc_rst: emmc-rst { 301*f126890aSEmmanuel Vadot rockchip,pins = <0 RK_PD3 2 &pcfg_pull_none>; 302*f126890aSEmmanuel Vadot }; 303*f126890aSEmmanuel Vadot 304*f126890aSEmmanuel Vadot /* 305*f126890aSEmmanuel Vadot * The data pins are shared between nandc and emmc and 306*f126890aSEmmanuel Vadot * not accessible through pinctrl. Also they should've 307*f126890aSEmmanuel Vadot * been already set correctly by firmware, as 308*f126890aSEmmanuel Vadot * flash/emmc is the boot-device. 309*f126890aSEmmanuel Vadot */ 310*f126890aSEmmanuel Vadot }; 311*f126890aSEmmanuel Vadot 312*f126890aSEmmanuel Vadot emac { 313*f126890aSEmmanuel Vadot emac_xfer: emac-xfer { 314*f126890aSEmmanuel Vadot rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>, /* tx_en */ 315*f126890aSEmmanuel Vadot <3 RK_PC1 2 &pcfg_pull_none>, /* txd1 */ 316*f126890aSEmmanuel Vadot <3 RK_PC2 2 &pcfg_pull_none>, /* txd0 */ 317*f126890aSEmmanuel Vadot <3 RK_PC3 2 &pcfg_pull_none>, /* rxd0 */ 318*f126890aSEmmanuel Vadot <3 RK_PC4 2 &pcfg_pull_none>, /* rxd1 */ 319*f126890aSEmmanuel Vadot <3 RK_PC5 2 &pcfg_pull_none>, /* mac_clk */ 320*f126890aSEmmanuel Vadot <3 RK_PC6 2 &pcfg_pull_none>, /* rx_err */ 321*f126890aSEmmanuel Vadot <3 RK_PC7 2 &pcfg_pull_none>; /* crs_dvalid */ 322*f126890aSEmmanuel Vadot }; 323*f126890aSEmmanuel Vadot 324*f126890aSEmmanuel Vadot emac_mdio: emac-mdio { 325*f126890aSEmmanuel Vadot rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>, 326*f126890aSEmmanuel Vadot <3 RK_PD1 2 &pcfg_pull_none>; 327*f126890aSEmmanuel Vadot }; 328*f126890aSEmmanuel Vadot }; 329*f126890aSEmmanuel Vadot 330*f126890aSEmmanuel Vadot i2c0 { 331*f126890aSEmmanuel Vadot i2c0_xfer: i2c0-xfer { 332*f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, 333*f126890aSEmmanuel Vadot <1 RK_PD1 1 &pcfg_pull_none>; 334*f126890aSEmmanuel Vadot }; 335*f126890aSEmmanuel Vadot }; 336*f126890aSEmmanuel Vadot 337*f126890aSEmmanuel Vadot i2c1 { 338*f126890aSEmmanuel Vadot i2c1_xfer: i2c1-xfer { 339*f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>, 340*f126890aSEmmanuel Vadot <1 RK_PD3 1 &pcfg_pull_none>; 341*f126890aSEmmanuel Vadot }; 342*f126890aSEmmanuel Vadot }; 343*f126890aSEmmanuel Vadot 344*f126890aSEmmanuel Vadot i2c2 { 345*f126890aSEmmanuel Vadot i2c2_xfer: i2c2-xfer { 346*f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>, 347*f126890aSEmmanuel Vadot <1 RK_PD5 1 &pcfg_pull_none>; 348*f126890aSEmmanuel Vadot }; 349*f126890aSEmmanuel Vadot }; 350*f126890aSEmmanuel Vadot 351*f126890aSEmmanuel Vadot i2c3 { 352*f126890aSEmmanuel Vadot i2c3_xfer: i2c3-xfer { 353*f126890aSEmmanuel Vadot rockchip,pins = <3 RK_PB6 2 &pcfg_pull_none>, 354*f126890aSEmmanuel Vadot <3 RK_PB7 2 &pcfg_pull_none>; 355*f126890aSEmmanuel Vadot }; 356*f126890aSEmmanuel Vadot }; 357*f126890aSEmmanuel Vadot 358*f126890aSEmmanuel Vadot i2c4 { 359*f126890aSEmmanuel Vadot i2c4_xfer: i2c4-xfer { 360*f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PD6 1 &pcfg_pull_none>, 361*f126890aSEmmanuel Vadot <1 RK_PD7 1 &pcfg_pull_none>; 362*f126890aSEmmanuel Vadot }; 363*f126890aSEmmanuel Vadot }; 364*f126890aSEmmanuel Vadot 365*f126890aSEmmanuel Vadot lcdc1 { 366*f126890aSEmmanuel Vadot lcdc1_dclk: lcdc1-dclk { 367*f126890aSEmmanuel Vadot rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>; 368*f126890aSEmmanuel Vadot }; 369*f126890aSEmmanuel Vadot 370*f126890aSEmmanuel Vadot lcdc1_den: lcdc1-den { 371*f126890aSEmmanuel Vadot rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none>; 372*f126890aSEmmanuel Vadot }; 373*f126890aSEmmanuel Vadot 374*f126890aSEmmanuel Vadot lcdc1_hsync: lcdc1-hsync { 375*f126890aSEmmanuel Vadot rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>; 376*f126890aSEmmanuel Vadot }; 377*f126890aSEmmanuel Vadot 378*f126890aSEmmanuel Vadot lcdc1_vsync: lcdc1-vsync { 379*f126890aSEmmanuel Vadot rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>; 380*f126890aSEmmanuel Vadot }; 381*f126890aSEmmanuel Vadot 382*f126890aSEmmanuel Vadot lcdc1_rgb24: lcdc1-rgb24 { 383*f126890aSEmmanuel Vadot rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>, 384*f126890aSEmmanuel Vadot <2 RK_PA1 1 &pcfg_pull_none>, 385*f126890aSEmmanuel Vadot <2 RK_PA2 1 &pcfg_pull_none>, 386*f126890aSEmmanuel Vadot <2 RK_PA3 1 &pcfg_pull_none>, 387*f126890aSEmmanuel Vadot <2 RK_PA4 1 &pcfg_pull_none>, 388*f126890aSEmmanuel Vadot <2 RK_PA5 1 &pcfg_pull_none>, 389*f126890aSEmmanuel Vadot <2 RK_PA6 1 &pcfg_pull_none>, 390*f126890aSEmmanuel Vadot <2 RK_PA7 1 &pcfg_pull_none>, 391*f126890aSEmmanuel Vadot <2 RK_PB0 1 &pcfg_pull_none>, 392*f126890aSEmmanuel Vadot <2 RK_PB1 1 &pcfg_pull_none>, 393*f126890aSEmmanuel Vadot <2 RK_PB2 1 &pcfg_pull_none>, 394*f126890aSEmmanuel Vadot <2 RK_PB3 1 &pcfg_pull_none>, 395*f126890aSEmmanuel Vadot <2 RK_PB4 1 &pcfg_pull_none>, 396*f126890aSEmmanuel Vadot <2 RK_PB5 1 &pcfg_pull_none>, 397*f126890aSEmmanuel Vadot <2 RK_PB6 1 &pcfg_pull_none>, 398*f126890aSEmmanuel Vadot <2 RK_PB7 1 &pcfg_pull_none>, 399*f126890aSEmmanuel Vadot <2 RK_PC0 1 &pcfg_pull_none>, 400*f126890aSEmmanuel Vadot <2 RK_PC1 1 &pcfg_pull_none>, 401*f126890aSEmmanuel Vadot <2 RK_PC2 1 &pcfg_pull_none>, 402*f126890aSEmmanuel Vadot <2 RK_PC3 1 &pcfg_pull_none>, 403*f126890aSEmmanuel Vadot <2 RK_PC4 1 &pcfg_pull_none>, 404*f126890aSEmmanuel Vadot <2 RK_PC5 1 &pcfg_pull_none>, 405*f126890aSEmmanuel Vadot <2 RK_PC6 1 &pcfg_pull_none>, 406*f126890aSEmmanuel Vadot <2 RK_PC7 1 &pcfg_pull_none>; 407*f126890aSEmmanuel Vadot }; 408*f126890aSEmmanuel Vadot }; 409*f126890aSEmmanuel Vadot 410*f126890aSEmmanuel Vadot pwm0 { 411*f126890aSEmmanuel Vadot pwm0_out: pwm0-out { 412*f126890aSEmmanuel Vadot rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; 413*f126890aSEmmanuel Vadot }; 414*f126890aSEmmanuel Vadot }; 415*f126890aSEmmanuel Vadot 416*f126890aSEmmanuel Vadot pwm1 { 417*f126890aSEmmanuel Vadot pwm1_out: pwm1-out { 418*f126890aSEmmanuel Vadot rockchip,pins = <3 RK_PD4 1 &pcfg_pull_none>; 419*f126890aSEmmanuel Vadot }; 420*f126890aSEmmanuel Vadot }; 421*f126890aSEmmanuel Vadot 422*f126890aSEmmanuel Vadot pwm2 { 423*f126890aSEmmanuel Vadot pwm2_out: pwm2-out { 424*f126890aSEmmanuel Vadot rockchip,pins = <3 RK_PD5 1 &pcfg_pull_none>; 425*f126890aSEmmanuel Vadot }; 426*f126890aSEmmanuel Vadot }; 427*f126890aSEmmanuel Vadot 428*f126890aSEmmanuel Vadot pwm3 { 429*f126890aSEmmanuel Vadot pwm3_out: pwm3-out { 430*f126890aSEmmanuel Vadot rockchip,pins = <3 RK_PD6 1 &pcfg_pull_none>; 431*f126890aSEmmanuel Vadot }; 432*f126890aSEmmanuel Vadot }; 433*f126890aSEmmanuel Vadot 434*f126890aSEmmanuel Vadot spi0 { 435*f126890aSEmmanuel Vadot spi0_clk: spi0-clk { 436*f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PA6 2 &pcfg_pull_up>; 437*f126890aSEmmanuel Vadot }; 438*f126890aSEmmanuel Vadot spi0_cs0: spi0-cs0 { 439*f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PA7 2 &pcfg_pull_up>; 440*f126890aSEmmanuel Vadot }; 441*f126890aSEmmanuel Vadot spi0_tx: spi0-tx { 442*f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PA5 2 &pcfg_pull_up>; 443*f126890aSEmmanuel Vadot }; 444*f126890aSEmmanuel Vadot spi0_rx: spi0-rx { 445*f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PA4 2 &pcfg_pull_up>; 446*f126890aSEmmanuel Vadot }; 447*f126890aSEmmanuel Vadot spi0_cs1: spi0-cs1 { 448*f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PB7 1 &pcfg_pull_up>; 449*f126890aSEmmanuel Vadot }; 450*f126890aSEmmanuel Vadot }; 451*f126890aSEmmanuel Vadot 452*f126890aSEmmanuel Vadot spi1 { 453*f126890aSEmmanuel Vadot spi1_clk: spi1-clk { 454*f126890aSEmmanuel Vadot rockchip,pins = <0 RK_PD6 1 &pcfg_pull_up>; 455*f126890aSEmmanuel Vadot }; 456*f126890aSEmmanuel Vadot spi1_cs0: spi1-cs0 { 457*f126890aSEmmanuel Vadot rockchip,pins = <0 RK_PD7 1 &pcfg_pull_up>; 458*f126890aSEmmanuel Vadot }; 459*f126890aSEmmanuel Vadot spi1_rx: spi1-rx { 460*f126890aSEmmanuel Vadot rockchip,pins = <0 RK_PD4 1 &pcfg_pull_up>; 461*f126890aSEmmanuel Vadot }; 462*f126890aSEmmanuel Vadot spi1_tx: spi1-tx { 463*f126890aSEmmanuel Vadot rockchip,pins = <0 RK_PD5 1 &pcfg_pull_up>; 464*f126890aSEmmanuel Vadot }; 465*f126890aSEmmanuel Vadot spi1_cs1: spi1-cs1 { 466*f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>; 467*f126890aSEmmanuel Vadot }; 468*f126890aSEmmanuel Vadot }; 469*f126890aSEmmanuel Vadot 470*f126890aSEmmanuel Vadot uart0 { 471*f126890aSEmmanuel Vadot uart0_xfer: uart0-xfer { 472*f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up>, 473*f126890aSEmmanuel Vadot <1 RK_PA1 1 &pcfg_pull_none>; 474*f126890aSEmmanuel Vadot }; 475*f126890aSEmmanuel Vadot 476*f126890aSEmmanuel Vadot uart0_cts: uart0-cts { 477*f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PA2 1 &pcfg_pull_none>; 478*f126890aSEmmanuel Vadot }; 479*f126890aSEmmanuel Vadot 480*f126890aSEmmanuel Vadot uart0_rts: uart0-rts { 481*f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PA3 1 &pcfg_pull_none>; 482*f126890aSEmmanuel Vadot }; 483*f126890aSEmmanuel Vadot }; 484*f126890aSEmmanuel Vadot 485*f126890aSEmmanuel Vadot uart1 { 486*f126890aSEmmanuel Vadot uart1_xfer: uart1-xfer { 487*f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up>, 488*f126890aSEmmanuel Vadot <1 RK_PA5 1 &pcfg_pull_none>; 489*f126890aSEmmanuel Vadot }; 490*f126890aSEmmanuel Vadot 491*f126890aSEmmanuel Vadot uart1_cts: uart1-cts { 492*f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>; 493*f126890aSEmmanuel Vadot }; 494*f126890aSEmmanuel Vadot 495*f126890aSEmmanuel Vadot uart1_rts: uart1-rts { 496*f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PA7 1 &pcfg_pull_none>; 497*f126890aSEmmanuel Vadot }; 498*f126890aSEmmanuel Vadot }; 499*f126890aSEmmanuel Vadot 500*f126890aSEmmanuel Vadot uart2 { 501*f126890aSEmmanuel Vadot uart2_xfer: uart2-xfer { 502*f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PB0 1 &pcfg_pull_up>, 503*f126890aSEmmanuel Vadot <1 RK_PB1 1 &pcfg_pull_none>; 504*f126890aSEmmanuel Vadot }; 505*f126890aSEmmanuel Vadot /* no rts / cts for uart2 */ 506*f126890aSEmmanuel Vadot }; 507*f126890aSEmmanuel Vadot 508*f126890aSEmmanuel Vadot uart3 { 509*f126890aSEmmanuel Vadot uart3_xfer: uart3-xfer { 510*f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PB2 1 &pcfg_pull_up>, 511*f126890aSEmmanuel Vadot <1 RK_PB3 1 &pcfg_pull_none>; 512*f126890aSEmmanuel Vadot }; 513*f126890aSEmmanuel Vadot 514*f126890aSEmmanuel Vadot uart3_cts: uart3-cts { 515*f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none>; 516*f126890aSEmmanuel Vadot }; 517*f126890aSEmmanuel Vadot 518*f126890aSEmmanuel Vadot uart3_rts: uart3-rts { 519*f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PB5 1 &pcfg_pull_none>; 520*f126890aSEmmanuel Vadot }; 521*f126890aSEmmanuel Vadot }; 522*f126890aSEmmanuel Vadot 523*f126890aSEmmanuel Vadot sd0 { 524*f126890aSEmmanuel Vadot sd0_clk: sd0-clk { 525*f126890aSEmmanuel Vadot rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none>; 526*f126890aSEmmanuel Vadot }; 527*f126890aSEmmanuel Vadot 528*f126890aSEmmanuel Vadot sd0_cmd: sd0-cmd { 529*f126890aSEmmanuel Vadot rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>; 530*f126890aSEmmanuel Vadot }; 531*f126890aSEmmanuel Vadot 532*f126890aSEmmanuel Vadot sd0_cd: sd0-cd { 533*f126890aSEmmanuel Vadot rockchip,pins = <3 RK_PB0 1 &pcfg_pull_none>; 534*f126890aSEmmanuel Vadot }; 535*f126890aSEmmanuel Vadot 536*f126890aSEmmanuel Vadot sd0_wp: sd0-wp { 537*f126890aSEmmanuel Vadot rockchip,pins = <3 RK_PB1 1 &pcfg_pull_none>; 538*f126890aSEmmanuel Vadot }; 539*f126890aSEmmanuel Vadot 540*f126890aSEmmanuel Vadot sd0_pwr: sd0-pwr { 541*f126890aSEmmanuel Vadot rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>; 542*f126890aSEmmanuel Vadot }; 543*f126890aSEmmanuel Vadot 544*f126890aSEmmanuel Vadot sd0_bus1: sd0-bus-width1 { 545*f126890aSEmmanuel Vadot rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>; 546*f126890aSEmmanuel Vadot }; 547*f126890aSEmmanuel Vadot 548*f126890aSEmmanuel Vadot sd0_bus4: sd0-bus-width4 { 549*f126890aSEmmanuel Vadot rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>, 550*f126890aSEmmanuel Vadot <3 RK_PA5 1 &pcfg_pull_none>, 551*f126890aSEmmanuel Vadot <3 RK_PA6 1 &pcfg_pull_none>, 552*f126890aSEmmanuel Vadot <3 RK_PA7 1 &pcfg_pull_none>; 553*f126890aSEmmanuel Vadot }; 554*f126890aSEmmanuel Vadot }; 555*f126890aSEmmanuel Vadot 556*f126890aSEmmanuel Vadot sd1 { 557*f126890aSEmmanuel Vadot sd1_clk: sd1-clk { 558*f126890aSEmmanuel Vadot rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>; 559*f126890aSEmmanuel Vadot }; 560*f126890aSEmmanuel Vadot 561*f126890aSEmmanuel Vadot sd1_cmd: sd1-cmd { 562*f126890aSEmmanuel Vadot rockchip,pins = <3 RK_PC0 1 &pcfg_pull_none>; 563*f126890aSEmmanuel Vadot }; 564*f126890aSEmmanuel Vadot 565*f126890aSEmmanuel Vadot sd1_cd: sd1-cd { 566*f126890aSEmmanuel Vadot rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>; 567*f126890aSEmmanuel Vadot }; 568*f126890aSEmmanuel Vadot 569*f126890aSEmmanuel Vadot sd1_wp: sd1-wp { 570*f126890aSEmmanuel Vadot rockchip,pins = <3 RK_PC7 1 &pcfg_pull_none>; 571*f126890aSEmmanuel Vadot }; 572*f126890aSEmmanuel Vadot 573*f126890aSEmmanuel Vadot sd1_bus1: sd1-bus-width1 { 574*f126890aSEmmanuel Vadot rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>; 575*f126890aSEmmanuel Vadot }; 576*f126890aSEmmanuel Vadot 577*f126890aSEmmanuel Vadot sd1_bus4: sd1-bus-width4 { 578*f126890aSEmmanuel Vadot rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>, 579*f126890aSEmmanuel Vadot <3 RK_PC2 1 &pcfg_pull_none>, 580*f126890aSEmmanuel Vadot <3 RK_PC3 1 &pcfg_pull_none>, 581*f126890aSEmmanuel Vadot <3 RK_PC4 1 &pcfg_pull_none>; 582*f126890aSEmmanuel Vadot }; 583*f126890aSEmmanuel Vadot }; 584*f126890aSEmmanuel Vadot 585*f126890aSEmmanuel Vadot i2s0 { 586*f126890aSEmmanuel Vadot i2s0_bus: i2s0-bus { 587*f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>, 588*f126890aSEmmanuel Vadot <1 RK_PC1 1 &pcfg_pull_none>, 589*f126890aSEmmanuel Vadot <1 RK_PC2 1 &pcfg_pull_none>, 590*f126890aSEmmanuel Vadot <1 RK_PC3 1 &pcfg_pull_none>, 591*f126890aSEmmanuel Vadot <1 RK_PC4 1 &pcfg_pull_none>, 592*f126890aSEmmanuel Vadot <1 RK_PC5 1 &pcfg_pull_none>; 593*f126890aSEmmanuel Vadot }; 594*f126890aSEmmanuel Vadot }; 595*f126890aSEmmanuel Vadot 596*f126890aSEmmanuel Vadot spdif { 597*f126890aSEmmanuel Vadot spdif_tx: spdif-tx { 598*f126890aSEmmanuel Vadot rockchip,pins = <1 RK_PB6 1 &pcfg_pull_none>; 599*f126890aSEmmanuel Vadot }; 600*f126890aSEmmanuel Vadot }; 601*f126890aSEmmanuel Vadot }; 602*f126890aSEmmanuel Vadot}; 603*f126890aSEmmanuel Vadot 604*f126890aSEmmanuel Vadot&emac { 605*f126890aSEmmanuel Vadot compatible = "rockchip,rk3188-emac"; 606*f126890aSEmmanuel Vadot}; 607*f126890aSEmmanuel Vadot 608*f126890aSEmmanuel Vadot&global_timer { 609*f126890aSEmmanuel Vadot interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 610*f126890aSEmmanuel Vadot}; 611*f126890aSEmmanuel Vadot 612*f126890aSEmmanuel Vadot&local_timer { 613*f126890aSEmmanuel Vadot interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 614*f126890aSEmmanuel Vadot}; 615*f126890aSEmmanuel Vadot 616*f126890aSEmmanuel Vadot&gpu { 617*f126890aSEmmanuel Vadot compatible = "rockchip,rk3188-mali", "arm,mali-400"; 618*f126890aSEmmanuel Vadot interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 619*f126890aSEmmanuel Vadot <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 620*f126890aSEmmanuel Vadot <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 621*f126890aSEmmanuel Vadot <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 622*f126890aSEmmanuel Vadot <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 623*f126890aSEmmanuel Vadot <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 624*f126890aSEmmanuel Vadot <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 625*f126890aSEmmanuel Vadot <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 626*f126890aSEmmanuel Vadot <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 627*f126890aSEmmanuel Vadot <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 628*f126890aSEmmanuel Vadot interrupt-names = "gp", 629*f126890aSEmmanuel Vadot "gpmmu", 630*f126890aSEmmanuel Vadot "pp0", 631*f126890aSEmmanuel Vadot "ppmmu0", 632*f126890aSEmmanuel Vadot "pp1", 633*f126890aSEmmanuel Vadot "ppmmu1", 634*f126890aSEmmanuel Vadot "pp2", 635*f126890aSEmmanuel Vadot "ppmmu2", 636*f126890aSEmmanuel Vadot "pp3", 637*f126890aSEmmanuel Vadot "ppmmu3"; 638*f126890aSEmmanuel Vadot power-domains = <&power RK3188_PD_GPU>; 639*f126890aSEmmanuel Vadot}; 640*f126890aSEmmanuel Vadot 641*f126890aSEmmanuel Vadot&grf { 642*f126890aSEmmanuel Vadot compatible = "rockchip,rk3188-grf", "syscon", "simple-mfd"; 643*f126890aSEmmanuel Vadot 644*f126890aSEmmanuel Vadot io_domains: io-domains { 645*f126890aSEmmanuel Vadot compatible = "rockchip,rk3188-io-voltage-domain"; 646*f126890aSEmmanuel Vadot status = "disabled"; 647*f126890aSEmmanuel Vadot }; 648*f126890aSEmmanuel Vadot 649*f126890aSEmmanuel Vadot usbphy: usbphy { 650*f126890aSEmmanuel Vadot compatible = "rockchip,rk3188-usb-phy"; 651*f126890aSEmmanuel Vadot #address-cells = <1>; 652*f126890aSEmmanuel Vadot #size-cells = <0>; 653*f126890aSEmmanuel Vadot status = "disabled"; 654*f126890aSEmmanuel Vadot 655*f126890aSEmmanuel Vadot usbphy0: usb-phy@10c { 656*f126890aSEmmanuel Vadot reg = <0x10c>; 657*f126890aSEmmanuel Vadot clocks = <&cru SCLK_OTGPHY0>; 658*f126890aSEmmanuel Vadot clock-names = "phyclk"; 659*f126890aSEmmanuel Vadot #clock-cells = <0>; 660*f126890aSEmmanuel Vadot #phy-cells = <0>; 661*f126890aSEmmanuel Vadot }; 662*f126890aSEmmanuel Vadot 663*f126890aSEmmanuel Vadot usbphy1: usb-phy@11c { 664*f126890aSEmmanuel Vadot reg = <0x11c>; 665*f126890aSEmmanuel Vadot clocks = <&cru SCLK_OTGPHY1>; 666*f126890aSEmmanuel Vadot clock-names = "phyclk"; 667*f126890aSEmmanuel Vadot #clock-cells = <0>; 668*f126890aSEmmanuel Vadot #phy-cells = <0>; 669*f126890aSEmmanuel Vadot }; 670*f126890aSEmmanuel Vadot }; 671*f126890aSEmmanuel Vadot}; 672*f126890aSEmmanuel Vadot 673*f126890aSEmmanuel Vadot&i2c0 { 674*f126890aSEmmanuel Vadot compatible = "rockchip,rk3188-i2c"; 675*f126890aSEmmanuel Vadot pinctrl-names = "default"; 676*f126890aSEmmanuel Vadot pinctrl-0 = <&i2c0_xfer>; 677*f126890aSEmmanuel Vadot}; 678*f126890aSEmmanuel Vadot 679*f126890aSEmmanuel Vadot&i2c1 { 680*f126890aSEmmanuel Vadot compatible = "rockchip,rk3188-i2c"; 681*f126890aSEmmanuel Vadot pinctrl-names = "default"; 682*f126890aSEmmanuel Vadot pinctrl-0 = <&i2c1_xfer>; 683*f126890aSEmmanuel Vadot}; 684*f126890aSEmmanuel Vadot 685*f126890aSEmmanuel Vadot&i2c2 { 686*f126890aSEmmanuel Vadot compatible = "rockchip,rk3188-i2c"; 687*f126890aSEmmanuel Vadot pinctrl-names = "default"; 688*f126890aSEmmanuel Vadot pinctrl-0 = <&i2c2_xfer>; 689*f126890aSEmmanuel Vadot}; 690*f126890aSEmmanuel Vadot 691*f126890aSEmmanuel Vadot&i2c3 { 692*f126890aSEmmanuel Vadot compatible = "rockchip,rk3188-i2c"; 693*f126890aSEmmanuel Vadot pinctrl-names = "default"; 694*f126890aSEmmanuel Vadot pinctrl-0 = <&i2c3_xfer>; 695*f126890aSEmmanuel Vadot}; 696*f126890aSEmmanuel Vadot 697*f126890aSEmmanuel Vadot&i2c4 { 698*f126890aSEmmanuel Vadot compatible = "rockchip,rk3188-i2c"; 699*f126890aSEmmanuel Vadot pinctrl-names = "default"; 700*f126890aSEmmanuel Vadot pinctrl-0 = <&i2c4_xfer>; 701*f126890aSEmmanuel Vadot}; 702*f126890aSEmmanuel Vadot 703*f126890aSEmmanuel Vadot&pmu { 704*f126890aSEmmanuel Vadot power: power-controller { 705*f126890aSEmmanuel Vadot compatible = "rockchip,rk3188-power-controller"; 706*f126890aSEmmanuel Vadot #power-domain-cells = <1>; 707*f126890aSEmmanuel Vadot #address-cells = <1>; 708*f126890aSEmmanuel Vadot #size-cells = <0>; 709*f126890aSEmmanuel Vadot 710*f126890aSEmmanuel Vadot power-domain@RK3188_PD_VIO { 711*f126890aSEmmanuel Vadot reg = <RK3188_PD_VIO>; 712*f126890aSEmmanuel Vadot clocks = <&cru ACLK_LCDC0>, 713*f126890aSEmmanuel Vadot <&cru ACLK_LCDC1>, 714*f126890aSEmmanuel Vadot <&cru DCLK_LCDC0>, 715*f126890aSEmmanuel Vadot <&cru DCLK_LCDC1>, 716*f126890aSEmmanuel Vadot <&cru HCLK_LCDC0>, 717*f126890aSEmmanuel Vadot <&cru HCLK_LCDC1>, 718*f126890aSEmmanuel Vadot <&cru SCLK_CIF0>, 719*f126890aSEmmanuel Vadot <&cru ACLK_CIF0>, 720*f126890aSEmmanuel Vadot <&cru HCLK_CIF0>, 721*f126890aSEmmanuel Vadot <&cru ACLK_IPP>, 722*f126890aSEmmanuel Vadot <&cru HCLK_IPP>, 723*f126890aSEmmanuel Vadot <&cru ACLK_RGA>, 724*f126890aSEmmanuel Vadot <&cru HCLK_RGA>; 725*f126890aSEmmanuel Vadot pm_qos = <&qos_lcdc0>, 726*f126890aSEmmanuel Vadot <&qos_lcdc1>, 727*f126890aSEmmanuel Vadot <&qos_cif0>, 728*f126890aSEmmanuel Vadot <&qos_ipp>, 729*f126890aSEmmanuel Vadot <&qos_rga>; 730*f126890aSEmmanuel Vadot #power-domain-cells = <0>; 731*f126890aSEmmanuel Vadot }; 732*f126890aSEmmanuel Vadot 733*f126890aSEmmanuel Vadot power-domain@RK3188_PD_VIDEO { 734*f126890aSEmmanuel Vadot reg = <RK3188_PD_VIDEO>; 735*f126890aSEmmanuel Vadot clocks = <&cru ACLK_VDPU>, 736*f126890aSEmmanuel Vadot <&cru ACLK_VEPU>, 737*f126890aSEmmanuel Vadot <&cru HCLK_VDPU>, 738*f126890aSEmmanuel Vadot <&cru HCLK_VEPU>; 739*f126890aSEmmanuel Vadot pm_qos = <&qos_vpu>; 740*f126890aSEmmanuel Vadot #power-domain-cells = <0>; 741*f126890aSEmmanuel Vadot }; 742*f126890aSEmmanuel Vadot 743*f126890aSEmmanuel Vadot power-domain@RK3188_PD_GPU { 744*f126890aSEmmanuel Vadot reg = <RK3188_PD_GPU>; 745*f126890aSEmmanuel Vadot clocks = <&cru ACLK_GPU>; 746*f126890aSEmmanuel Vadot pm_qos = <&qos_gpu>; 747*f126890aSEmmanuel Vadot #power-domain-cells = <0>; 748*f126890aSEmmanuel Vadot }; 749*f126890aSEmmanuel Vadot }; 750*f126890aSEmmanuel Vadot}; 751*f126890aSEmmanuel Vadot 752*f126890aSEmmanuel Vadot&pwm0 { 753*f126890aSEmmanuel Vadot pinctrl-names = "default"; 754*f126890aSEmmanuel Vadot pinctrl-0 = <&pwm0_out>; 755*f126890aSEmmanuel Vadot}; 756*f126890aSEmmanuel Vadot 757*f126890aSEmmanuel Vadot&pwm1 { 758*f126890aSEmmanuel Vadot pinctrl-names = "default"; 759*f126890aSEmmanuel Vadot pinctrl-0 = <&pwm1_out>; 760*f126890aSEmmanuel Vadot}; 761*f126890aSEmmanuel Vadot 762*f126890aSEmmanuel Vadot&pwm2 { 763*f126890aSEmmanuel Vadot pinctrl-names = "default"; 764*f126890aSEmmanuel Vadot pinctrl-0 = <&pwm2_out>; 765*f126890aSEmmanuel Vadot}; 766*f126890aSEmmanuel Vadot 767*f126890aSEmmanuel Vadot&pwm3 { 768*f126890aSEmmanuel Vadot pinctrl-names = "default"; 769*f126890aSEmmanuel Vadot pinctrl-0 = <&pwm3_out>; 770*f126890aSEmmanuel Vadot}; 771*f126890aSEmmanuel Vadot 772*f126890aSEmmanuel Vadot&spi0 { 773*f126890aSEmmanuel Vadot compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi"; 774*f126890aSEmmanuel Vadot pinctrl-names = "default"; 775*f126890aSEmmanuel Vadot pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 776*f126890aSEmmanuel Vadot}; 777*f126890aSEmmanuel Vadot 778*f126890aSEmmanuel Vadot&spi1 { 779*f126890aSEmmanuel Vadot compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi"; 780*f126890aSEmmanuel Vadot pinctrl-names = "default"; 781*f126890aSEmmanuel Vadot pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 782*f126890aSEmmanuel Vadot}; 783*f126890aSEmmanuel Vadot 784*f126890aSEmmanuel Vadot&uart0 { 785*f126890aSEmmanuel Vadot compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; 786*f126890aSEmmanuel Vadot pinctrl-names = "default"; 787*f126890aSEmmanuel Vadot pinctrl-0 = <&uart0_xfer>; 788*f126890aSEmmanuel Vadot}; 789*f126890aSEmmanuel Vadot 790*f126890aSEmmanuel Vadot&uart1 { 791*f126890aSEmmanuel Vadot compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; 792*f126890aSEmmanuel Vadot pinctrl-names = "default"; 793*f126890aSEmmanuel Vadot pinctrl-0 = <&uart1_xfer>; 794*f126890aSEmmanuel Vadot}; 795*f126890aSEmmanuel Vadot 796*f126890aSEmmanuel Vadot&uart2 { 797*f126890aSEmmanuel Vadot compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; 798*f126890aSEmmanuel Vadot pinctrl-names = "default"; 799*f126890aSEmmanuel Vadot pinctrl-0 = <&uart2_xfer>; 800*f126890aSEmmanuel Vadot}; 801*f126890aSEmmanuel Vadot 802*f126890aSEmmanuel Vadot&uart3 { 803*f126890aSEmmanuel Vadot compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; 804*f126890aSEmmanuel Vadot pinctrl-names = "default"; 805*f126890aSEmmanuel Vadot pinctrl-0 = <&uart3_xfer>; 806*f126890aSEmmanuel Vadot}; 807*f126890aSEmmanuel Vadot 808*f126890aSEmmanuel Vadot&vpu { 809*f126890aSEmmanuel Vadot compatible = "rockchip,rk3188-vpu", "rockchip,rk3066-vpu"; 810*f126890aSEmmanuel Vadot power-domains = <&power RK3188_PD_VIDEO>; 811*f126890aSEmmanuel Vadot}; 812*f126890aSEmmanuel Vadot 813*f126890aSEmmanuel Vadot&wdt { 814*f126890aSEmmanuel Vadot compatible = "rockchip,rk3188-wdt", "snps,dw-wdt"; 815*f126890aSEmmanuel Vadot}; 816