1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/*
7 * AM335x Starter Kit
8 * http://www.ti.com/tool/tmdssk3358
9 */
10
11/dts-v1/;
12
13#include "am33xx.dtsi"
14#include <dt-bindings/pwm/pwm.h>
15#include <dt-bindings/interrupt-controller/irq.h>
16
17/ {
18	model = "TI AM335x EVM-SK";
19	compatible = "ti,am335x-evmsk", "ti,am33xx";
20
21	cpus {
22		cpu@0 {
23			cpu0-supply = <&vdd1_reg>;
24		};
25	};
26
27	memory@80000000 {
28		device_type = "memory";
29		reg = <0x80000000 0x10000000>; /* 256 MB */
30	};
31
32	chosen {
33		stdout-path = &uart0;
34	};
35
36	vbat: fixedregulator0 {
37		compatible = "regulator-fixed";
38		regulator-name = "vbat";
39		regulator-min-microvolt = <5000000>;
40		regulator-max-microvolt = <5000000>;
41		regulator-boot-on;
42	};
43
44	lis3_reg: fixedregulator1 {
45		compatible = "regulator-fixed";
46		regulator-name = "lis3_reg";
47		regulator-boot-on;
48	};
49
50	wl12xx_vmmc: fixedregulator2 {
51		pinctrl-names = "default";
52		pinctrl-0 = <&wl12xx_gpio>;
53		compatible = "regulator-fixed";
54		regulator-name = "vwl1271";
55		regulator-min-microvolt = <1800000>;
56		regulator-max-microvolt = <1800000>;
57		gpio = <&gpio1 29 0>;
58		startup-delay-us = <70000>;
59		enable-active-high;
60	};
61
62	vtt_fixed: fixedregulator3 {
63		compatible = "regulator-fixed";
64		regulator-name = "vtt";
65		regulator-min-microvolt = <1500000>;
66		regulator-max-microvolt = <1500000>;
67		gpio = <&gpio0 7 GPIO_ACTIVE_HIGH>;
68		regulator-always-on;
69		regulator-boot-on;
70		enable-active-high;
71	};
72
73	/* TPS79518 */
74	v1_8d_reg: fixedregulator-v1_8d {
75		compatible = "regulator-fixed";
76		regulator-name = "v1_8d";
77		vin-supply = <&vbat>;
78		regulator-min-microvolt = <1800000>;
79		regulator-max-microvolt = <1800000>;
80	};
81
82	/* TPS78633 */
83	v3_3d_reg: fixedregulator-v3_3d {
84		compatible = "regulator-fixed";
85		regulator-name = "v3_3d";
86		vin-supply = <&vbat>;
87		regulator-min-microvolt = <3300000>;
88		regulator-max-microvolt = <3300000>;
89	};
90
91	leds {
92		pinctrl-names = "default";
93		pinctrl-0 = <&user_leds_s0>;
94
95		compatible = "gpio-leds";
96
97		led1 {
98			label = "evmsk:green:usr0";
99			gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
100			default-state = "off";
101		};
102
103		led2 {
104			label = "evmsk:green:usr1";
105			gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
106			default-state = "off";
107		};
108
109		led3 {
110			label = "evmsk:green:mmc0";
111			gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
112			linux,default-trigger = "mmc0";
113			default-state = "off";
114		};
115
116		led4 {
117			label = "evmsk:green:heartbeat";
118			gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
119			linux,default-trigger = "heartbeat";
120			default-state = "off";
121		};
122	};
123
124	gpio_buttons: gpio_buttons0 {
125		compatible = "gpio-keys";
126		#address-cells = <1>;
127		#size-cells = <0>;
128
129		switch1 {
130			label = "button0";
131			linux,code = <0x100>;
132			gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
133		};
134
135		switch2 {
136			label = "button1";
137			linux,code = <0x101>;
138			gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
139		};
140
141		switch3 {
142			label = "button2";
143			linux,code = <0x102>;
144			gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>;
145			wakeup-source;
146		};
147
148		switch4 {
149			label = "button3";
150			linux,code = <0x103>;
151			gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
152		};
153	};
154
155	lcd_bl: backlight {
156		compatible = "pwm-backlight";
157		pwms = <&ecap2 0 50000 PWM_POLARITY_INVERTED>;
158		brightness-levels = <0 58 61 66 75 90 125 170 255>;
159		default-brightness-level = <8>;
160	};
161
162	sound {
163		compatible = "simple-audio-card";
164		simple-audio-card,name = "AM335x-EVMSK";
165		simple-audio-card,widgets =
166			"Headphone", "Headphone Jack";
167		simple-audio-card,routing =
168			"Headphone Jack",	"HPLOUT",
169			"Headphone Jack",	"HPROUT";
170		simple-audio-card,format = "dsp_b";
171		simple-audio-card,bitclock-master = <&sound_master>;
172		simple-audio-card,frame-master = <&sound_master>;
173		simple-audio-card,bitclock-inversion;
174
175		simple-audio-card,cpu {
176			sound-dai = <&mcasp1>;
177		};
178
179		sound_master: simple-audio-card,codec {
180			sound-dai = <&tlv320aic3106>;
181			system-clock-frequency = <24000000>;
182		};
183	};
184
185	panel {
186		compatible = "newhaven,nhd-4.3-480272ef-atxl";
187
188		pinctrl-names = "default", "sleep";
189		pinctrl-0 = <&lcd_pins_default>;
190		pinctrl-1 = <&lcd_pins_sleep>;
191		backlight = <&lcd_bl>;
192
193		port {
194			panel_0: endpoint {
195				remote-endpoint = <&lcdc_0>;
196			};
197		};
198	};
199};
200
201&am33xx_pinmux {
202	pinctrl-names = "default";
203	pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>;
204
205	lcd_pins_default: lcd-default-pins {
206		pinctrl-single,pins = <
207			AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1)	/* gpmc_ad8.lcd_data23 */
208			AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1)	/* gpmc_ad9.lcd_data22 */
209			AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1)	/* gpmc_ad10.lcd_data21 */
210			AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1)	/* gpmc_ad11.lcd_data20 */
211			AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1)	/* gpmc_ad12.lcd_data19 */
212			AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1)	/* gpmc_ad13.lcd_data18 */
213			AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1)	/* gpmc_ad14.lcd_data17 */
214			AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1)	/* gpmc_ad15.lcd_data16 */
215			AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
216			AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
217			AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
218			AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
219			AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
220			AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
221			AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
222			AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
223			AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
224			AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
225			AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
226			AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
227			AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
228			AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
229			AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
230			AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
231			AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0)
232			AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0)
233			AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0)
234			AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0)
235		>;
236	};
237
238	lcd_pins_sleep: lcd-sleep-pins {
239		pinctrl-single,pins = <
240			AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ad8.lcd_data23 */
241			AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ad9.lcd_data22 */
242			AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ad10.lcd_data21 */
243			AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ad11.lcd_data20 */
244			AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ad12.lcd_data19 */
245			AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ad13.lcd_data18 */
246			AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ad14.lcd_data17 */
247			AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ad15.lcd_data16 */
248			AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PULL_DISABLE, MUX_MODE7)
249			AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PULL_DISABLE, MUX_MODE7)
250			AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PULL_DISABLE, MUX_MODE7)
251			AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PULL_DISABLE, MUX_MODE7)
252			AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PULL_DISABLE, MUX_MODE7)
253			AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PULL_DISABLE, MUX_MODE7)
254			AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PULL_DISABLE, MUX_MODE7)
255			AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PULL_DISABLE, MUX_MODE7)
256			AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PULL_DISABLE, MUX_MODE7)
257			AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PULL_DISABLE, MUX_MODE7)
258			AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PULL_DISABLE, MUX_MODE7)
259			AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PULL_DISABLE, MUX_MODE7)
260			AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PULL_DISABLE, MUX_MODE7)
261			AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PULL_DISABLE, MUX_MODE7)
262			AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PULL_DISABLE, MUX_MODE7)
263			AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PULL_DISABLE, MUX_MODE7)
264			AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)
265			AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)
266			AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
267			AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
268		>;
269	};
270
271
272	user_leds_s0: user-leds-s0-pins {
273		pinctrl-single,pins = <
274			AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ad4.gpio1_4 */
275			AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ad5.gpio1_5 */
276			AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ad6.gpio1_6 */
277			AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ad7.gpio1_7 */
278		>;
279	};
280
281	gpio_keys_s0: gpio-keys-s0-pins {
282		pinctrl-single,pins = <
283			AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_oen_ren.gpio2_3 */
284			AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_advn_ale.gpio2_2 */
285			AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_wait0.gpio0_30 */
286			AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_ben0_cle.gpio2_5 */
287		>;
288	};
289
290	i2c0_pins: i2c0-pins {
291		pinctrl-single,pins = <
292			AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
293			AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
294		>;
295	};
296
297	uart0_pins: uart0-pins {
298		pinctrl-single,pins = <
299			AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
300			AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
301		>;
302	};
303
304	clkout2_pin: clkout2-pins {
305		pinctrl-single,pins = <
306			AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3)	/* xdma_event_intr1.clkout2 */
307		>;
308	};
309
310	ecap2_pins: backlight-pins {
311		pinctrl-single,pins = <
312			AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, 0x0, MUX_MODE4)	/* mcasp0_ahclkr.ecap2_in_pwm2_out */
313		>;
314	};
315
316	cpsw_default: cpsw-default-pins {
317		pinctrl-single,pins = <
318			/* Slave 1 */
319			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txen.rgmii1_tctl */
320			AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxdv.rgmii1_rctl */
321			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txd3.rgmii1_td3 */
322			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txd2.rgmii1_td2 */
323			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txd1.rgmii1_td1 */
324			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txd0.rgmii1_td0 */
325			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txclk.rgmii1_tclk */
326			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxclk.rgmii1_rclk */
327			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxd3.rgmii1_rd3 */
328			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxd2.rgmii1_rd2 */
329			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxd1.rgmii1_rd1 */
330			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxd0.rgmii1_rd0 */
331
332			/* Slave 2 */
333			AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a0.rgmii2_tctl */
334			AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a1.rgmii2_rctl */
335			AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a2.rgmii2_td3 */
336			AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a3.rgmii2_td2 */
337			AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a4.rgmii2_td1 */
338			AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a5.rgmii2_td0 */
339			AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a6.rgmii2_tclk */
340			AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a7.rgmii2_rclk */
341			AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a8.rgmii2_rd3 */
342			AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a9.rgmii2_rd2 */
343			AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a10.rgmii2_rd1 */
344			AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a11.rgmii2_rd0 */
345		>;
346	};
347
348	cpsw_sleep: cpsw-sleep-pins {
349		pinctrl-single,pins = <
350			/* Slave 1 reset value */
351			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
352			AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
353			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
354			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
355			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
356			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
357			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
358			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
359			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
360			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
361			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
362			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
363
364			/* Slave 2 reset value*/
365			AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7)
366			AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7)
367			AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7)
368			AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7)
369			AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7)
370			AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7)
371			AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7)
372			AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7)
373			AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7)
374			AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7)
375			AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7)
376			AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7)
377		>;
378	};
379
380	davinci_mdio_default: davinci-mdio-default-pins {
381		pinctrl-single,pins = <
382			/* MDIO */
383			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
384			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
385		>;
386	};
387
388	davinci_mdio_sleep: davinci-mdio-sleep-pins {
389		pinctrl-single,pins = <
390			/* MDIO reset value */
391			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
392			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
393		>;
394	};
395
396	mmc1_pins: mmc1-pins {
397		pinctrl-single,pins = <
398			AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) 		/* spi0_cs1.gpio0_6 */
399			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
400			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
401			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
402			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
403			AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
404			AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
405			AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT, MUX_MODE4)		/* mcasp0_aclkr.mmc0_sdwp */
406		>;
407	};
408
409	mcasp1_pins: mcasp1-pins {
410		pinctrl-single,pins = <
411			AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
412			AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
413			AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* mii1_col.mcasp1_axr2 */
414			AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
415		>;
416	};
417
418	mcasp1_pins_sleep: mcasp1-sleep-pins {
419		pinctrl-single,pins = <
420			AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7)
421			AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
422			AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7)
423			AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
424		>;
425	};
426
427	mmc2_pins: mmc2-pins {
428		pinctrl-single,pins = <
429			AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */
430			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */
431			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
432			AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
433			AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
434			AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
435			AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
436		>;
437	};
438
439	wl12xx_gpio: wl12xx-gpio-pins {
440		pinctrl-single,pins = <
441			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_csn0.gpio1_29 */
442		>;
443	};
444};
445
446&uart0 {
447	pinctrl-names = "default";
448	pinctrl-0 = <&uart0_pins>;
449
450	status = "okay";
451};
452
453&i2c0 {
454	pinctrl-names = "default";
455	pinctrl-0 = <&i2c0_pins>;
456
457	status = "okay";
458	clock-frequency = <400000>;
459
460	tps: tps@2d {
461		reg = <0x2d>;
462	};
463
464	lis331dlh: lis331dlh@18 {
465		compatible = "st,lis331dlh", "st,lis3lv02d";
466		reg = <0x18>;
467		Vdd-supply = <&lis3_reg>;
468		Vdd_IO-supply = <&lis3_reg>;
469
470		st,click-single-x;
471		st,click-single-y;
472		st,click-single-z;
473		st,click-thresh-x = <10>;
474		st,click-thresh-y = <10>;
475		st,click-thresh-z = <10>;
476		st,irq1-click;
477		st,irq2-click;
478		st,wakeup-x-lo;
479		st,wakeup-x-hi;
480		st,wakeup-y-lo;
481		st,wakeup-y-hi;
482		st,wakeup-z-lo;
483		st,wakeup-z-hi;
484		st,min-limit-x = <120>;
485		st,min-limit-y = <120>;
486		st,min-limit-z = <140>;
487		st,max-limit-x = <550>;
488		st,max-limit-y = <550>;
489		st,max-limit-z = <750>;
490	};
491
492	tlv320aic3106: tlv320aic3106@1b {
493		#sound-dai-cells = <0>;
494		compatible = "ti,tlv320aic3106";
495		reg = <0x1b>;
496		status = "okay";
497
498		/* Regulators */
499		AVDD-supply = <&v3_3d_reg>;
500		IOVDD-supply = <&v3_3d_reg>;
501		DRVDD-supply = <&v3_3d_reg>;
502		DVDD-supply = <&v1_8d_reg>;
503	};
504};
505
506&usb1 {
507	dr_mode = "host";
508};
509
510&epwmss2 {
511	status = "okay";
512
513	ecap2: pwm@100 {
514		status = "okay";
515		pinctrl-names = "default";
516		pinctrl-0 = <&ecap2_pins>;
517	};
518};
519
520#include "../../tps65910.dtsi"
521
522&tps {
523	vcc1-supply = <&vbat>;
524	vcc2-supply = <&vbat>;
525	vcc3-supply = <&vbat>;
526	vcc4-supply = <&vbat>;
527	vcc5-supply = <&vbat>;
528	vcc6-supply = <&vbat>;
529	vcc7-supply = <&vbat>;
530	vccio-supply = <&vbat>;
531
532	regulators {
533		vrtc_reg: regulator@0 {
534			regulator-always-on;
535		};
536
537		vio_reg: regulator@1 {
538			regulator-always-on;
539		};
540
541		vdd1_reg: regulator@2 {
542			/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
543			regulator-name = "vdd_mpu";
544			regulator-min-microvolt = <912500>;
545			regulator-max-microvolt = <1351500>;
546			regulator-boot-on;
547			regulator-always-on;
548		};
549
550		vdd2_reg: regulator@3 {
551			/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
552			regulator-name = "vdd_core";
553			regulator-min-microvolt = <912500>;
554			regulator-max-microvolt = <1150000>;
555			regulator-boot-on;
556			regulator-always-on;
557		};
558
559		vdd3_reg: regulator@4 {
560			regulator-always-on;
561		};
562
563		vdig1_reg: regulator@5 {
564			regulator-always-on;
565		};
566
567		vdig2_reg: regulator@6 {
568			regulator-always-on;
569		};
570
571		vpll_reg: regulator@7 {
572			regulator-always-on;
573		};
574
575		vdac_reg: regulator@8 {
576			regulator-always-on;
577		};
578
579		vaux1_reg: regulator@9 {
580			regulator-always-on;
581		};
582
583		vaux2_reg: regulator@10 {
584			regulator-always-on;
585		};
586
587		vaux33_reg: regulator@11 {
588			regulator-always-on;
589		};
590
591		vmmc_reg: regulator@12 {
592			regulator-min-microvolt = <1800000>;
593			regulator-max-microvolt = <3300000>;
594			regulator-always-on;
595		};
596	};
597};
598
599&mac_sw {
600	pinctrl-names = "default", "sleep";
601	pinctrl-0 = <&cpsw_default>;
602	pinctrl-1 = <&cpsw_sleep>;
603	status = "okay";
604};
605
606&davinci_mdio_sw {
607	pinctrl-names = "default", "sleep";
608	pinctrl-0 = <&davinci_mdio_default>;
609	pinctrl-1 = <&davinci_mdio_sleep>;
610
611	ethphy0: ethernet-phy@0 {
612		reg = <0>;
613	};
614
615	ethphy1: ethernet-phy@1 {
616		reg = <1>;
617	};
618};
619
620&cpsw_port1 {
621	phy-handle = <&ethphy0>;
622	phy-mode = "rgmii-id";
623	ti,dual-emac-pvid = <1>;
624};
625
626&cpsw_port2 {
627	phy-handle = <&ethphy1>;
628	phy-mode = "rgmii-id";
629	ti,dual-emac-pvid = <2>;
630};
631
632&mmc1 {
633	status = "okay";
634	vmmc-supply = <&vmmc_reg>;
635	bus-width = <4>;
636	pinctrl-names = "default";
637	pinctrl-0 = <&mmc1_pins>;
638	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
639};
640
641&sham {
642	status = "okay";
643};
644
645&aes {
646	status = "okay";
647};
648
649&gpio0_target {
650	ti,no-reset-on-init;
651};
652
653&mmc2 {
654	status = "okay";
655	vmmc-supply = <&wl12xx_vmmc>;
656	non-removable;
657	bus-width = <4>;
658	cap-power-off-card;
659	keep-power-in-suspend;
660	pinctrl-names = "default";
661	pinctrl-0 = <&mmc2_pins>;
662
663	#address-cells = <1>;
664	#size-cells = <0>;
665	wlcore: wlcore@2 {
666		compatible = "ti,wl1271";
667		reg = <2>;
668		interrupt-parent = <&gpio0>;
669		interrupts = <31 IRQ_TYPE_EDGE_RISING>; /* gpio 31 */
670		ref-clock-frequency = <38400000>;
671	};
672};
673
674&mcasp1 {
675	#sound-dai-cells = <0>;
676	pinctrl-names = "default", "sleep";
677	pinctrl-0 = <&mcasp1_pins>;
678	pinctrl-1 = <&mcasp1_pins_sleep>;
679
680	status = "okay";
681
682	op-mode = <0>;          /* MCASP_IIS_MODE */
683	tdm-slots = <2>;
684	/* 4 serializers */
685	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
686		0 0 1 2
687	>;
688	tx-num-evt = <32>;
689	rx-num-evt = <32>;
690};
691
692&tscadc {
693	status = "okay";
694	tsc {
695		ti,wires = <4>;
696		ti,x-plate-resistance = <200>;
697		ti,coordinate-readouts = <5>;
698		ti,wire-config = <0x00 0x11 0x22 0x33>;
699	};
700};
701
702&lcdc {
703	status = "okay";
704
705	blue-and-red-wiring = "crossed";
706
707	port {
708		lcdc_0: endpoint@0 {
709			remote-endpoint = <&panel_0>;
710		};
711	};
712};
713
714&rtc {
715	clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
716	clock-names = "ext-clk", "int-clk";
717};
718
719&pruss_tm {
720	status = "okay";
721};
722
723&wkup_m3_ipc {
724	firmware-name = "am335x-evm-scale-data.bin";
725};
726