1// SPDX-License-Identifier: GPL-2.0-only
2
3#include <dt-bindings/bus/ti-sysc.h>
4#include <dt-bindings/clock/dm816.h>
5#include <dt-bindings/gpio/gpio.h>
6#include <dt-bindings/pinctrl/omap.h>
7
8/ {
9	compatible = "ti,dm816";
10	interrupt-parent = <&intc>;
11	#address-cells = <1>;
12	#size-cells = <1>;
13	chosen { };
14
15	aliases {
16		i2c0 = &i2c1;
17		i2c1 = &i2c2;
18		serial0 = &uart1;
19		serial1 = &uart2;
20		serial2 = &uart3;
21		ethernet0 = &eth0;
22		ethernet1 = &eth1;
23	};
24
25	cpus {
26		#address-cells = <1>;
27		#size-cells = <0>;
28		cpu@0 {
29			compatible = "arm,cortex-a8";
30			device_type = "cpu";
31			reg = <0>;
32		};
33	};
34
35	pmu {
36		compatible = "arm,cortex-a8-pmu";
37		interrupts = <3>;
38	};
39
40	/*
41	 * The soc node represents the soc top level view. It is used for IPs
42	 * that are not memory mapped in the MPU view or for the MPU itself.
43	 */
44	soc {
45		compatible = "ti,omap-infra";
46		mpu {
47			compatible = "ti,omap3-mpu";
48			ti,hwmods = "mpu";
49		};
50	};
51
52	/*
53	 * XXX: Use a flat representation of the dm816x interconnect.
54	 * The real dm816x interconnect network is quite complex. Since
55	 * it will not bring real advantage to represent that in DT
56	 * for the moment, just use a fake OCP bus entry to represent
57	 * the whole bus hierarchy.
58	 */
59	ocp {
60		compatible = "simple-bus";
61		reg = <0x44000000 0x10000>;
62		interrupts = <9 10>;
63		#address-cells = <1>;
64		#size-cells = <1>;
65		ranges;
66
67		prcm: prcm@48180000 {
68			compatible = "ti,dm816-prcm", "simple-bus";
69			reg = <0x48180000 0x4000>;
70			#address-cells = <1>;
71			#size-cells = <1>;
72			ranges = <0 0x48180000 0x4000>;
73
74			prcm_clocks: clocks {
75				#address-cells = <1>;
76				#size-cells = <0>;
77			};
78
79			prcm_clockdomains: clockdomains {
80			};
81		};
82
83		scrm: scrm@48140000 {
84			compatible = "ti,dm816-scrm", "simple-bus";
85			reg = <0x48140000 0x21000>;
86			#address-cells = <1>;
87			#size-cells = <1>;
88			#pinctrl-cells = <1>;
89			ranges = <0 0x48140000 0x21000>;
90
91			dm816x_pinmux: pinmux@800 {
92				compatible = "pinctrl-single";
93				reg = <0x800 0x50a>;
94				#address-cells = <1>;
95				#size-cells = <0>;
96				#pinctrl-cells = <1>;
97				pinctrl-single,register-width = <16>;
98				pinctrl-single,function-mask = <0xf>;
99			};
100
101			/* Device Configuration Registers */
102			scm_conf: syscon@600 {
103				compatible = "syscon", "simple-bus";
104				reg = <0x600 0x110>;
105				#address-cells = <1>;
106				#size-cells = <1>;
107				ranges = <0 0x600 0x110>;
108
109				usb_phy0: usb-phy@20 {
110					compatible = "ti,dm8168-usb-phy";
111					reg = <0x20 0x8>;
112					reg-names = "phy";
113					clocks = <&main_fapll 6>;
114					clock-names = "refclk";
115					#phy-cells = <0>;
116					syscon = <&scm_conf>;
117				};
118
119				usb_phy1: usb-phy@28 {
120					compatible = "ti,dm8168-usb-phy";
121					reg = <0x28 0x8>;
122					reg-names = "phy";
123					clocks = <&main_fapll 6>;
124					clock-names = "refclk";
125					#phy-cells = <0>;
126					syscon = <&scm_conf>;
127				};
128			};
129
130			scrm_clocks: clocks {
131				#address-cells = <1>;
132				#size-cells = <0>;
133			};
134
135			scrm_clockdomains: clockdomains {
136			};
137		};
138
139		target-module@49000000 {
140			compatible = "ti,sysc-omap4", "ti,sysc";
141			reg = <0x49000000 0x4>;
142			reg-names = "rev";
143			clocks = <&alwon_clkctrl DM816_TPCC_CLKCTRL 0>;
144			clock-names = "fck";
145			#address-cells = <1>;
146			#size-cells = <1>;
147			ranges = <0x0 0x49000000 0x10000>;
148
149			edma: dma@0 {
150				compatible = "ti,edma3-tpcc";
151				reg = <0 0x10000>;
152				reg-names = "edma3_cc";
153				interrupts = <12 13 14>;
154				interrupt-names = "edma3_ccint", "edma3_mperr",
155						  "edma3_ccerrint";
156				dma-requests = <64>;
157				#dma-cells = <2>;
158
159				ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
160					   <&edma_tptc2 3>, <&edma_tptc3 0>;
161
162				ti,edma-memcpy-channels = <20 21>;
163			};
164		};
165
166		target-module@49800000 {
167			compatible = "ti,sysc-omap4", "ti,sysc";
168			reg = <0x49800000 0x4>,
169			      <0x49800010 0x4>;
170			reg-names = "rev", "sysc";
171			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
172			ti,sysc-midle = <SYSC_IDLE_FORCE>;
173			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
174					<SYSC_IDLE_SMART>;
175			clocks = <&alwon_clkctrl DM816_TPTC0_CLKCTRL 0>;
176			clock-names = "fck";
177			#address-cells = <1>;
178			#size-cells = <1>;
179			ranges = <0x0 0x49800000 0x100000>;
180
181			edma_tptc0: dma@0 {
182				compatible = "ti,edma3-tptc";
183				reg = <0 0x100000>;
184				interrupts = <112>;
185				interrupt-names = "edma3_tcerrint";
186			};
187		};
188
189		target-module@49900000 {
190			compatible = "ti,sysc-omap4", "ti,sysc";
191			reg = <0x49900000 0x4>,
192			      <0x49900010 0x4>;
193			reg-names = "rev", "sysc";
194			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
195			ti,sysc-midle = <SYSC_IDLE_FORCE>;
196			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
197					<SYSC_IDLE_SMART>;
198			clocks = <&alwon_clkctrl DM816_TPTC1_CLKCTRL 0>;
199			clock-names = "fck";
200			#address-cells = <1>;
201			#size-cells = <1>;
202			ranges = <0x0 0x49900000 0x100000>;
203
204			edma_tptc1: dma@0 {
205				compatible = "ti,edma3-tptc";
206				reg = <0 0x100000>;
207				interrupts = <113>;
208				interrupt-names = "edma3_tcerrint";
209			};
210		};
211
212		target-module@49a00000 {
213			compatible = "ti,sysc-omap4", "ti,sysc";
214			reg = <0x49a00000 0x4>,
215			      <0x49a00010 0x4>;
216			reg-names = "rev", "sysc";
217			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
218			ti,sysc-midle = <SYSC_IDLE_FORCE>;
219			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
220					<SYSC_IDLE_SMART>;
221			clocks = <&alwon_clkctrl DM816_TPTC2_CLKCTRL 0>;
222			clock-names = "fck";
223			#address-cells = <1>;
224			#size-cells = <1>;
225			ranges = <0x0 0x49a00000 0x100000>;
226
227			edma_tptc2: dma@0 {
228				compatible = "ti,edma3-tptc";
229				reg = <0 0x100000>;
230				interrupts = <114>;
231				interrupt-names = "edma3_tcerrint";
232			};
233		};
234
235		target-module@49b00000 {
236			compatible = "ti,sysc-omap4", "ti,sysc";
237			reg = <0x49b00000 0x4>,
238			      <0x49b00010 0x4>;
239			reg-names = "rev", "sysc";
240			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
241			ti,sysc-midle = <SYSC_IDLE_FORCE>;
242			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
243					<SYSC_IDLE_SMART>;
244			clocks = <&alwon_clkctrl DM816_TPTC3_CLKCTRL 0>;
245			clock-names = "fck";
246			#address-cells = <1>;
247			#size-cells = <1>;
248			ranges = <0x0 0x49b00000 0x100000>;
249
250			edma_tptc3: dma@0 {
251				compatible = "ti,edma3-tptc";
252				reg = <0 0x100000>;
253				interrupts = <115>;
254				interrupt-names = "edma3_tcerrint";
255			};
256		};
257
258		elm: elm@48080000 {
259			compatible = "ti,am3352-elm";
260			ti,hwmods = "elm";
261			reg = <0x48080000 0x2000>;
262			interrupts = <4>;
263		};
264
265		gpio1: gpio@48032000 {
266			compatible = "ti,omap4-gpio";
267			ti,hwmods = "gpio1";
268			ti,gpio-always-on;
269			reg = <0x48032000 0x1000>;
270			interrupts = <96>;
271			gpio-controller;
272			#gpio-cells = <2>;
273			interrupt-controller;
274			#interrupt-cells = <2>;
275		};
276
277		gpio2: gpio@4804c000 {
278			compatible = "ti,omap4-gpio";
279			ti,hwmods = "gpio2";
280			ti,gpio-always-on;
281			reg = <0x4804c000 0x1000>;
282			interrupts = <98>;
283			gpio-controller;
284			#gpio-cells = <2>;
285			interrupt-controller;
286			#interrupt-cells = <2>;
287		};
288
289		gpmc: gpmc@50000000 {
290			compatible = "ti,am3352-gpmc";
291			ti,hwmods = "gpmc";
292			reg = <0x50000000 0x2000>;
293			#address-cells = <2>;
294			#size-cells = <1>;
295			interrupts = <100>;
296			dmas = <&edma 52 0>;
297			dma-names = "rxtx";
298			gpmc,num-cs = <6>;
299			gpmc,num-waitpins = <2>;
300			interrupt-controller;
301			#interrupt-cells = <2>;
302			gpio-controller;
303			#gpio-cells = <2>;
304		};
305
306		i2c1: i2c@48028000 {
307			compatible = "ti,omap4-i2c";
308			ti,hwmods = "i2c1";
309			reg = <0x48028000 0x1000>;
310			#address-cells = <1>;
311			#size-cells = <0>;
312			interrupts = <70>;
313		};
314
315		i2c2: i2c@4802a000 {
316			compatible = "ti,omap4-i2c";
317			ti,hwmods = "i2c2";
318			reg = <0x4802a000 0x1000>;
319			#address-cells = <1>;
320			#size-cells = <0>;
321			interrupts = <71>;
322		};
323
324		intc: interrupt-controller@48200000 {
325			compatible = "ti,dm816-intc";
326			interrupt-controller;
327			#interrupt-cells = <1>;
328			reg = <0x48200000 0x1000>;
329		};
330
331		rtc: rtc@480c0000 {
332			compatible = "ti,am3352-rtc", "ti,da830-rtc";
333			reg = <0x480c0000 0x1000>;
334			interrupts = <75 76>;
335			ti,hwmods = "rtc";
336		};
337
338		mailbox: mailbox@480c8000 {
339			compatible = "ti,omap4-mailbox";
340			reg = <0x480c8000 0x2000>;
341			interrupts = <77>;
342			ti,hwmods = "mailbox";
343			#mbox-cells = <1>;
344			ti,mbox-num-users = <4>;
345			ti,mbox-num-fifos = <12>;
346			mbox_dsp: mbox-dsp {
347				ti,mbox-tx = <3 0 0>;
348				ti,mbox-rx = <0 0 0>;
349			};
350		};
351
352		spinbox: spinbox@480ca000 {
353			compatible = "ti,omap4-hwspinlock";
354			reg = <0x480ca000 0x2000>;
355			ti,hwmods = "spinbox";
356			#hwlock-cells = <1>;
357		};
358
359		mdio: mdio@4a100800 {
360			compatible = "ti,davinci_mdio";
361			#address-cells = <1>;
362			#size-cells = <0>;
363			reg = <0x4a100800 0x100>;
364			ti,hwmods = "davinci_mdio";
365			bus_freq = <1000000>;
366			phy0: ethernet-phy@0 {
367				reg = <1>;
368			};
369			phy1: ethernet-phy@1 {
370				reg = <2>;
371			};
372		};
373
374		eth0: ethernet@4a100000 {
375			compatible = "ti,dm816-emac";
376			ti,hwmods = "emac0";
377			reg = <0x4a100000 0x800
378			       0x4a100900 0x3700>;
379			clocks = <&sysclk24_ck>;
380			syscon = <&scm_conf>;
381			ti,davinci-ctrl-reg-offset = <0>;
382			ti,davinci-ctrl-mod-reg-offset = <0x900>;
383			ti,davinci-ctrl-ram-offset = <0x2000>;
384			ti,davinci-ctrl-ram-size = <0x2000>;
385			interrupts = <40 41 42 43>;
386			phy-handle = <&phy0>;
387		};
388
389		eth1: ethernet@4a120000 {
390			compatible = "ti,dm816-emac";
391			ti,hwmods = "emac1";
392			reg = <0x4a120000 0x4000>;
393			clocks = <&sysclk24_ck>;
394			syscon = <&scm_conf>;
395			ti,davinci-ctrl-reg-offset = <0>;
396			ti,davinci-ctrl-mod-reg-offset = <0x900>;
397			ti,davinci-ctrl-ram-offset = <0x2000>;
398			ti,davinci-ctrl-ram-size = <0x2000>;
399			interrupts = <44 45 46 47>;
400			phy-handle = <&phy1>;
401		};
402
403		sata: sata@4a140000 {
404			compatible = "ti,dm816-ahci";
405			reg = <0x4a140000 0x10000>;
406			interrupts = <16>;
407			ti,hwmods = "sata";
408		};
409
410		mcspi1: spi@48030000 {
411			compatible = "ti,omap4-mcspi";
412			reg = <0x48030000 0x1000>;
413			#address-cells = <1>;
414			#size-cells = <0>;
415			interrupts = <65>;
416			ti,spi-num-cs = <4>;
417			ti,hwmods = "mcspi1";
418			dmas = <&edma 16 0 &edma 17 0
419				&edma 18 0 &edma 19 0
420				&edma 20 0 &edma 21 0
421				&edma 22 0 &edma 23 0>;
422			dma-names = "tx0", "rx0", "tx1", "rx1",
423				    "tx2", "rx2", "tx3", "rx3";
424		};
425
426		mmc1: mmc@48060000 {
427			compatible = "ti,omap4-hsmmc";
428			reg = <0x48060000 0x11000>;
429			ti,hwmods = "mmc1";
430			interrupts = <64>;
431			dmas = <&edma 24 0 &edma 25 0>;
432			dma-names = "tx", "rx";
433		};
434
435		timer1_target: target-module@4802e000 {
436			compatible = "ti,sysc-omap4-timer", "ti,sysc";
437			reg = <0x4802e000 0x4>,
438			      <0x4802e010 0x4>;
439			reg-names = "rev", "sysc";
440			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
441			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
442					<SYSC_IDLE_NO>,
443					<SYSC_IDLE_SMART>,
444					<SYSC_IDLE_SMART_WKUP>;
445			clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>;
446			clock-names = "fck";
447			#address-cells = <1>;
448			#size-cells = <1>;
449			ranges = <0x0 0x4802e000 0x1000>;
450
451			timer1: timer@0 {
452				compatible = "ti,dm816-timer";
453				reg = <0 0x1000>;
454				interrupts = <67>;
455				ti,timer-alwon;
456				clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>;
457				clock-names = "fck";
458			};
459		};
460
461		timer2_target: target-module@48040000 {
462			compatible = "ti,sysc-omap4-timer", "ti,sysc";
463			reg = <0x48040000 0x4>,
464			      <0x48040010 0x4>;
465			reg-names = "rev", "sysc";
466			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
467			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
468					<SYSC_IDLE_NO>,
469					<SYSC_IDLE_SMART>,
470					<SYSC_IDLE_SMART_WKUP>;
471			clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>;
472			clock-names = "fck";
473			#address-cells = <1>;
474			#size-cells = <1>;
475			ranges = <0x0 0x48040000 0x1000>;
476
477			timer2: timer@0 {
478				compatible = "ti,dm816-timer";
479				reg = <0 0x1000>;
480				interrupts = <68>;
481				clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>;
482				clock-names = "fck";
483			};
484		};
485
486		timer3: timer@48042000 {
487			compatible = "ti,dm816-timer";
488			reg = <0x48042000 0x2000>;
489			interrupts = <69>;
490			ti,hwmods = "timer3";
491		};
492
493		timer4: timer@48044000 {
494			compatible = "ti,dm816-timer";
495			reg = <0x48044000 0x2000>;
496			interrupts = <92>;
497			ti,hwmods = "timer4";
498			ti,timer-pwm;
499		};
500
501		timer5: timer@48046000 {
502			compatible = "ti,dm816-timer";
503			reg = <0x48046000 0x2000>;
504			interrupts = <93>;
505			ti,hwmods = "timer5";
506			ti,timer-pwm;
507		};
508
509		timer6: timer@48048000 {
510			compatible = "ti,dm816-timer";
511			reg = <0x48048000 0x2000>;
512			interrupts = <94>;
513			ti,hwmods = "timer6";
514			ti,timer-pwm;
515		};
516
517		timer7: timer@4804a000 {
518			compatible = "ti,dm816-timer";
519			reg = <0x4804a000 0x2000>;
520			interrupts = <95>;
521			ti,hwmods = "timer7";
522			ti,timer-pwm;
523		};
524
525		uart1: serial@48020000 {
526			compatible = "ti,am3352-uart", "ti,omap3-uart";
527			ti,hwmods = "uart1";
528			reg = <0x48020000 0x2000>;
529			clock-frequency = <48000000>;
530			interrupts = <72>;
531			dmas = <&edma 26 0 &edma 27 0>;
532			dma-names = "tx", "rx";
533		};
534
535		uart2: serial@48022000 {
536			compatible = "ti,am3352-uart", "ti,omap3-uart";
537			ti,hwmods = "uart2";
538			reg = <0x48022000 0x2000>;
539			clock-frequency = <48000000>;
540			interrupts = <73>;
541			dmas = <&edma 28 0 &edma 29 0>;
542			dma-names = "tx", "rx";
543		};
544
545		uart3: serial@48024000 {
546			compatible = "ti,am3352-uart", "ti,omap3-uart";
547			ti,hwmods = "uart3";
548			reg = <0x48024000 0x2000>;
549			clock-frequency = <48000000>;
550			interrupts = <74>;
551			dmas = <&edma 30 0 &edma 31 0>;
552			dma-names = "tx", "rx";
553		};
554
555		/* NOTE: USB needs a transceiver driver for phys to work */
556		usb: usb_otg_hs@47401000 {
557			compatible = "ti,am33xx-usb";
558			reg = <0x47401000 0x400000>;
559			ranges;
560			#address-cells = <1>;
561			#size-cells = <1>;
562			ti,hwmods = "usb_otg_hs";
563
564			usb0: usb@47401000 {
565				compatible = "ti,musb-dm816";
566				reg = <0x47401400 0x400
567				       0x47401000 0x200>;
568				reg-names = "mc", "control";
569				interrupts = <18>;
570				interrupt-names = "mc";
571				dr_mode = "host";
572				interface-type = <0>;
573				phys = <&usb_phy0>;
574				phy-names = "usb2-phy";
575				mentor,multipoint = <1>;
576				mentor,num-eps = <16>;
577				mentor,ram-bits = <12>;
578				mentor,power = <500>;
579
580				dmas = <&cppi41dma  0 0 &cppi41dma  1 0
581					&cppi41dma  2 0 &cppi41dma  3 0
582					&cppi41dma  4 0 &cppi41dma  5 0
583					&cppi41dma  6 0 &cppi41dma  7 0
584					&cppi41dma  8 0 &cppi41dma  9 0
585					&cppi41dma 10 0 &cppi41dma 11 0
586					&cppi41dma 12 0 &cppi41dma 13 0
587					&cppi41dma 14 0 &cppi41dma  0 1
588					&cppi41dma  1 1 &cppi41dma  2 1
589					&cppi41dma  3 1 &cppi41dma  4 1
590					&cppi41dma  5 1 &cppi41dma  6 1
591					&cppi41dma  7 1 &cppi41dma  8 1
592					&cppi41dma  9 1 &cppi41dma 10 1
593					&cppi41dma 11 1 &cppi41dma 12 1
594					&cppi41dma 13 1 &cppi41dma 14 1>;
595				dma-names =
596					"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
597					"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
598					"rx14", "rx15",
599					"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
600					"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
601					"tx14", "tx15";
602			};
603
604			usb1: usb@47401800 {
605				compatible = "ti,musb-dm816";
606				reg = <0x47401c00 0x400
607				       0x47401800 0x200>;
608				reg-names = "mc", "control";
609				interrupts = <19>;
610				interrupt-names = "mc";
611				dr_mode = "host";
612				interface-type = <0>;
613				phys = <&usb_phy1>;
614				phy-names = "usb2-phy";
615				mentor,multipoint = <1>;
616				mentor,num-eps = <16>;
617				mentor,ram-bits = <12>;
618				mentor,power = <500>;
619
620				dmas = <&cppi41dma 15 0 &cppi41dma 16 0
621					&cppi41dma 17 0 &cppi41dma 18 0
622					&cppi41dma 19 0 &cppi41dma 20 0
623					&cppi41dma 21 0 &cppi41dma 22 0
624					&cppi41dma 23 0 &cppi41dma 24 0
625					&cppi41dma 25 0 &cppi41dma 26 0
626					&cppi41dma 27 0 &cppi41dma 28 0
627					&cppi41dma 29 0 &cppi41dma 15 1
628					&cppi41dma 16 1 &cppi41dma 17 1
629					&cppi41dma 18 1 &cppi41dma 19 1
630					&cppi41dma 20 1 &cppi41dma 21 1
631					&cppi41dma 22 1 &cppi41dma 23 1
632					&cppi41dma 24 1 &cppi41dma 25 1
633					&cppi41dma 26 1 &cppi41dma 27 1
634					&cppi41dma 28 1 &cppi41dma 29 1>;
635				dma-names =
636					"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
637					"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
638					"rx14", "rx15",
639					"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
640					"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
641					"tx14", "tx15";
642			};
643
644			cppi41dma: dma-controller@47402000 {
645				compatible = "ti,am3359-cppi41";
646				reg =  <0x47400000 0x1000
647					0x47402000 0x1000
648					0x47403000 0x1000
649					0x47404000 0x4000>;
650				reg-names = "glue", "controller", "scheduler", "queuemgr";
651				interrupts = <17>;
652				interrupt-names = "glue";
653				#dma-cells = <2>;
654				/* For backwards compatibility: */
655				#dma-channels = <30>;
656				dma-channels = <30>;
657				#dma-requests = <256>;
658				dma-requests = <256>;
659			};
660		};
661
662		wd_timer2: wd_timer@480c2000 {
663			compatible = "ti,omap3-wdt";
664			ti,hwmods = "wd_timer";
665			reg = <0x480c2000 0x1000>;
666			interrupts = <0>;
667		};
668	};
669};
670
671#include "dm816x-clocks.dtsi"
672
673/* Preferred always-on timer for clocksource */
674&timer1_target {
675	ti,no-reset-on-init;
676	ti,no-idle;
677	timer@0 {
678		assigned-clocks = <&timer1_fck>;
679		assigned-clock-parents = <&sys_clkin_ck>;
680	};
681};
682
683/* Preferred timer for clockevent */
684&timer2_target {
685	ti,no-reset-on-init;
686	ti,no-idle;
687	timer@0 {
688		assigned-clocks = <&timer2_fck>;
689		assigned-clock-parents = <&sys_clkin_ck>;
690	};
691};
692