1*f126890aSEmmanuel Vadot// SPDX-License-Identifier: GPL-2.0 2*f126890aSEmmanuel Vadot// Copyright (c) 2018 Texas Instruments 3*f126890aSEmmanuel Vadot// MMC IOdelay values for TI's DRA76x and AM576x SoCs. 4*f126890aSEmmanuel Vadot// Author: Sekhar Nori <nsekhar@ti.com> 5*f126890aSEmmanuel Vadot 6*f126890aSEmmanuel Vadot/* 7*f126890aSEmmanuel Vadot * Rules for modifying this file: 8*f126890aSEmmanuel Vadot * a) Update of this file should typically correspond to a datamanual revision. 9*f126890aSEmmanuel Vadot * Datamanual revision that was used should be updated in comment below. 10*f126890aSEmmanuel Vadot * If there is no update to datamanual, do not update the values. If you 11*f126890aSEmmanuel Vadot * need to use values different from that recommended by the datamanual 12*f126890aSEmmanuel Vadot * for your design, then you should consider adding values to the device- 13*f126890aSEmmanuel Vadot * -tree file for your board directly. 14*f126890aSEmmanuel Vadot * b) We keep the mode names as close to the datamanual as possible. So 15*f126890aSEmmanuel Vadot * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v, 16*f126890aSEmmanuel Vadot * we follow that in code too. 17*f126890aSEmmanuel Vadot * c) If the values change between multiple revisions of silicon, we add 18*f126890aSEmmanuel Vadot * a revision tag to both the new and old entry. Use 'rev11' for PG 1.1, 19*f126890aSEmmanuel Vadot * 'rev20' for PG 2.0 and so on. 20*f126890aSEmmanuel Vadot * d) The node name and node label should be the exact same string. This is 21*f126890aSEmmanuel Vadot * to curb naming creativity and achieve consistency. 22*f126890aSEmmanuel Vadot * 23*f126890aSEmmanuel Vadot * Datamanual Revisions: 24*f126890aSEmmanuel Vadot * 25*f126890aSEmmanuel Vadot * DRA76x Silicon Revision 1.0: SPRS993E, Revised December 2018 26*f126890aSEmmanuel Vadot * 27*f126890aSEmmanuel Vadot */ 28*f126890aSEmmanuel Vadot 29*f126890aSEmmanuel Vadot&dra7_pmx_core { 30*f126890aSEmmanuel Vadot mmc1_pins_default: mmc1-default-pins { 31*f126890aSEmmanuel Vadot pinctrl-single,pins = < 32*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 33*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 34*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 35*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ 36*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ 37*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ 38*f126890aSEmmanuel Vadot >; 39*f126890aSEmmanuel Vadot }; 40*f126890aSEmmanuel Vadot 41*f126890aSEmmanuel Vadot mmc1_pins_hs: mmc1-hs-pins { 42*f126890aSEmmanuel Vadot pinctrl-single,pins = < 43*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ 44*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ 45*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */ 46*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */ 47*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */ 48*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */ 49*f126890aSEmmanuel Vadot >; 50*f126890aSEmmanuel Vadot }; 51*f126890aSEmmanuel Vadot 52*f126890aSEmmanuel Vadot mmc1_pins_sdr50: mmc1-sdr50-pins { 53*f126890aSEmmanuel Vadot pinctrl-single,pins = < 54*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_clk.clk */ 55*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_cmd.cmd */ 56*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat0.dat0 */ 57*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat1.dat1 */ 58*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat2.dat2 */ 59*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat3.dat3 */ 60*f126890aSEmmanuel Vadot >; 61*f126890aSEmmanuel Vadot }; 62*f126890aSEmmanuel Vadot 63*f126890aSEmmanuel Vadot mmc1_pins_ddr50: mmc1-ddr50-pins { 64*f126890aSEmmanuel Vadot pinctrl-single,pins = < 65*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ 66*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ 67*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ 68*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ 69*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ 70*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ 71*f126890aSEmmanuel Vadot >; 72*f126890aSEmmanuel Vadot }; 73*f126890aSEmmanuel Vadot 74*f126890aSEmmanuel Vadot mmc2_pins_default: mmc2-default-pins { 75*f126890aSEmmanuel Vadot pinctrl-single,pins = < 76*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ 77*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ 78*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ 79*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ 80*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ 81*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ 82*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ 83*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ 84*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ 85*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ 86*f126890aSEmmanuel Vadot >; 87*f126890aSEmmanuel Vadot }; 88*f126890aSEmmanuel Vadot 89*f126890aSEmmanuel Vadot mmc2_pins_hs200: mmc2-hs200-pins { 90*f126890aSEmmanuel Vadot pinctrl-single,pins = < 91*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ 92*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ 93*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ 94*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ 95*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ 96*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ 97*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ 98*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ 99*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ 100*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ 101*f126890aSEmmanuel Vadot >; 102*f126890aSEmmanuel Vadot }; 103*f126890aSEmmanuel Vadot 104*f126890aSEmmanuel Vadot mmc3_pins_default: mmc3-default-pins { 105*f126890aSEmmanuel Vadot pinctrl-single,pins = < 106*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ 107*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ 108*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ 109*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ 110*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ 111*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ 112*f126890aSEmmanuel Vadot >; 113*f126890aSEmmanuel Vadot }; 114*f126890aSEmmanuel Vadot 115*f126890aSEmmanuel Vadot mmc4_pins_hs: mmc4-hs-pins { 116*f126890aSEmmanuel Vadot pinctrl-single,pins = < 117*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ 118*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ 119*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ 120*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ 121*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ 122*f126890aSEmmanuel Vadot DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ 123*f126890aSEmmanuel Vadot >; 124*f126890aSEmmanuel Vadot }; 125*f126890aSEmmanuel Vadot}; 126*f126890aSEmmanuel Vadot 127*f126890aSEmmanuel Vadot&dra7_iodelay_core { 128*f126890aSEmmanuel Vadot 129*f126890aSEmmanuel Vadot /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */ 130*f126890aSEmmanuel Vadot mmc1_iodelay_ddr_conf: mmc1_iodelay_ddr_conf { 131*f126890aSEmmanuel Vadot pinctrl-pin-array = < 132*f126890aSEmmanuel Vadot 0x618 A_DELAY_PS(489) G_DELAY_PS(0) /* CFG_MMC1_CLK_IN */ 133*f126890aSEmmanuel Vadot 0x624 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_IN */ 134*f126890aSEmmanuel Vadot 0x630 A_DELAY_PS(374) G_DELAY_PS(0) /* CFG_MMC1_DAT0_IN */ 135*f126890aSEmmanuel Vadot 0x63c A_DELAY_PS(31) G_DELAY_PS(0) /* CFG_MMC1_DAT1_IN */ 136*f126890aSEmmanuel Vadot 0x648 A_DELAY_PS(56) G_DELAY_PS(0) /* CFG_MMC1_DAT2_IN */ 137*f126890aSEmmanuel Vadot 0x654 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */ 138*f126890aSEmmanuel Vadot 0x620 A_DELAY_PS(1355) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */ 139*f126890aSEmmanuel Vadot 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ 140*f126890aSEmmanuel Vadot 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ 141*f126890aSEmmanuel Vadot 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ 142*f126890aSEmmanuel Vadot 0x638 A_DELAY_PS(0) G_DELAY_PS(4) /* CFG_MMC1_DAT0_OUT */ 143*f126890aSEmmanuel Vadot 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ 144*f126890aSEmmanuel Vadot 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ 145*f126890aSEmmanuel Vadot 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ 146*f126890aSEmmanuel Vadot 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ 147*f126890aSEmmanuel Vadot 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ 148*f126890aSEmmanuel Vadot 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ 149*f126890aSEmmanuel Vadot >; 150*f126890aSEmmanuel Vadot }; 151*f126890aSEmmanuel Vadot 152*f126890aSEmmanuel Vadot /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */ 153*f126890aSEmmanuel Vadot mmc1_iodelay_sdr104_conf: mmc1_iodelay_sdr104_conf { 154*f126890aSEmmanuel Vadot pinctrl-pin-array = < 155*f126890aSEmmanuel Vadot 0x620 A_DELAY_PS(892) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */ 156*f126890aSEmmanuel Vadot 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ 157*f126890aSEmmanuel Vadot 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ 158*f126890aSEmmanuel Vadot 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ 159*f126890aSEmmanuel Vadot 0x638 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ 160*f126890aSEmmanuel Vadot 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ 161*f126890aSEmmanuel Vadot 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ 162*f126890aSEmmanuel Vadot 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ 163*f126890aSEmmanuel Vadot 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ 164*f126890aSEmmanuel Vadot 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ 165*f126890aSEmmanuel Vadot 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ 166*f126890aSEmmanuel Vadot >; 167*f126890aSEmmanuel Vadot }; 168*f126890aSEmmanuel Vadot 169*f126890aSEmmanuel Vadot /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */ 170*f126890aSEmmanuel Vadot mmc2_iodelay_hs200_conf: mmc2_iodelay_hs200_conf { 171*f126890aSEmmanuel Vadot pinctrl-pin-array = < 172*f126890aSEmmanuel Vadot 0x190 A_DELAY_PS(384) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ 173*f126890aSEmmanuel Vadot 0x194 A_DELAY_PS(350) G_DELAY_PS(174) /* CFG_GPMC_A19_OUT */ 174*f126890aSEmmanuel Vadot 0x1a8 A_DELAY_PS(410) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ 175*f126890aSEmmanuel Vadot 0x1ac A_DELAY_PS(335) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ 176*f126890aSEmmanuel Vadot 0x1b4 A_DELAY_PS(468) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ 177*f126890aSEmmanuel Vadot 0x1b8 A_DELAY_PS(339) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ 178*f126890aSEmmanuel Vadot 0x1c0 A_DELAY_PS(676) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ 179*f126890aSEmmanuel Vadot 0x1c4 A_DELAY_PS(219) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ 180*f126890aSEmmanuel Vadot 0x1d0 A_DELAY_PS(1062) G_DELAY_PS(154) /* CFG_GPMC_A23_OUT */ 181*f126890aSEmmanuel Vadot 0x1d8 A_DELAY_PS(640) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ 182*f126890aSEmmanuel Vadot 0x1dc A_DELAY_PS(150) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ 183*f126890aSEmmanuel Vadot 0x1e4 A_DELAY_PS(356) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ 184*f126890aSEmmanuel Vadot 0x1e8 A_DELAY_PS(150) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ 185*f126890aSEmmanuel Vadot 0x1f0 A_DELAY_PS(579) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ 186*f126890aSEmmanuel Vadot 0x1f4 A_DELAY_PS(200) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ 187*f126890aSEmmanuel Vadot 0x1fc A_DELAY_PS(435) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ 188*f126890aSEmmanuel Vadot 0x200 A_DELAY_PS(236) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ 189*f126890aSEmmanuel Vadot 0x364 A_DELAY_PS(759) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ 190*f126890aSEmmanuel Vadot 0x368 A_DELAY_PS(372) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ 191*f126890aSEmmanuel Vadot >; 192*f126890aSEmmanuel Vadot }; 193*f126890aSEmmanuel Vadot 194*f126890aSEmmanuel Vadot /* Corresponds to MMC3_MANUAL1 in datamanual */ 195*f126890aSEmmanuel Vadot mmc3_iodelay_manual1_conf: mmc3_iodelay_manual1_conf { 196*f126890aSEmmanuel Vadot pinctrl-pin-array = < 197*f126890aSEmmanuel Vadot 0x678 A_DELAY_PS(0) G_DELAY_PS(386) /* CFG_MMC3_CLK_IN */ 198*f126890aSEmmanuel Vadot 0x680 A_DELAY_PS(605) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */ 199*f126890aSEmmanuel Vadot 0x684 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */ 200*f126890aSEmmanuel Vadot 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */ 201*f126890aSEmmanuel Vadot 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */ 202*f126890aSEmmanuel Vadot 0x690 A_DELAY_PS(171) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */ 203*f126890aSEmmanuel Vadot 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */ 204*f126890aSEmmanuel Vadot 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */ 205*f126890aSEmmanuel Vadot 0x69c A_DELAY_PS(221) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */ 206*f126890aSEmmanuel Vadot 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */ 207*f126890aSEmmanuel Vadot 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */ 208*f126890aSEmmanuel Vadot 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */ 209*f126890aSEmmanuel Vadot 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */ 210*f126890aSEmmanuel Vadot 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */ 211*f126890aSEmmanuel Vadot 0x6b4 A_DELAY_PS(474) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */ 212*f126890aSEmmanuel Vadot 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */ 213*f126890aSEmmanuel Vadot 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */ 214*f126890aSEmmanuel Vadot >; 215*f126890aSEmmanuel Vadot }; 216*f126890aSEmmanuel Vadot 217*f126890aSEmmanuel Vadot /* Corresponds to MMC3_MANUAL2 in datamanual */ 218*f126890aSEmmanuel Vadot mmc3_iodelay_sdr50_conf: mmc3_iodelay_sdr50_conf { 219*f126890aSEmmanuel Vadot pinctrl-pin-array = < 220*f126890aSEmmanuel Vadot 0x678 A_DELAY_PS(852) G_DELAY_PS(0) /* CFG_MMC3_CLK_IN */ 221*f126890aSEmmanuel Vadot 0x680 A_DELAY_PS(94) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */ 222*f126890aSEmmanuel Vadot 0x684 A_DELAY_PS(122) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */ 223*f126890aSEmmanuel Vadot 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */ 224*f126890aSEmmanuel Vadot 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */ 225*f126890aSEmmanuel Vadot 0x690 A_DELAY_PS(91) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */ 226*f126890aSEmmanuel Vadot 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */ 227*f126890aSEmmanuel Vadot 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */ 228*f126890aSEmmanuel Vadot 0x69c A_DELAY_PS(57) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */ 229*f126890aSEmmanuel Vadot 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */ 230*f126890aSEmmanuel Vadot 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */ 231*f126890aSEmmanuel Vadot 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */ 232*f126890aSEmmanuel Vadot 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */ 233*f126890aSEmmanuel Vadot 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */ 234*f126890aSEmmanuel Vadot 0x6b4 A_DELAY_PS(375) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */ 235*f126890aSEmmanuel Vadot 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */ 236*f126890aSEmmanuel Vadot 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */ 237*f126890aSEmmanuel Vadot >; 238*f126890aSEmmanuel Vadot }; 239*f126890aSEmmanuel Vadot 240*f126890aSEmmanuel Vadot /* Corresponds to MMC4_MANUAL1 in datamanual */ 241*f126890aSEmmanuel Vadot mmc4_iodelay_manual1_conf: mmc4_iodelay_manual1_conf { 242*f126890aSEmmanuel Vadot pinctrl-pin-array = < 243*f126890aSEmmanuel Vadot 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ 244*f126890aSEmmanuel Vadot 0x848 A_DELAY_PS(1147) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ 245*f126890aSEmmanuel Vadot 0x84c A_DELAY_PS(1834) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ 246*f126890aSEmmanuel Vadot 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ 247*f126890aSEmmanuel Vadot 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ 248*f126890aSEmmanuel Vadot 0x870 A_DELAY_PS(2165) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ 249*f126890aSEmmanuel Vadot 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ 250*f126890aSEmmanuel Vadot 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ 251*f126890aSEmmanuel Vadot 0x87c A_DELAY_PS(1929) G_DELAY_PS(64) /* CFG_UART2_RTSN_IN */ 252*f126890aSEmmanuel Vadot 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ 253*f126890aSEmmanuel Vadot 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ 254*f126890aSEmmanuel Vadot 0x888 A_DELAY_PS(1935) G_DELAY_PS(128) /* CFG_UART2_RXD_IN */ 255*f126890aSEmmanuel Vadot 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ 256*f126890aSEmmanuel Vadot 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ 257*f126890aSEmmanuel Vadot 0x894 A_DELAY_PS(2172) G_DELAY_PS(44) /* CFG_UART2_TXD_IN */ 258*f126890aSEmmanuel Vadot 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ 259*f126890aSEmmanuel Vadot 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ 260*f126890aSEmmanuel Vadot >; 261*f126890aSEmmanuel Vadot }; 262*f126890aSEmmanuel Vadot 263*f126890aSEmmanuel Vadot /* Corresponds to MMC4_DS_MANUAL1 in datamanual */ 264*f126890aSEmmanuel Vadot mmc4_iodelay_default_conf: mmc4_iodelay_default_conf { 265*f126890aSEmmanuel Vadot pinctrl-pin-array = < 266*f126890aSEmmanuel Vadot 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ 267*f126890aSEmmanuel Vadot 0x848 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ 268*f126890aSEmmanuel Vadot 0x84c A_DELAY_PS(307) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ 269*f126890aSEmmanuel Vadot 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ 270*f126890aSEmmanuel Vadot 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ 271*f126890aSEmmanuel Vadot 0x870 A_DELAY_PS(785) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ 272*f126890aSEmmanuel Vadot 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ 273*f126890aSEmmanuel Vadot 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ 274*f126890aSEmmanuel Vadot 0x87c A_DELAY_PS(613) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */ 275*f126890aSEmmanuel Vadot 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ 276*f126890aSEmmanuel Vadot 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ 277*f126890aSEmmanuel Vadot 0x888 A_DELAY_PS(683) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */ 278*f126890aSEmmanuel Vadot 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ 279*f126890aSEmmanuel Vadot 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ 280*f126890aSEmmanuel Vadot 0x894 A_DELAY_PS(835) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */ 281*f126890aSEmmanuel Vadot 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ 282*f126890aSEmmanuel Vadot 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ 283*f126890aSEmmanuel Vadot >; 284*f126890aSEmmanuel Vadot }; 285*f126890aSEmmanuel Vadot}; 286