1/*
2 * Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
3 *
4 * Antoine Tenart <antoine.tenart@free-electrons.com>
5 *
6 * This software is available to you under a choice of one of two
7 * licenses.  You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * BSD license below:
11 *
12 *     Redistribution and use in source and binary forms, with or
13 *     without modification, are permitted provided that the following
14 *     conditions are met:
15 *
16 *      - Redistributions of source code must retain the above
17 *        copyright notice, this list of conditions and the following
18 *        disclaimer.
19 *
20 *      - Redistributions in binary form must reproduce the above
21 *        copyright notice, this list of conditions and the following
22 *        disclaimer in the documentation and/or other materials
23 *        provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35/dts-v1/;
36
37#include <dt-bindings/interrupt-controller/arm-gic.h>
38
39/ {
40	model = "Annapurna Labs Alpine v2";
41	compatible = "al,alpine-v2";
42	#address-cells = <2>;
43	#size-cells = <2>;
44
45	cpus {
46		#address-cells = <2>;
47		#size-cells = <0>;
48
49		cpu@0 {
50			compatible = "arm,cortex-a57";
51			device_type = "cpu";
52			reg = <0x0 0x0>;
53			enable-method = "psci";
54		};
55
56		cpu@1 {
57			compatible = "arm,cortex-a57";
58			device_type = "cpu";
59			reg = <0x0 0x1>;
60			enable-method = "psci";
61		};
62
63		cpu@2 {
64			compatible = "arm,cortex-a57";
65			device_type = "cpu";
66			reg = <0x0 0x2>;
67			enable-method = "psci";
68		};
69
70		cpu@3 {
71			compatible = "arm,cortex-a57";
72			device_type = "cpu";
73			reg = <0x0 0x3>;
74			enable-method = "psci";
75		};
76	};
77
78	psci {
79		compatible = "arm,psci-0.2", "arm,psci";
80		method = "smc";
81		cpu_suspend = <0x84000001>;
82		cpu_off = <0x84000002>;
83		cpu_on = <0x84000003>;
84	};
85
86	sbclk: sbclk {
87		compatible = "fixed-clock";
88		#clock-cells = <0>;
89		clock-frequency = <1000000>;
90	};
91
92	soc {
93		compatible = "simple-bus";
94		#address-cells = <2>;
95		#size-cells = <2>;
96
97		interrupt-parent = <&gic>;
98		ranges;
99
100		timer {
101			compatible = "arm,armv8-timer";
102			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
103				     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
104				     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
105				     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
106		};
107
108		pmu {
109			compatible = "arm,armv8-pmuv3";
110			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
111				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
112				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
113				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
114		};
115
116		gic: gic@f0100000 {
117			compatible = "arm,gic-v3";
118			reg = <0x0 0xf0200000 0x0 0x10000>,	/* GIC Dist */
119			      <0x0 0xf0280000 0x0 0x200000>,	/* GICR */
120			      <0x0 0xf0100000 0x0 0x2000>,	/* GICC */
121			      <0x0 0xf0110000 0x0 0x2000>,	/* GICV */
122			      <0x0 0xf0120000 0x0 0x2000>;	/* GICH */
123			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
124			interrupt-controller;
125			#interrupt-cells = <3>;
126		};
127
128		pci@fbc00000 {
129			compatible = "pci-host-ecam-generic";
130			device_type = "pci";
131			#size-cells = <2>;
132			#address-cells = <3>;
133			#interrupt-cells = <1>;
134			reg = <0x0 0xfbc00000 0x0 0x100000>;
135			interrupt-map-mask = <0xf800 0 0 7>;
136			/* add legacy interrupts for SATA only */
137			interrupt-map = <0x4000 0 0 1 &gic 0 53 4>,
138					<0x4800 0 0 1 &gic 0 54 4>;
139			/* 32 bit non prefetchable memory space */
140			ranges = <0x2000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>;
141			bus-range = <0x00 0x00>;
142			msi-parent = <&msix>;
143		};
144
145		msix: msix@fbe00000 {
146			compatible = "al,alpine-msix";
147			reg = <0x0 0xfbe00000 0x0 0x100000>;
148			interrupt-controller;
149			msi-controller;
150			al,msi-base-spi = <160>;
151			al,msi-num-spis = <160>;
152		};
153
154		io-fabric {
155			compatible = "simple-bus";
156			#address-cells = <1>;
157			#size-cells = <1>;
158			ranges = <0x0 0x0 0xfc000000 0x2000000>;
159
160			uart0: serial@1883000 {
161				compatible = "ns16550a";
162				device_type = "serial";
163				reg = <0x1883000 0x1000>;
164				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
165				clock-frequency = <500000000>;
166				reg-shift = <2>;
167				reg-io-width = <4>;
168				status = "disabled";
169			};
170
171			uart1: serial@1884000 {
172				compatible = "ns16550a";
173				device_type = "serial";
174				reg = <0x1884000 0x1000>;
175				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
176				clock-frequency = <500000000>;
177				reg-shift = <2>;
178				reg-io-width = <4>;
179				status = "disabled";
180			};
181
182			uart2: serial@1885000 {
183				compatible = "ns16550a";
184				device_type = "serial";
185				reg = <0x1885000 0x1000>;
186				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
187				clock-frequency = <500000000>;
188				reg-shift = <2>;
189				reg-io-width = <4>;
190				status = "disabled";
191			};
192
193			uart3: serial@1886000 {
194				compatible = "ns16550a";
195				device_type = "serial";
196				reg = <0x1886000 0x1000>;
197				interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
198				clock-frequency = <500000000>;
199				reg-shift = <2>;
200				reg-io-width = <4>;
201				status = "disabled";
202			};
203
204			timer0: timer@1890000 {
205				compatible = "arm,sp804", "arm,primecell";
206				reg = <0x1890000 0x1000>;
207				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
208				clocks = <&sbclk>;
209			};
210
211			timer1: timer@1891000 {
212				compatible = "arm,sp804", "arm,primecell";
213				reg = <0x1891000 0x1000>;
214				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
215				clocks = <&sbclk>;
216				status = "disabled";
217			};
218
219			timer2: timer@1892000 {
220				compatible = "arm,sp804", "arm,primecell";
221				reg = <0x1892000 0x1000>;
222				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
223				clocks = <&sbclk>;
224				status = "disabled";
225			};
226
227			timer3: timer@1893000 {
228				compatible = "arm,sp804", "arm,primecell";
229				reg = <0x1893000 0x1000>;
230				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
231				clocks = <&sbclk>;
232				status = "disabled";
233			};
234		};
235	};
236};
237