1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright Altera Corporation (C) 2015. All rights reserved. 4 */ 5 6/dts-v1/; 7#include <dt-bindings/reset/altr,rst-mgr-s10.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/clock/stratix10-clock.h> 10 11/ { 12 compatible = "altr,socfpga-stratix10"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 reserved-memory { 17 #address-cells = <2>; 18 #size-cells = <2>; 19 ranges; 20 21 service_reserved: svcbuffer@0 { 22 compatible = "shared-dma-pool"; 23 reg = <0x0 0x0 0x0 0x1000000>; 24 alignment = <0x1000>; 25 no-map; 26 }; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu0: cpu@0 { 34 compatible = "arm,cortex-a53"; 35 device_type = "cpu"; 36 enable-method = "psci"; 37 reg = <0x0>; 38 }; 39 40 cpu1: cpu@1 { 41 compatible = "arm,cortex-a53"; 42 device_type = "cpu"; 43 enable-method = "psci"; 44 reg = <0x1>; 45 }; 46 47 cpu2: cpu@2 { 48 compatible = "arm,cortex-a53"; 49 device_type = "cpu"; 50 enable-method = "psci"; 51 reg = <0x2>; 52 }; 53 54 cpu3: cpu@3 { 55 compatible = "arm,cortex-a53"; 56 device_type = "cpu"; 57 enable-method = "psci"; 58 reg = <0x3>; 59 }; 60 }; 61 62 pmu { 63 compatible = "arm,armv8-pmuv3"; 64 interrupts = <0 170 4>, 65 <0 171 4>, 66 <0 172 4>, 67 <0 173 4>; 68 interrupt-affinity = <&cpu0>, 69 <&cpu1>, 70 <&cpu2>, 71 <&cpu3>; 72 interrupt-parent = <&intc>; 73 }; 74 75 psci { 76 compatible = "arm,psci-0.2"; 77 method = "smc"; 78 }; 79 80 /* Local timer */ 81 timer { 82 compatible = "arm,armv8-timer"; 83 interrupts = <1 13 0xf08>, 84 <1 14 0xf08>, 85 <1 11 0xf08>, 86 <1 10 0xf08>; 87 interrupt-parent = <&intc>; 88 }; 89 90 intc: interrupt-controller@fffc1000 { 91 compatible = "arm,gic-400", "arm,cortex-a15-gic"; 92 #interrupt-cells = <3>; 93 interrupt-controller; 94 reg = <0x0 0xfffc1000 0x0 0x1000>, 95 <0x0 0xfffc2000 0x0 0x2000>, 96 <0x0 0xfffc4000 0x0 0x2000>, 97 <0x0 0xfffc6000 0x0 0x2000>; 98 }; 99 100 soc { 101 #address-cells = <1>; 102 #size-cells = <1>; 103 compatible = "simple-bus"; 104 device_type = "soc"; 105 interrupt-parent = <&intc>; 106 ranges = <0 0 0 0xffffffff>; 107 108 base_fpga_region { 109 #address-cells = <0x1>; 110 #size-cells = <0x1>; 111 112 compatible = "fpga-region"; 113 fpga-mgr = <&fpga_mgr>; 114 }; 115 116 clkmgr: clock-controller@ffd10000 { 117 compatible = "intel,stratix10-clkmgr"; 118 reg = <0xffd10000 0x1000>; 119 #clock-cells = <1>; 120 }; 121 122 clocks { 123 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { 124 #clock-cells = <0>; 125 compatible = "fixed-clock"; 126 }; 127 128 cb_intosc_ls_clk: cb-intosc-ls-clk { 129 #clock-cells = <0>; 130 compatible = "fixed-clock"; 131 }; 132 133 f2s_free_clk: f2s-free-clk { 134 #clock-cells = <0>; 135 compatible = "fixed-clock"; 136 }; 137 138 osc1: osc1 { 139 #clock-cells = <0>; 140 compatible = "fixed-clock"; 141 }; 142 143 qspi_clk: qspi-clk { 144 #clock-cells = <0>; 145 compatible = "fixed-clock"; 146 clock-frequency = <200000000>; 147 }; 148 }; 149 150 gmac0: ethernet@ff800000 { 151 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; 152 reg = <0xff800000 0x2000>; 153 interrupts = <0 90 4>; 154 interrupt-names = "macirq"; 155 mac-address = [00 00 00 00 00 00]; 156 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; 157 reset-names = "stmmaceth", "stmmaceth-ocp"; 158 clocks = <&clkmgr STRATIX10_EMAC0_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>; 159 clock-names = "stmmaceth", "ptp_ref"; 160 tx-fifo-depth = <16384>; 161 rx-fifo-depth = <16384>; 162 snps,multicast-filter-bins = <256>; 163 iommus = <&smmu 1>; 164 altr,sysmgr-syscon = <&sysmgr 0x44 0>; 165 status = "disabled"; 166 }; 167 168 gmac1: ethernet@ff802000 { 169 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; 170 reg = <0xff802000 0x2000>; 171 interrupts = <0 91 4>; 172 interrupt-names = "macirq"; 173 mac-address = [00 00 00 00 00 00]; 174 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; 175 reset-names = "stmmaceth", "stmmaceth-ocp"; 176 clocks = <&clkmgr STRATIX10_EMAC1_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>; 177 clock-names = "stmmaceth", "ptp_ref"; 178 tx-fifo-depth = <16384>; 179 rx-fifo-depth = <16384>; 180 snps,multicast-filter-bins = <256>; 181 iommus = <&smmu 2>; 182 altr,sysmgr-syscon = <&sysmgr 0x48 8>; 183 status = "disabled"; 184 }; 185 186 gmac2: ethernet@ff804000 { 187 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; 188 reg = <0xff804000 0x2000>; 189 interrupts = <0 92 4>; 190 interrupt-names = "macirq"; 191 mac-address = [00 00 00 00 00 00]; 192 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; 193 reset-names = "stmmaceth", "stmmaceth-ocp"; 194 clocks = <&clkmgr STRATIX10_EMAC2_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>; 195 clock-names = "stmmaceth", "ptp_ref"; 196 tx-fifo-depth = <16384>; 197 rx-fifo-depth = <16384>; 198 snps,multicast-filter-bins = <256>; 199 iommus = <&smmu 3>; 200 altr,sysmgr-syscon = <&sysmgr 0x4c 16>; 201 status = "disabled"; 202 }; 203 204 gpio0: gpio@ffc03200 { 205 #address-cells = <1>; 206 #size-cells = <0>; 207 compatible = "snps,dw-apb-gpio"; 208 reg = <0xffc03200 0x100>; 209 resets = <&rst GPIO0_RESET>; 210 status = "disabled"; 211 212 porta: gpio-controller@0 { 213 compatible = "snps,dw-apb-gpio-port"; 214 gpio-controller; 215 #gpio-cells = <2>; 216 ngpios = <24>; 217 reg = <0>; 218 interrupt-controller; 219 #interrupt-cells = <2>; 220 interrupts = <0 110 4>; 221 }; 222 }; 223 224 gpio1: gpio@ffc03300 { 225 #address-cells = <1>; 226 #size-cells = <0>; 227 compatible = "snps,dw-apb-gpio"; 228 reg = <0xffc03300 0x100>; 229 resets = <&rst GPIO1_RESET>; 230 status = "disabled"; 231 232 portb: gpio-controller@0 { 233 compatible = "snps,dw-apb-gpio-port"; 234 gpio-controller; 235 #gpio-cells = <2>; 236 ngpios = <24>; 237 reg = <0>; 238 interrupt-controller; 239 #interrupt-cells = <2>; 240 interrupts = <0 111 4>; 241 }; 242 }; 243 244 i2c0: i2c@ffc02800 { 245 #address-cells = <1>; 246 #size-cells = <0>; 247 compatible = "snps,designware-i2c"; 248 reg = <0xffc02800 0x100>; 249 interrupts = <0 103 4>; 250 resets = <&rst I2C0_RESET>; 251 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 252 status = "disabled"; 253 }; 254 255 i2c1: i2c@ffc02900 { 256 #address-cells = <1>; 257 #size-cells = <0>; 258 compatible = "snps,designware-i2c"; 259 reg = <0xffc02900 0x100>; 260 interrupts = <0 104 4>; 261 resets = <&rst I2C1_RESET>; 262 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 263 status = "disabled"; 264 }; 265 266 i2c2: i2c@ffc02a00 { 267 #address-cells = <1>; 268 #size-cells = <0>; 269 compatible = "snps,designware-i2c"; 270 reg = <0xffc02a00 0x100>; 271 interrupts = <0 105 4>; 272 resets = <&rst I2C2_RESET>; 273 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 274 status = "disabled"; 275 }; 276 277 i2c3: i2c@ffc02b00 { 278 #address-cells = <1>; 279 #size-cells = <0>; 280 compatible = "snps,designware-i2c"; 281 reg = <0xffc02b00 0x100>; 282 interrupts = <0 106 4>; 283 resets = <&rst I2C3_RESET>; 284 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 285 status = "disabled"; 286 }; 287 288 i2c4: i2c@ffc02c00 { 289 #address-cells = <1>; 290 #size-cells = <0>; 291 compatible = "snps,designware-i2c"; 292 reg = <0xffc02c00 0x100>; 293 interrupts = <0 107 4>; 294 resets = <&rst I2C4_RESET>; 295 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 296 status = "disabled"; 297 }; 298 299 mmc: mmc@ff808000 { 300 #address-cells = <1>; 301 #size-cells = <0>; 302 compatible = "altr,socfpga-dw-mshc"; 303 reg = <0xff808000 0x1000>; 304 interrupts = <0 96 4>; 305 fifo-depth = <0x400>; 306 resets = <&rst SDMMC_RESET>; 307 reset-names = "reset"; 308 clocks = <&clkmgr STRATIX10_L4_MP_CLK>, 309 <&clkmgr STRATIX10_SDMMC_CLK>; 310 clock-names = "biu", "ciu"; 311 iommus = <&smmu 5>; 312 status = "disabled"; 313 }; 314 315 nand: nand-controller@ffb90000 { 316 #address-cells = <1>; 317 #size-cells = <0>; 318 compatible = "altr,socfpga-denali-nand"; 319 reg = <0xffb90000 0x10000>, 320 <0xffb80000 0x1000>; 321 reg-names = "nand_data", "denali_reg"; 322 interrupts = <0 97 4>; 323 clocks = <&clkmgr STRATIX10_NAND_CLK>, 324 <&clkmgr STRATIX10_NAND_X_CLK>, 325 <&clkmgr STRATIX10_NAND_ECC_CLK>; 326 clock-names = "nand", "nand_x", "ecc"; 327 resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>; 328 status = "disabled"; 329 }; 330 331 ocram: sram@ffe00000 { 332 compatible = "mmio-sram"; 333 reg = <0xffe00000 0x100000>; 334 }; 335 336 pdma: dma-controller@ffda0000 { 337 compatible = "arm,pl330", "arm,primecell"; 338 reg = <0xffda0000 0x1000>; 339 interrupts = <0 81 4>, 340 <0 82 4>, 341 <0 83 4>, 342 <0 84 4>, 343 <0 85 4>, 344 <0 86 4>, 345 <0 87 4>, 346 <0 88 4>, 347 <0 89 4>; 348 #dma-cells = <1>; 349 #dma-channels = <8>; 350 #dma-requests = <32>; 351 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; 352 clock-names = "apb_pclk"; 353 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; 354 reset-names = "dma", "dma-ocp"; 355 }; 356 357 rst: rstmgr@ffd11000 { 358 #reset-cells = <1>; 359 compatible = "altr,stratix10-rst-mgr"; 360 reg = <0xffd11000 0x1000>; 361 }; 362 363 smmu: iommu@fa000000 { 364 compatible = "arm,mmu-500", "arm,smmu-v2"; 365 reg = <0xfa000000 0x40000>; 366 #global-interrupts = <2>; 367 #iommu-cells = <1>; 368 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; 369 clock-names = "iommu"; 370 interrupt-parent = <&intc>; 371 interrupts = <0 128 4>, /* Global Secure Fault */ 372 <0 129 4>, /* Global Non-secure Fault */ 373 /* Non-secure Context Interrupts (32) */ 374 <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>, 375 <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>, 376 <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>, 377 <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>, 378 <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>, 379 <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>, 380 <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>, 381 <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>; 382 stream-match-mask = <0x7ff0>; 383 status = "disabled"; 384 }; 385 386 spi0: spi@ffda4000 { 387 compatible = "snps,dw-apb-ssi"; 388 #address-cells = <1>; 389 #size-cells = <0>; 390 reg = <0xffda4000 0x1000>; 391 interrupts = <0 99 4>; 392 resets = <&rst SPIM0_RESET>; 393 reset-names = "spi"; 394 reg-io-width = <4>; 395 num-cs = <4>; 396 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; 397 status = "disabled"; 398 }; 399 400 spi1: spi@ffda5000 { 401 compatible = "snps,dw-apb-ssi"; 402 #address-cells = <1>; 403 #size-cells = <0>; 404 reg = <0xffda5000 0x1000>; 405 interrupts = <0 100 4>; 406 resets = <&rst SPIM1_RESET>; 407 reset-names = "spi"; 408 reg-io-width = <4>; 409 num-cs = <4>; 410 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; 411 status = "disabled"; 412 }; 413 414 sysmgr: sysmgr@ffd12000 { 415 compatible = "altr,sys-mgr-s10","altr,sys-mgr"; 416 reg = <0xffd12000 0x228>; 417 }; 418 419 timer0: timer0@ffc03000 { 420 compatible = "snps,dw-apb-timer"; 421 interrupts = <0 113 4>; 422 reg = <0xffc03000 0x100>; 423 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 424 clock-names = "timer"; 425 }; 426 427 timer1: timer1@ffc03100 { 428 compatible = "snps,dw-apb-timer"; 429 interrupts = <0 114 4>; 430 reg = <0xffc03100 0x100>; 431 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 432 clock-names = "timer"; 433 }; 434 435 timer2: timer2@ffd00000 { 436 compatible = "snps,dw-apb-timer"; 437 interrupts = <0 115 4>; 438 reg = <0xffd00000 0x100>; 439 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 440 clock-names = "timer"; 441 }; 442 443 timer3: timer3@ffd00100 { 444 compatible = "snps,dw-apb-timer"; 445 interrupts = <0 116 4>; 446 reg = <0xffd00100 0x100>; 447 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 448 clock-names = "timer"; 449 }; 450 451 uart0: serial@ffc02000 { 452 compatible = "snps,dw-apb-uart"; 453 reg = <0xffc02000 0x100>; 454 interrupts = <0 108 4>; 455 reg-shift = <2>; 456 reg-io-width = <4>; 457 resets = <&rst UART0_RESET>; 458 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 459 status = "disabled"; 460 }; 461 462 uart1: serial@ffc02100 { 463 compatible = "snps,dw-apb-uart"; 464 reg = <0xffc02100 0x100>; 465 interrupts = <0 109 4>; 466 reg-shift = <2>; 467 reg-io-width = <4>; 468 resets = <&rst UART1_RESET>; 469 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 470 status = "disabled"; 471 }; 472 473 usbphy0: usbphy@0 { 474 #phy-cells = <0>; 475 compatible = "usb-nop-xceiv"; 476 status = "okay"; 477 }; 478 479 usb0: usb@ffb00000 { 480 compatible = "snps,dwc2"; 481 reg = <0xffb00000 0x40000>; 482 interrupts = <0 93 4>; 483 phys = <&usbphy0>; 484 phy-names = "usb2-phy"; 485 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; 486 reset-names = "dwc2", "dwc2-ecc"; 487 clocks = <&clkmgr STRATIX10_USB_CLK>; 488 clock-names = "otg"; 489 iommus = <&smmu 6>; 490 status = "disabled"; 491 }; 492 493 usb1: usb@ffb40000 { 494 compatible = "snps,dwc2"; 495 reg = <0xffb40000 0x40000>; 496 interrupts = <0 94 4>; 497 phys = <&usbphy0>; 498 phy-names = "usb2-phy"; 499 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; 500 reset-names = "dwc2", "dwc2-ecc"; 501 clocks = <&clkmgr STRATIX10_USB_CLK>; 502 iommus = <&smmu 7>; 503 status = "disabled"; 504 }; 505 506 watchdog0: watchdog@ffd00200 { 507 compatible = "snps,dw-wdt"; 508 reg = <0xffd00200 0x100>; 509 interrupts = <0 117 4>; 510 resets = <&rst WATCHDOG0_RESET>; 511 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; 512 status = "disabled"; 513 }; 514 515 watchdog1: watchdog@ffd00300 { 516 compatible = "snps,dw-wdt"; 517 reg = <0xffd00300 0x100>; 518 interrupts = <0 118 4>; 519 resets = <&rst WATCHDOG1_RESET>; 520 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; 521 status = "disabled"; 522 }; 523 524 watchdog2: watchdog@ffd00400 { 525 compatible = "snps,dw-wdt"; 526 reg = <0xffd00400 0x100>; 527 interrupts = <0 125 4>; 528 resets = <&rst WATCHDOG2_RESET>; 529 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; 530 status = "disabled"; 531 }; 532 533 watchdog3: watchdog@ffd00500 { 534 compatible = "snps,dw-wdt"; 535 reg = <0xffd00500 0x100>; 536 interrupts = <0 126 4>; 537 resets = <&rst WATCHDOG3_RESET>; 538 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; 539 status = "disabled"; 540 }; 541 542 sdr: sdr@f8011100 { 543 compatible = "altr,sdr-ctl", "syscon"; 544 reg = <0xf8011100 0xc0>; 545 }; 546 547 eccmgr { 548 compatible = "altr,socfpga-s10-ecc-manager", 549 "altr,socfpga-a10-ecc-manager"; 550 altr,sysmgr-syscon = <&sysmgr>; 551 #address-cells = <1>; 552 #size-cells = <1>; 553 interrupts = <0 15 4>; 554 interrupt-controller; 555 #interrupt-cells = <2>; 556 ranges; 557 558 sdramedac { 559 compatible = "altr,sdram-edac-s10"; 560 altr,sdr-syscon = <&sdr>; 561 interrupts = <16 4>; 562 }; 563 564 ocram-ecc@ff8cc000 { 565 compatible = "altr,socfpga-s10-ocram-ecc", 566 "altr,socfpga-a10-ocram-ecc"; 567 reg = <0xff8cc000 0x100>; 568 altr,ecc-parent = <&ocram>; 569 interrupts = <1 4>; 570 }; 571 572 usb0-ecc@ff8c4000 { 573 compatible = "altr,socfpga-s10-usb-ecc", 574 "altr,socfpga-usb-ecc"; 575 reg = <0xff8c4000 0x100>; 576 altr,ecc-parent = <&usb0>; 577 interrupts = <2 4>; 578 }; 579 580 emac0-rx-ecc@ff8c0000 { 581 compatible = "altr,socfpga-s10-eth-mac-ecc", 582 "altr,socfpga-eth-mac-ecc"; 583 reg = <0xff8c0000 0x100>; 584 altr,ecc-parent = <&gmac0>; 585 interrupts = <4 4>; 586 }; 587 588 emac0-tx-ecc@ff8c0400 { 589 compatible = "altr,socfpga-s10-eth-mac-ecc", 590 "altr,socfpga-eth-mac-ecc"; 591 reg = <0xff8c0400 0x100>; 592 altr,ecc-parent = <&gmac0>; 593 interrupts = <5 4>; 594 }; 595 596 }; 597 598 qspi: spi@ff8d2000 { 599 compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; 600 #address-cells = <1>; 601 #size-cells = <0>; 602 reg = <0xff8d2000 0x100>, 603 <0xff900000 0x100000>; 604 interrupts = <0 3 4>; 605 cdns,fifo-depth = <128>; 606 cdns,fifo-width = <4>; 607 cdns,trigger-address = <0x00000000>; 608 clocks = <&qspi_clk>; 609 610 status = "disabled"; 611 }; 612 613 firmware { 614 svc { 615 compatible = "intel,stratix10-svc"; 616 method = "smc"; 617 memory-region = <&service_reserved>; 618 619 fpga_mgr: fpga-mgr { 620 compatible = "intel,stratix10-soc-fpga-mgr"; 621 }; 622 }; 623 }; 624 }; 625}; 626