1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2020, Amazon.com, Inc. or its affiliates. All Rights Reserved
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9
10/ {
11	model = "Amazon's Annapurna Labs Alpine v3";
12	compatible = "amazon,al-alpine-v3";
13
14	interrupt-parent = <&gic>;
15
16	#address-cells = <2>;
17	#size-cells = <2>;
18
19	cpus {
20		#address-cells = <1>;
21		#size-cells = <0>;
22
23		cpu@0 {
24			device_type = "cpu";
25			compatible = "arm,cortex-a72";
26			reg = <0x0>;
27			enable-method = "psci";
28			d-cache-size = <0x8000>;
29			d-cache-line-size = <64>;
30			d-cache-sets = <256>;
31			i-cache-size = <0xc000>;
32			i-cache-line-size = <64>;
33			i-cache-sets = <256>;
34			next-level-cache = <&cluster0_l2>;
35		};
36
37		cpu@1 {
38			device_type = "cpu";
39			compatible = "arm,cortex-a72";
40			reg = <0x1>;
41			enable-method = "psci";
42			d-cache-size = <0x8000>;
43			d-cache-line-size = <64>;
44			d-cache-sets = <256>;
45			i-cache-size = <0xc000>;
46			i-cache-line-size = <64>;
47			i-cache-sets = <256>;
48			next-level-cache = <&cluster0_l2>;
49		};
50
51		cpu@2 {
52			device_type = "cpu";
53			compatible = "arm,cortex-a72";
54			reg = <0x2>;
55			enable-method = "psci";
56			d-cache-size = <0x8000>;
57			d-cache-line-size = <64>;
58			d-cache-sets = <256>;
59			i-cache-size = <0xc000>;
60			i-cache-line-size = <64>;
61			i-cache-sets = <256>;
62			next-level-cache = <&cluster0_l2>;
63		};
64
65		cpu@3 {
66			device_type = "cpu";
67			compatible = "arm,cortex-a72";
68			reg = <0x3>;
69			enable-method = "psci";
70			d-cache-size = <0x8000>;
71			d-cache-line-size = <64>;
72			d-cache-sets = <256>;
73			i-cache-size = <0xc000>;
74			i-cache-line-size = <64>;
75			i-cache-sets = <256>;
76			next-level-cache = <&cluster0_l2>;
77		};
78
79		cpu@100 {
80			device_type = "cpu";
81			compatible = "arm,cortex-a72";
82			reg = <0x100>;
83			enable-method = "psci";
84			d-cache-size = <0x8000>;
85			d-cache-line-size = <64>;
86			d-cache-sets = <256>;
87			i-cache-size = <0xc000>;
88			i-cache-line-size = <64>;
89			i-cache-sets = <256>;
90			next-level-cache = <&cluster1_l2>;
91		};
92
93		cpu@101 {
94			device_type = "cpu";
95			compatible = "arm,cortex-a72";
96			reg = <0x101>;
97			enable-method = "psci";
98			d-cache-size = <0x8000>;
99			d-cache-line-size = <64>;
100			d-cache-sets = <256>;
101			i-cache-size = <0xc000>;
102			i-cache-line-size = <64>;
103			i-cache-sets = <256>;
104			next-level-cache = <&cluster1_l2>;
105		};
106
107		cpu@102 {
108			device_type = "cpu";
109			compatible = "arm,cortex-a72";
110			reg = <0x102>;
111			enable-method = "psci";
112			d-cache-size = <0x8000>;
113			d-cache-line-size = <64>;
114			d-cache-sets = <256>;
115			i-cache-size = <0xc000>;
116			i-cache-line-size = <64>;
117			i-cache-sets = <256>;
118			next-level-cache = <&cluster1_l2>;
119		};
120
121		cpu@103 {
122			device_type = "cpu";
123			compatible = "arm,cortex-a72";
124			reg = <0x103>;
125			enable-method = "psci";
126			d-cache-size = <0x8000>;
127			d-cache-line-size = <64>;
128			d-cache-sets = <256>;
129			i-cache-size = <0xc000>;
130			i-cache-line-size = <64>;
131			i-cache-sets = <256>;
132			next-level-cache = <&cluster1_l2>;
133		};
134
135		cpu@200 {
136			device_type = "cpu";
137			compatible = "arm,cortex-a72";
138			reg = <0x200>;
139			enable-method = "psci";
140			d-cache-size = <0x8000>;
141			d-cache-line-size = <64>;
142			d-cache-sets = <256>;
143			i-cache-size = <0xc000>;
144			i-cache-line-size = <64>;
145			i-cache-sets = <256>;
146			next-level-cache = <&cluster2_l2>;
147		};
148
149		cpu@201 {
150			device_type = "cpu";
151			compatible = "arm,cortex-a72";
152			reg = <0x201>;
153			enable-method = "psci";
154			d-cache-size = <0x8000>;
155			d-cache-line-size = <64>;
156			d-cache-sets = <256>;
157			i-cache-size = <0xc000>;
158			i-cache-line-size = <64>;
159			i-cache-sets = <256>;
160			next-level-cache = <&cluster2_l2>;
161		};
162
163		cpu@202 {
164			device_type = "cpu";
165			compatible = "arm,cortex-a72";
166			reg = <0x202>;
167			enable-method = "psci";
168			d-cache-size = <0x8000>;
169			d-cache-line-size = <64>;
170			d-cache-sets = <256>;
171			i-cache-size = <0xc000>;
172			i-cache-line-size = <64>;
173			i-cache-sets = <256>;
174			next-level-cache = <&cluster2_l2>;
175		};
176
177		cpu@203 {
178			device_type = "cpu";
179			compatible = "arm,cortex-a72";
180			reg = <0x203>;
181			enable-method = "psci";
182			d-cache-size = <0x8000>;
183			d-cache-line-size = <64>;
184			d-cache-sets = <256>;
185			i-cache-size = <0xc000>;
186			i-cache-line-size = <64>;
187			i-cache-sets = <256>;
188			next-level-cache = <&cluster2_l2>;
189		};
190
191		cpu@300 {
192			device_type = "cpu";
193			compatible = "arm,cortex-a72";
194			reg = <0x300>;
195			enable-method = "psci";
196			d-cache-size = <0x8000>;
197			d-cache-line-size = <64>;
198			d-cache-sets = <256>;
199			i-cache-size = <0xc000>;
200			i-cache-line-size = <64>;
201			i-cache-sets = <256>;
202			next-level-cache = <&cluster3_l2>;
203		};
204
205		cpu@301 {
206			device_type = "cpu";
207			compatible = "arm,cortex-a72";
208			reg = <0x301>;
209			enable-method = "psci";
210			d-cache-size = <0x8000>;
211			d-cache-line-size = <64>;
212			d-cache-sets = <256>;
213			i-cache-size = <0xc000>;
214			i-cache-line-size = <64>;
215			i-cache-sets = <256>;
216			next-level-cache = <&cluster3_l2>;
217		};
218
219		cpu@302 {
220			device_type = "cpu";
221			compatible = "arm,cortex-a72";
222			reg = <0x302>;
223			enable-method = "psci";
224			d-cache-size = <0x8000>;
225			d-cache-line-size = <64>;
226			d-cache-sets = <256>;
227			i-cache-size = <0xc000>;
228			i-cache-line-size = <64>;
229			i-cache-sets = <256>;
230			next-level-cache = <&cluster3_l2>;
231		};
232
233		cpu@303 {
234			device_type = "cpu";
235			compatible = "arm,cortex-a72";
236			reg = <0x303>;
237			enable-method = "psci";
238			d-cache-size = <0x8000>;
239			d-cache-line-size = <64>;
240			d-cache-sets = <256>;
241			i-cache-size = <0xc000>;
242			i-cache-line-size = <64>;
243			i-cache-sets = <256>;
244			next-level-cache = <&cluster3_l2>;
245		};
246
247		cluster0_l2: cache@0 {
248			compatible = "cache";
249			cache-size = <0x200000>;
250			cache-line-size = <64>;
251			cache-sets = <2048>;
252			cache-level = <2>;
253		};
254
255		cluster1_l2: cache@100 {
256			compatible = "cache";
257			cache-size = <0x200000>;
258			cache-line-size = <64>;
259			cache-sets = <2048>;
260			cache-level = <2>;
261		};
262
263		cluster2_l2: cache@200 {
264			compatible = "cache";
265			cache-size = <0x200000>;
266			cache-line-size = <64>;
267			cache-sets = <2048>;
268			cache-level = <2>;
269		};
270
271		cluster3_l2: cache@300 {
272			compatible = "cache";
273			cache-size = <0x200000>;
274			cache-line-size = <64>;
275			cache-sets = <2048>;
276			cache-level = <2>;
277		};
278
279	};
280
281	reserved-memory {
282		#address-cells = <2>;
283		#size-cells = <2>;
284		ranges;
285
286		secmon@0 {
287			reg = <0x0 0x0 0x0 0x100000>;
288			no-map;
289		};
290	};
291
292	psci {
293		compatible = "arm,psci-0.2";
294		method = "smc";
295	};
296
297	timer {
298		compatible = "arm,armv8-timer";
299		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
300			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
301			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
302			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
303	};
304
305	pmu {
306		compatible = "arm,cortex-a72-pmu";
307		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
308	};
309
310
311	soc {
312		compatible = "simple-bus";
313		#address-cells = <2>;
314		#size-cells = <2>;
315		ranges;
316
317		gic: interrupt-controller@f0000000 {
318			compatible = "arm,gic-v3";
319			#interrupt-cells = <3>;
320			interrupt-controller;
321			reg = <0x0 0xf0800000 0 0x10000>,	/* GICD */
322			      <0x0 0xf0a00000 0 0x200000>,	/* GICR */
323			      <0x0 0xf0000000 0 0x2000>,	/* GICC */
324			      <0x0 0xf0010000 0 0x1000>,	/* GICH */
325			      <0x0 0xf0020000 0 0x2000>;	/* GICV */
326			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
327		};
328
329		pcie@fbd00000 {
330			compatible = "pci-host-ecam-generic";
331			device_type = "pci";
332			#size-cells = <2>;
333			#address-cells = <3>;
334			#interrupt-cells = <1>;
335			reg = <0x0 0xfbd00000 0x0 0x100000>;
336			interrupt-map-mask = <0xf800 0 0 7>;
337			/* 8 x legacy interrupts for SATA only */
338			interrupt-map = <0x4000 0 0 1 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
339					<0x4800 0 0 1 &gic 0 58 IRQ_TYPE_LEVEL_HIGH>,
340					<0x5000 0 0 1 &gic 0 59 IRQ_TYPE_LEVEL_HIGH>,
341					<0x5800 0 0 1 &gic 0 60 IRQ_TYPE_LEVEL_HIGH>,
342					<0x6000 0 0 1 &gic 0 61 IRQ_TYPE_LEVEL_HIGH>,
343					<0x6800 0 0 1 &gic 0 62 IRQ_TYPE_LEVEL_HIGH>,
344					<0x7000 0 0 1 &gic 0 63 IRQ_TYPE_LEVEL_HIGH>,
345					<0x7800 0 0 1 &gic 0 64 IRQ_TYPE_LEVEL_HIGH>;
346			ranges = <0x02000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>;
347			bus-range = <0x00 0x00>;
348			msi-parent = <&msix>;
349		};
350
351		msix: msix@fbe00000 {
352			compatible = "al,alpine-msix";
353			reg = <0x0 0xfbe00000 0x0 0x100000>;
354			interrupt-controller;
355			msi-controller;
356			al,msi-base-spi = <336>;
357			al,msi-num-spis = <959>;
358			interrupt-parent = <&gic>;
359		};
360
361		io-fabric {
362			compatible = "simple-bus";
363			#address-cells = <1>;
364			#size-cells = <1>;
365			ranges = <0x0 0x0 0xfc000000 0x2000000>;
366
367			uart0: serial@1883000 {
368				compatible = "ns16550a";
369				reg = <0x1883000 0x1000>;
370				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
371				clock-frequency = <0>; /* Filled by firmware */
372				reg-shift = <2>;
373				reg-io-width = <4>;
374				status = "disabled";
375			};
376
377			uart1: serial@1884000 {
378				compatible = "ns16550a";
379				reg = <0x1884000 0x1000>;
380				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
381				clock-frequency = <0>; /* Filled by firmware */
382				reg-shift = <2>;
383				reg-io-width = <4>;
384				status = "disabled";
385			};
386
387			uart2: serial@1885000 {
388				compatible = "ns16550a";
389				reg = <0x1885000 0x1000>;
390				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
391				clock-frequency = <0>; /* Filled by firmware */
392				reg-shift = <2>;
393				reg-io-width = <4>;
394				status = "disabled";
395			};
396
397			uart3: serial@1886000 {
398				compatible = "ns16550a";
399				reg = <0x1886000 0x1000>;
400				interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
401				clock-frequency = <0>; /* Filled by firmware */
402				reg-shift = <2>;
403				reg-io-width = <4>;
404				status = "disabled";
405			};
406		};
407	};
408};
409