1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2022 Broadcom Ltd.
4 */
5
6#include <dt-bindings/interrupt-controller/irq.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8
9/ {
10	compatible = "brcm,bcm4912", "brcm,bcmbca";
11	#address-cells = <2>;
12	#size-cells = <2>;
13
14	interrupt-parent = <&gic>;
15
16	cpus {
17		#address-cells = <2>;
18		#size-cells = <0>;
19
20		B53_0: cpu@0 {
21			compatible = "brcm,brahma-b53";
22			device_type = "cpu";
23			reg = <0x0 0x0>;
24			next-level-cache = <&L2_0>;
25			enable-method = "psci";
26		};
27
28		B53_1: cpu@1 {
29			compatible = "brcm,brahma-b53";
30			device_type = "cpu";
31			reg = <0x0 0x1>;
32			next-level-cache = <&L2_0>;
33			enable-method = "psci";
34		};
35
36		B53_2: cpu@2 {
37			compatible = "brcm,brahma-b53";
38			device_type = "cpu";
39			reg = <0x0 0x2>;
40			next-level-cache = <&L2_0>;
41			enable-method = "psci";
42		};
43
44		B53_3: cpu@3 {
45			compatible = "brcm,brahma-b53";
46			device_type = "cpu";
47			reg = <0x0 0x3>;
48			next-level-cache = <&L2_0>;
49			enable-method = "psci";
50		};
51
52		L2_0: l2-cache0 {
53			compatible = "cache";
54			cache-level = <2>;
55		};
56	};
57
58	timer {
59		compatible = "arm,armv8-timer";
60		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
61			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
62			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
63			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
64	};
65
66	pmu: pmu {
67		compatible = "arm,cortex-a53-pmu";
68		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
69			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
70			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
71			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
72		interrupt-affinity = <&B53_0>, <&B53_1>,
73			<&B53_2>, <&B53_3>;
74	};
75
76	clocks: clocks {
77		periph_clk: periph-clk {
78			compatible = "fixed-clock";
79			#clock-cells = <0>;
80			clock-frequency = <200000000>;
81		};
82
83		uart_clk: uart-clk {
84			compatible = "fixed-factor-clock";
85			#clock-cells = <0>;
86			clocks = <&periph_clk>;
87			clock-div = <4>;
88			clock-mult = <1>;
89		};
90
91		hsspi_pll: hsspi-pll {
92			compatible = "fixed-clock";
93			#clock-cells = <0>;
94			clock-frequency = <200000000>;
95		};
96	};
97
98	psci {
99		compatible = "arm,psci-0.2";
100		method = "smc";
101	};
102
103	axi@81000000 {
104		compatible = "simple-bus";
105		#address-cells = <1>;
106		#size-cells = <1>;
107		ranges = <0x0 0x0 0x81000000 0x8000>;
108
109		gic: interrupt-controller@1000 {
110			compatible = "arm,gic-400";
111			#interrupt-cells = <3>;
112			interrupt-controller;
113			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
114			reg = <0x1000 0x1000>,
115				<0x2000 0x2000>,
116				<0x4000 0x2000>,
117				<0x6000 0x2000>;
118		};
119	};
120
121	bus@ff800000 {
122		compatible = "simple-bus";
123		#address-cells = <1>;
124		#size-cells = <1>;
125		ranges = <0x0 0x0 0xff800000 0x800000>;
126
127		hsspi: spi@1000 {
128			#address-cells = <1>;
129			#size-cells = <0>;
130			compatible = "brcm,bcm4912-hsspi", "brcm,bcmbca-hsspi-v1.1";
131			reg = <0x1000 0x600>, <0x2610 0x4>;
132			reg-names = "hsspi", "spim-ctrl";
133			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
134			clocks = <&hsspi_pll &hsspi_pll>;
135			clock-names = "hsspi", "pll";
136			num-cs = <8>;
137			status = "disabled";
138		};
139
140		uart0: serial@12000 {
141			compatible = "arm,pl011", "arm,primecell";
142			reg = <0x12000 0x1000>;
143			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
144			clocks = <&uart_clk>, <&uart_clk>;
145			clock-names = "uartclk", "apb_pclk";
146			status = "disabled";
147		};
148	};
149};
150