1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2022 Broadcom Ltd.
4 */
5
6#include <dt-bindings/interrupt-controller/irq.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8
9/ {
10	compatible = "brcm,bcm6856", "brcm,bcmbca";
11	#address-cells = <2>;
12	#size-cells = <2>;
13
14	interrupt-parent = <&gic>;
15
16	cpus {
17		#address-cells = <2>;
18		#size-cells = <0>;
19
20		B53_0: cpu@0 {
21			compatible = "brcm,brahma-b53";
22			device_type = "cpu";
23			reg = <0x0 0x0>;
24			next-level-cache = <&L2_0>;
25			enable-method = "psci";
26		};
27
28		B53_1: cpu@1 {
29			compatible = "brcm,brahma-b53";
30			device_type = "cpu";
31			reg = <0x0 0x1>;
32			next-level-cache = <&L2_0>;
33			enable-method = "psci";
34		};
35
36		L2_0: l2-cache0 {
37			compatible = "cache";
38			cache-level = <2>;
39			cache-unified;
40		};
41	};
42
43	timer {
44		compatible = "arm,armv8-timer";
45		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
46			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
47			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
48			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
49	};
50
51	pmu: pmu {
52		compatible = "arm,cortex-a53-pmu";
53		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
54			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
55		interrupt-affinity = <&B53_0>, <&B53_1>;
56	};
57
58	clocks: clocks {
59		periph_clk:periph-clk {
60			compatible = "fixed-clock";
61			#clock-cells = <0>;
62			clock-frequency = <200000000>;
63		};
64
65		hsspi_pll: hsspi-pll {
66			compatible = "fixed-clock";
67			#clock-cells = <0>;
68			clock-frequency = <400000000>;
69		};
70	};
71
72	psci {
73		compatible = "arm,psci-0.2";
74		method = "smc";
75	};
76
77	axi@81000000 {
78		compatible = "simple-bus";
79		#address-cells = <1>;
80		#size-cells = <1>;
81		ranges = <0x0 0x0 0x81000000 0x8000>;
82
83		gic: interrupt-controller@1000 {
84			compatible = "arm,gic-400";
85			#interrupt-cells = <3>;
86			interrupt-controller;
87			reg = <0x1000 0x1000>, /* GICD */
88				<0x2000 0x2000>, /* GICC */
89				<0x4000 0x2000>, /* GICH */
90				<0x6000 0x2000>; /* GICV */
91			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
92					IRQ_TYPE_LEVEL_HIGH)>;
93		};
94	};
95
96	bus@ff800000 {
97		compatible = "simple-bus";
98		#address-cells = <1>;
99		#size-cells = <1>;
100		ranges = <0x0 0x0 0xff800000 0x800000>;
101
102		uart0: serial@640 {
103			compatible = "brcm,bcm6345-uart";
104			reg = <0x640 0x18>;
105			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
106			clocks = <&periph_clk>;
107			clock-names = "refclk";
108			status = "disabled";
109		};
110
111		hsspi: spi@1000 {
112			#address-cells = <1>;
113			#size-cells = <0>;
114			compatible = "brcm,bcm6856-hsspi", "brcm,bcmbca-hsspi-v1.0";
115			reg = <0x1000 0x600>;
116			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
117			clocks = <&hsspi_pll &hsspi_pll>;
118			clock-names = "hsspi", "pll";
119			num-cs = <8>;
120			status = "disabled";
121		};
122	};
123};
124