1/*
2 *  BSD LICENSE
3 *
4 *  Copyright(c) 2015-2017 Broadcom.  All rights reserved.
5 *
6 *  Redistribution and use in source and binary forms, with or without
7 *  modification, are permitted provided that the following conditions
8 *  are met:
9 *
10 *    * Redistributions of source code must retain the above copyright
11 *      notice, this list of conditions and the following disclaimer.
12 *    * Redistributions in binary form must reproduce the above copyright
13 *      notice, this list of conditions and the following disclaimer in
14 *      the documentation and/or other materials provided with the
15 *      distribution.
16 *    * Neither the name of Broadcom nor the names of its
17 *      contributors may be used to endorse or promote products derived
18 *      from this software without specific prior written permission.
19 *
20 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#include <dt-bindings/interrupt-controller/arm-gic.h>
34
35/ {
36	compatible = "brcm,stingray";
37	interrupt-parent = <&gic>;
38	#address-cells = <2>;
39	#size-cells = <2>;
40
41	cpus {
42		#address-cells = <2>;
43		#size-cells = <0>;
44
45		cpu@0 {
46			device_type = "cpu";
47			compatible = "arm,cortex-a72";
48			reg = <0x0 0x0>;
49			enable-method = "psci";
50			next-level-cache = <&CLUSTER0_L2>;
51		};
52
53		cpu@1 {
54			device_type = "cpu";
55			compatible = "arm,cortex-a72";
56			reg = <0x0 0x1>;
57			enable-method = "psci";
58			next-level-cache = <&CLUSTER0_L2>;
59		};
60
61		cpu@100 {
62			device_type = "cpu";
63			compatible = "arm,cortex-a72";
64			reg = <0x0 0x100>;
65			enable-method = "psci";
66			next-level-cache = <&CLUSTER1_L2>;
67		};
68
69		cpu@101 {
70			device_type = "cpu";
71			compatible = "arm,cortex-a72";
72			reg = <0x0 0x101>;
73			enable-method = "psci";
74			next-level-cache = <&CLUSTER1_L2>;
75		};
76
77		cpu@200 {
78			device_type = "cpu";
79			compatible = "arm,cortex-a72";
80			reg = <0x0 0x200>;
81			enable-method = "psci";
82			next-level-cache = <&CLUSTER2_L2>;
83		};
84
85		cpu@201 {
86			device_type = "cpu";
87			compatible = "arm,cortex-a72";
88			reg = <0x0 0x201>;
89			enable-method = "psci";
90			next-level-cache = <&CLUSTER2_L2>;
91		};
92
93		cpu@300 {
94			device_type = "cpu";
95			compatible = "arm,cortex-a72";
96			reg = <0x0 0x300>;
97			enable-method = "psci";
98			next-level-cache = <&CLUSTER3_L2>;
99		};
100
101		cpu@301 {
102			device_type = "cpu";
103			compatible = "arm,cortex-a72";
104			reg = <0x0 0x301>;
105			enable-method = "psci";
106			next-level-cache = <&CLUSTER3_L2>;
107		};
108
109		CLUSTER0_L2: l2-cache@0 {
110			compatible = "cache";
111			cache-level = <2>;
112			cache-unified;
113		};
114
115		CLUSTER1_L2: l2-cache@100 {
116			compatible = "cache";
117			cache-level = <2>;
118			cache-unified;
119		};
120
121		CLUSTER2_L2: l2-cache@200 {
122			compatible = "cache";
123			cache-level = <2>;
124			cache-unified;
125		};
126
127		CLUSTER3_L2: l2-cache@300 {
128			compatible = "cache";
129			cache-level = <2>;
130			cache-unified;
131		};
132	};
133
134	memory: memory@80000000 {
135		device_type = "memory";
136		reg = <0x00000000 0x80000000 0 0x40000000>;
137	};
138
139	psci {
140		compatible = "arm,psci-0.2";
141		method = "smc";
142	};
143
144	pmu {
145		compatible = "arm,armv8-pmuv3";
146		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
147	};
148
149	timer {
150		compatible = "arm,armv8-timer";
151		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
152			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
153			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
154			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
155	};
156
157	mhb: syscon@60401000 {
158		compatible = "brcm,sr-mhb", "syscon";
159		reg = <0 0x60401000 0 0x38c>;
160	};
161
162	scr {
163		compatible = "simple-bus";
164		#address-cells = <1>;
165		#size-cells = <1>;
166		ranges = <0x0 0x0 0x61000000 0x05000000>;
167
168		ccn: ccn@0 {
169			compatible = "arm,ccn-502";
170			reg = <0x00000000 0x900000>;
171			interrupts = <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>;
172		};
173
174		gic: interrupt-controller@2c00000 {
175			compatible = "arm,gic-v3";
176			#interrupt-cells = <3>;
177			#address-cells = <1>;
178			#size-cells = <1>;
179			ranges;
180			interrupt-controller;
181			reg = <0x02c00000 0x010000>, /* GICD */
182			      <0x02e00000 0x600000>; /* GICR */
183			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
184
185			gic_its: msi-controller@63c20000 {
186				compatible = "arm,gic-v3-its";
187				msi-controller;
188				#msi-cells = <1>;
189				reg = <0x02c20000 0x10000>;
190			};
191		};
192
193		smmu: iommu@3000000 {
194			compatible = "arm,mmu-500";
195			reg = <0x03000000 0x80000>;
196			#global-interrupts = <1>;
197			interrupts = <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>,
198				     <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
199				     <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
200				     <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
201				     <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
202				     <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
203				     <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>,
204				     <GIC_SPI 717 IRQ_TYPE_LEVEL_HIGH>,
205				     <GIC_SPI 718 IRQ_TYPE_LEVEL_HIGH>,
206				     <GIC_SPI 719 IRQ_TYPE_LEVEL_HIGH>,
207				     <GIC_SPI 720 IRQ_TYPE_LEVEL_HIGH>,
208				     <GIC_SPI 721 IRQ_TYPE_LEVEL_HIGH>,
209				     <GIC_SPI 722 IRQ_TYPE_LEVEL_HIGH>,
210				     <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH>,
211				     <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH>,
212				     <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH>,
213				     <GIC_SPI 726 IRQ_TYPE_LEVEL_HIGH>,
214				     <GIC_SPI 727 IRQ_TYPE_LEVEL_HIGH>,
215				     <GIC_SPI 728 IRQ_TYPE_LEVEL_HIGH>,
216				     <GIC_SPI 729 IRQ_TYPE_LEVEL_HIGH>,
217				     <GIC_SPI 730 IRQ_TYPE_LEVEL_HIGH>,
218				     <GIC_SPI 731 IRQ_TYPE_LEVEL_HIGH>,
219				     <GIC_SPI 732 IRQ_TYPE_LEVEL_HIGH>,
220				     <GIC_SPI 733 IRQ_TYPE_LEVEL_HIGH>,
221				     <GIC_SPI 734 IRQ_TYPE_LEVEL_HIGH>,
222				     <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>,
223				     <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>,
224				     <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>,
225				     <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>,
226				     <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>,
227				     <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>,
228				     <GIC_SPI 741 IRQ_TYPE_LEVEL_HIGH>,
229				     <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>,
230				     <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>,
231				     <GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>,
232				     <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>,
233				     <GIC_SPI 746 IRQ_TYPE_LEVEL_HIGH>,
234				     <GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>,
235				     <GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>,
236				     <GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>,
237				     <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>,
238				     <GIC_SPI 751 IRQ_TYPE_LEVEL_HIGH>,
239				     <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>,
240				     <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>,
241				     <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>,
242				     <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>,
243				     <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>,
244				     <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>,
245				     <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
246				     <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
247				     <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>,
248				     <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
249				     <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>,
250				     <GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH>,
251				     <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>,
252				     <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>,
253				     <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>,
254				     <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>,
255				     <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
256				     <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
257				     <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
258				     <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>,
259				     <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
260				     <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
261				     <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>;
262			#iommu-cells = <2>;
263		};
264	};
265
266	crmu: crmu {
267		compatible = "simple-bus";
268		#address-cells = <1>;
269		#size-cells = <1>;
270		ranges = <0x0 0x0 0x66400000 0x100000>;
271
272		#include "stingray-clock.dtsi"
273
274		otp: otp@1c400 {
275			compatible = "brcm,ocotp-v2";
276			reg = <0x0001c400 0x68>;
277			brcm,ocotp-size = <2048>;
278			status = "okay";
279		};
280
281		cdru: syscon@1d000 {
282			compatible = "brcm,sr-cdru", "syscon";
283			reg = <0x0001d000 0x400>;
284		};
285
286		gpio_crmu: gpio@24800 {
287			compatible = "brcm,iproc-gpio";
288			reg = <0x00024800 0x4c>;
289			ngpios = <6>;
290			#gpio-cells = <2>;
291			gpio-controller;
292		};
293	};
294
295	#include "stingray-fs4.dtsi"
296	#include "stingray-pcie.dtsi"
297	#include "stingray-usb.dtsi"
298
299	hsls {
300		compatible = "simple-bus";
301		#address-cells = <1>;
302		#size-cells = <1>;
303		ranges = <0x0 0x0 0x68900000 0x17700000>;
304
305		#include "stingray-pinctrl.dtsi"
306
307		mdio_mux_iproc: mdio-mux@20000 {
308			compatible = "brcm,mdio-mux-iproc";
309			reg = <0x00020000 0x250>;
310			#address-cells = <1>;
311			#size-cells = <0>;
312
313			mdio@0 { /* PCIe serdes */
314				reg = <0x0>;
315				#address-cells = <1>;
316				#size-cells = <0>;
317			};
318
319			mdio@3 { /* USB */
320				reg = <0x3>;
321				#address-cells = <1>;
322				#size-cells = <0>;
323			};
324
325			mdio@10 { /* RGMII */
326				reg = <0x10>;
327				#address-cells = <1>;
328				#size-cells = <0>;
329			};
330		};
331
332		pwm: pwm@10000 {
333			compatible = "brcm,iproc-pwm";
334			reg = <0x00010000 0x1000>;
335			clocks = <&crmu_ref25m>;
336			#pwm-cells = <3>;
337			status = "disabled";
338		};
339
340		timer0: timer@30000 {
341			compatible = "arm,sp804", "arm,primecell";
342			reg = <0x00030000 0x1000>;
343			interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
344			clocks = <&hsls_25m_div2_clk>,
345				 <&hsls_25m_div2_clk>,
346				 <&hsls_div4_clk>;
347			clock-names = "timer1", "timer2", "apb_pclk";
348			status = "disabled";
349		};
350
351		timer1: timer@40000 {
352			compatible = "arm,sp804", "arm,primecell";
353			reg = <0x00040000 0x1000>;
354			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
355			clocks = <&hsls_25m_div2_clk>,
356				 <&hsls_25m_div2_clk>,
357				 <&hsls_div4_clk>;
358			clock-names = "timer1", "timer2", "apb_pclk";
359		};
360
361		timer2: timer@50000 {
362			compatible = "arm,sp804", "arm,primecell";
363			reg = <0x00050000 0x1000>;
364			interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
365			clocks = <&hsls_25m_div2_clk>,
366				 <&hsls_25m_div2_clk>,
367				 <&hsls_div4_clk>;
368			clock-names = "timer1", "timer2", "apb_pclk";
369			status = "disabled";
370		};
371
372		timer3: timer@60000 {
373			compatible = "arm,sp804", "arm,primecell";
374			reg = <0x00060000 0x1000>;
375			interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
376			clocks = <&hsls_25m_div2_clk>,
377				 <&hsls_25m_div2_clk>,
378				 <&hsls_div4_clk>;
379			clock-names = "timer1", "timer2", "apb_pclk";
380			status = "disabled";
381		};
382
383		timer4: timer@70000 {
384			compatible = "arm,sp804", "arm,primecell";
385			reg = <0x00070000 0x1000>;
386			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
387			clocks = <&hsls_25m_div2_clk>,
388				 <&hsls_25m_div2_clk>,
389				 <&hsls_div4_clk>;
390			clock-names = "timer1", "timer2", "apb_pclk";
391			status = "disabled";
392		};
393
394		timer5: timer@80000 {
395			compatible = "arm,sp804", "arm,primecell";
396			reg = <0x00080000 0x1000>;
397			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
398			clocks = <&hsls_25m_div2_clk>,
399				 <&hsls_25m_div2_clk>,
400				 <&hsls_div4_clk>;
401			clock-names = "timer1", "timer2", "apb_pclk";
402			status = "disabled";
403		};
404
405		timer6: timer@90000 {
406			compatible = "arm,sp804", "arm,primecell";
407			reg = <0x00090000 0x1000>;
408			interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
409			clocks = <&hsls_25m_div2_clk>,
410				 <&hsls_25m_div2_clk>,
411				 <&hsls_div4_clk>;
412			clock-names = "timer1", "timer2", "apb_pclk";
413			status = "disabled";
414		};
415
416		timer7: timer@a0000 {
417			compatible = "arm,sp804", "arm,primecell";
418			reg = <0x000a0000 0x1000>;
419			interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
420			clocks = <&hsls_25m_div2_clk>,
421				 <&hsls_25m_div2_clk>,
422				 <&hsls_div4_clk>;
423			clock-names = "timer1", "timer2", "apb_pclk";
424			status = "disabled";
425		};
426
427		i2c0: i2c@b0000 {
428			compatible = "brcm,iproc-i2c";
429			reg = <0x000b0000 0x100>;
430			#address-cells = <1>;
431			#size-cells = <0>;
432			interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
433			clock-frequency = <100000>;
434			status = "disabled";
435		};
436
437		wdt0: watchdog@c0000 {
438			compatible = "arm,sp805", "arm,primecell";
439			reg = <0x000c0000 0x1000>;
440			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
441			clocks = <&hsls_25m_div2_clk>, <&hsls_div4_clk>;
442			clock-names = "wdog_clk", "apb_pclk";
443			timeout-sec = <60>;
444		};
445
446		gpio_hsls: gpio@d0000 {
447			compatible = "brcm,iproc-gpio";
448			reg = <0x000d0000 0x864>;
449			ngpios = <151>;
450			#gpio-cells = <2>;
451			gpio-controller;
452			interrupt-controller;
453			interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
454			gpio-ranges = <&pinmux 0 0 16>,
455					<&pinmux 16 71 2>,
456					<&pinmux 18 131 8>,
457					<&pinmux 26 83 6>,
458					<&pinmux 32 123 4>,
459					<&pinmux 36 43 24>,
460					<&pinmux 60 89 2>,
461					<&pinmux 62 73 4>,
462					<&pinmux 66 95 28>,
463					<&pinmux 94 127 4>,
464					<&pinmux 98 139 10>,
465					<&pinmux 108 16 27>,
466					<&pinmux 135 77 6>,
467					<&pinmux 141 67 4>,
468					<&pinmux 145 149 6>;
469		};
470
471		i2c1: i2c@e0000 {
472			compatible = "brcm,iproc-i2c";
473			reg = <0x000e0000 0x100>;
474			#address-cells = <1>;
475			#size-cells = <0>;
476			interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
477			clock-frequency = <100000>;
478			status = "disabled";
479		};
480
481		uart0: serial@100000 {
482			compatible = "snps,dw-apb-uart";
483			reg = <0x00100000 0x1000>;
484			reg-shift = <2>;
485			clock-frequency = <25000000>;
486			interrupt-parent = <&gic>;
487			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
488			status = "disabled";
489		};
490
491		uart1: serial@110000 {
492			compatible = "snps,dw-apb-uart";
493			reg = <0x00110000 0x1000>;
494			reg-shift = <2>;
495			clock-frequency = <25000000>;
496			interrupt-parent = <&gic>;
497			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
498			status = "disabled";
499		};
500
501		uart2: serial@120000 {
502			compatible = "snps,dw-apb-uart";
503			reg = <0x00120000 0x1000>;
504			reg-shift = <2>;
505			clock-frequency = <25000000>;
506			interrupt-parent = <&gic>;
507			interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
508			status = "disabled";
509		};
510
511		uart3: serial@130000 {
512			compatible = "snps,dw-apb-uart";
513			reg = <0x00130000 0x1000>;
514			reg-shift = <2>;
515			clock-frequency = <25000000>;
516			interrupt-parent = <&gic>;
517			interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
518			status = "disabled";
519		};
520
521		ssp0: spi@180000 {
522			compatible = "arm,pl022", "arm,primecell";
523			reg = <0x00180000 0x1000>;
524			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
525			clocks = <&hsls_div2_clk>, <&hsls_div2_clk>;
526			clock-names = "sspclk", "apb_pclk";
527			num-cs = <1>;
528			#address-cells = <1>;
529			#size-cells = <0>;
530			status = "disabled";
531		};
532
533		ssp1: spi@190000 {
534			compatible = "arm,pl022", "arm,primecell";
535			reg = <0x00190000 0x1000>;
536			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
537			clocks = <&hsls_div2_clk>, <&hsls_div2_clk>;
538			clock-names = "sspclk", "apb_pclk";
539			num-cs = <1>;
540			#address-cells = <1>;
541			#size-cells = <0>;
542			status = "disabled";
543		};
544
545		hwrng: hwrng@220000 {
546			compatible = "brcm,iproc-rng200";
547			reg = <0x00220000 0x28>;
548		};
549
550		dma0: dma-controller@310000 {
551			compatible = "arm,pl330", "arm,primecell";
552			reg = <0x00310000 0x1000>;
553			interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
554				     <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
555				     <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
556				     <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
557				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
558				     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
559				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
560				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
561				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
562			#dma-cells = <1>;
563			clocks = <&hsls_div2_clk>;
564			clock-names = "apb_pclk";
565			iommus = <&smmu 0x6000 0x0000>;
566		};
567
568		enet: ethernet@340000{
569			compatible = "brcm,amac";
570			reg = <0x00340000 0x1000>;
571			reg-names = "amac_base";
572			dma-coherent;
573			interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
574			status = "disabled";
575		};
576
577		nand: nand@360000 {
578			compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
579			reg = <0x00360000 0x600>,
580			      <0x0050a408 0x600>,
581			      <0x00360f00 0x20>;
582			reg-names = "nand", "iproc-idm", "iproc-ext";
583			interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
584			#address-cells = <1>;
585			#size-cells = <0>;
586			brcm,nand-has-wp;
587			status = "disabled";
588		};
589
590		sdio0: sdhci@3f1000 {
591			compatible = "brcm,sdhci-iproc";
592			reg = <0x003f1000 0x100>;
593			interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
594			bus-width = <8>;
595			clocks = <&sdio0_clk>;
596			iommus = <&smmu 0x6002 0x0000>;
597			status = "disabled";
598		};
599
600		sdio1: sdhci@3f2000 {
601			compatible = "brcm,sdhci-iproc";
602			reg = <0x003f2000 0x100>;
603			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
604			bus-width = <8>;
605			clocks = <&sdio1_clk>;
606			iommus = <&smmu 0x6003 0x0000>;
607			status = "disabled";
608		};
609	};
610
611	tmons {
612		compatible = "simple-bus";
613		#address-cells = <1>;
614		#size-cells = <1>;
615		ranges = <0x0 0x0 0x8f100000 0x100>;
616
617		tmon: tmon@0 {
618			compatible = "brcm,sr-thermal";
619			reg = <0x0 0x40>;
620			brcm,tmon-mask = <0x3f>;
621			#thermal-sensor-cells = <1>;
622		};
623	};
624
625	thermal-zones {
626		ihost0_thermal: ihost0-thermal {
627			polling-delay-passive = <0>;
628			polling-delay = <1000>;
629			thermal-sensors = <&tmon 0>;
630			trips {
631				cpu-crit {
632					temperature = <105000>;
633					hysteresis = <0>;
634					type = "critical";
635				};
636			};
637		};
638		ihost1_thermal: ihost1-thermal {
639			polling-delay-passive = <0>;
640			polling-delay = <1000>;
641			thermal-sensors = <&tmon 1>;
642			trips {
643				cpu-crit {
644					temperature = <105000>;
645					hysteresis = <0>;
646					type = "critical";
647				};
648			};
649		};
650		ihost2_thermal: ihost2-thermal {
651			polling-delay-passive = <0>;
652			polling-delay = <1000>;
653			thermal-sensors = <&tmon 2>;
654			trips {
655				cpu-crit {
656					temperature = <105000>;
657					hysteresis = <0>;
658					type = "critical";
659				};
660			};
661		};
662		ihost3_thermal: ihost3-thermal {
663			polling-delay-passive = <0>;
664			polling-delay = <1000>;
665			thermal-sensors = <&tmon 3>;
666			trips {
667				cpu-crit {
668					temperature = <105000>;
669					hysteresis = <0>;
670					type = "critical";
671				};
672			};
673		};
674		crmu_thermal: crmu-thermal {
675			polling-delay-passive = <0>;
676			polling-delay = <1000>;
677			thermal-sensors = <&tmon 4>;
678			trips {
679				cpu-crit {
680					temperature = <105000>;
681					hysteresis = <0>;
682					type = "critical";
683				};
684			};
685		};
686		nitro_thermal: nitro-thermal {
687			polling-delay-passive = <0>;
688			polling-delay = <1000>;
689			thermal-sensors = <&tmon 5>;
690			trips {
691				cpu-crit {
692					temperature = <105000>;
693					hysteresis = <0>;
694					type = "critical";
695				};
696			};
697		};
698	};
699
700	nic-hsls {
701		compatible = "simple-bus";
702		#address-cells = <1>;
703		#size-cells = <1>;
704		ranges = <0x0 0x0  0x0 0x7fffffff>;
705
706		nic_i2c0: i2c@60826100 {
707			compatible = "brcm,iproc-nic-i2c";
708			#address-cells = <1>;
709			#size-cells = <0>;
710			reg = <0x60826100 0x100>,
711			      <0x60e00408 0x1000>;
712			brcm,ape-hsls-addr-mask = <0x03400000>;
713			clock-frequency = <100000>;
714			status = "disabled";
715		};
716	};
717};
718