1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Samsung Exynos7 SoC device tree source
4 *
5 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
6 *		http://www.samsung.com
7 */
8
9#include <dt-bindings/clock/exynos7-clk.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11
12/ {
13	compatible = "samsung,exynos7";
14	interrupt-parent = <&gic>;
15	#address-cells = <2>;
16	#size-cells = <2>;
17
18	aliases {
19		pinctrl0 = &pinctrl_alive;
20		pinctrl1 = &pinctrl_bus0;
21		pinctrl2 = &pinctrl_nfc;
22		pinctrl3 = &pinctrl_touch;
23		pinctrl4 = &pinctrl_ff;
24		pinctrl5 = &pinctrl_ese;
25		pinctrl6 = &pinctrl_fsys0;
26		pinctrl7 = &pinctrl_fsys1;
27		pinctrl8 = &pinctrl_bus1;
28		tmuctrl0 = &tmuctrl_0;
29	};
30
31	arm-pmu {
32		compatible = "arm,cortex-a57-pmu";
33		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
34			     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
35			     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
36			     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
37		interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>,
38				     <&cpu_atlas2>, <&cpu_atlas3>;
39	};
40
41	fin_pll: clock {
42		/* XXTI */
43		compatible = "fixed-clock";
44		clock-output-names = "fin_pll";
45		#clock-cells = <0>;
46	};
47
48	cpus {
49		#address-cells = <1>;
50		#size-cells = <0>;
51
52		cpu_atlas0: cpu@0 {
53			device_type = "cpu";
54			compatible = "arm,cortex-a57";
55			reg = <0x0>;
56			enable-method = "psci";
57			i-cache-size = <0xc000>;
58			i-cache-line-size = <64>;
59			i-cache-sets = <256>;
60			d-cache-size = <0x8000>;
61			d-cache-line-size = <64>;
62			d-cache-sets = <256>;
63			next-level-cache = <&atlas_l2>;
64		};
65
66		cpu_atlas1: cpu@1 {
67			device_type = "cpu";
68			compatible = "arm,cortex-a57";
69			reg = <0x1>;
70			enable-method = "psci";
71			i-cache-size = <0xc000>;
72			i-cache-line-size = <64>;
73			i-cache-sets = <256>;
74			d-cache-size = <0x8000>;
75			d-cache-line-size = <64>;
76			d-cache-sets = <256>;
77			next-level-cache = <&atlas_l2>;
78		};
79
80		cpu_atlas2: cpu@2 {
81			device_type = "cpu";
82			compatible = "arm,cortex-a57";
83			reg = <0x2>;
84			enable-method = "psci";
85			i-cache-size = <0xc000>;
86			i-cache-line-size = <64>;
87			i-cache-sets = <256>;
88			d-cache-size = <0x8000>;
89			d-cache-line-size = <64>;
90			d-cache-sets = <256>;
91			next-level-cache = <&atlas_l2>;
92		};
93
94		cpu_atlas3: cpu@3 {
95			device_type = "cpu";
96			compatible = "arm,cortex-a57";
97			reg = <0x3>;
98			enable-method = "psci";
99			i-cache-size = <0xc000>;
100			i-cache-line-size = <64>;
101			i-cache-sets = <256>;
102			d-cache-size = <0x8000>;
103			d-cache-line-size = <64>;
104			d-cache-sets = <256>;
105			next-level-cache = <&atlas_l2>;
106		};
107
108		atlas_l2: l2-cache0 {
109			compatible = "cache";
110			cache-size = <0x200000>;
111			cache-line-size = <64>;
112			cache-sets = <2048>;
113		};
114	};
115
116	psci {
117		compatible = "arm,psci";
118		method = "smc";
119		cpu_off = <0x84000002>;
120		cpu_on = <0xC4000003>;
121	};
122
123	soc: soc@0 {
124		compatible = "simple-bus";
125		#address-cells = <1>;
126		#size-cells = <1>;
127		ranges = <0 0 0 0x18000000>;
128
129		chipid@10000000 {
130			compatible = "samsung,exynos4210-chipid";
131			reg = <0x10000000 0x100>;
132		};
133
134		gic: interrupt-controller@11001000 {
135			compatible = "arm,gic-400";
136			#interrupt-cells = <3>;
137			#address-cells = <0>;
138			interrupt-controller;
139			reg =	<0x11001000 0x1000>,
140				<0x11002000 0x2000>,
141				<0x11004000 0x2000>,
142				<0x11006000 0x2000>;
143		};
144
145		pdma0: dma-controller@10e10000 {
146			compatible = "arm,pl330", "arm,primecell";
147			reg = <0x10E10000 0x1000>;
148			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
149			clocks = <&clock_fsys0 ACLK_PDMA0>;
150			clock-names = "apb_pclk";
151			#dma-cells = <1>;
152		};
153
154		pdma1: dma-controller@10eb0000 {
155			compatible = "arm,pl330", "arm,primecell";
156			reg = <0x10EB0000 0x1000>;
157			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
158			clocks = <&clock_fsys0 ACLK_PDMA1>;
159			clock-names = "apb_pclk";
160			#dma-cells = <1>;
161		};
162
163		clock_topc: clock-controller@10570000 {
164			compatible = "samsung,exynos7-clock-topc";
165			reg = <0x10570000 0x10000>;
166			#clock-cells = <1>;
167		};
168
169		clock_top0: clock-controller@105d0000 {
170			compatible = "samsung,exynos7-clock-top0";
171			reg = <0x105d0000 0xb000>;
172			#clock-cells = <1>;
173			clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
174				 <&clock_topc DOUT_SCLK_BUS1_PLL>,
175				 <&clock_topc DOUT_SCLK_CC_PLL>,
176				 <&clock_topc DOUT_SCLK_MFC_PLL>,
177				 <&clock_topc DOUT_SCLK_AUD_PLL>;
178			clock-names = "fin_pll", "dout_sclk_bus0_pll",
179				      "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
180				      "dout_sclk_mfc_pll", "dout_sclk_aud_pll";
181		};
182
183		clock_top1: clock-controller@105e0000 {
184			compatible = "samsung,exynos7-clock-top1";
185			reg = <0x105e0000 0xb000>;
186			#clock-cells = <1>;
187			clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
188				 <&clock_topc DOUT_SCLK_BUS1_PLL>,
189				 <&clock_topc DOUT_SCLK_CC_PLL>,
190				 <&clock_topc DOUT_SCLK_MFC_PLL>;
191			clock-names = "fin_pll", "dout_sclk_bus0_pll",
192				      "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
193				      "dout_sclk_mfc_pll";
194		};
195
196		clock_ccore: clock-controller@105b0000 {
197			compatible = "samsung,exynos7-clock-ccore";
198			reg = <0x105b0000 0xd00>;
199			#clock-cells = <1>;
200			clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_CCORE_133>;
201			clock-names = "fin_pll", "dout_aclk_ccore_133";
202		};
203
204		clock_peric0: clock-controller@13610000 {
205			compatible = "samsung,exynos7-clock-peric0";
206			reg = <0x13610000 0xd00>;
207			#clock-cells = <1>;
208			clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC0>,
209				 <&clock_top0 CLK_SCLK_UART0>;
210			clock-names = "fin_pll", "dout_aclk_peric0_66",
211				      "sclk_uart0";
212		};
213
214		clock_peric1: clock-controller@14c80000 {
215			compatible = "samsung,exynos7-clock-peric1";
216			reg = <0x14c80000 0xd00>;
217			#clock-cells = <1>;
218			clocks = <&fin_pll>,
219				 <&clock_top0 DOUT_ACLK_PERIC1>,
220				 <&clock_top0 CLK_SCLK_UART1>,
221				 <&clock_top0 CLK_SCLK_UART2>,
222				 <&clock_top0 CLK_SCLK_UART3>,
223				 <&clock_top0 CLK_SCLK_SPI0>,
224				 <&clock_top0 CLK_SCLK_SPI1>,
225				 <&clock_top0 CLK_SCLK_SPI2>,
226				 <&clock_top0 CLK_SCLK_SPI3>,
227				 <&clock_top0 CLK_SCLK_SPI4>,
228				 <&clock_top0 CLK_SCLK_I2S1>,
229				 <&clock_top0 CLK_SCLK_PCM1>,
230				 <&clock_top0 CLK_SCLK_SPDIF>;
231			clock-names = "fin_pll",
232				      "dout_aclk_peric1_66",
233				      "sclk_uart1",
234				      "sclk_uart2",
235				      "sclk_uart3",
236				      "sclk_spi0",
237				      "sclk_spi1",
238				      "sclk_spi2",
239				      "sclk_spi3",
240				      "sclk_spi4",
241				      "sclk_i2s1",
242				      "sclk_pcm1",
243				      "sclk_spdif";
244		};
245
246		clock_peris: clock-controller@10040000 {
247			compatible = "samsung,exynos7-clock-peris";
248			reg = <0x10040000 0xd00>;
249			#clock-cells = <1>;
250			clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_PERIS>;
251			clock-names = "fin_pll", "dout_aclk_peris_66";
252		};
253
254		clock_fsys0: clock-controller@10e90000 {
255			compatible = "samsung,exynos7-clock-fsys0";
256			reg = <0x10e90000 0xd00>;
257			#clock-cells = <1>;
258			clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS0_200>,
259				 <&clock_top1 DOUT_SCLK_MMC2>;
260			clock-names = "fin_pll", "dout_aclk_fsys0_200",
261				      "dout_sclk_mmc2";
262		};
263
264		clock_fsys1: clock-controller@156e0000 {
265			compatible = "samsung,exynos7-clock-fsys1";
266			reg = <0x156e0000 0xd00>;
267			#clock-cells = <1>;
268			clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS1_200>,
269				 <&clock_top1 DOUT_SCLK_MMC0>,
270				 <&clock_top1 DOUT_SCLK_MMC1>,
271				 <&clock_top1 DOUT_SCLK_UFSUNIPRO20>,
272				 <&clock_top1 DOUT_SCLK_PHY_FSYS1>,
273				 <&clock_top1 DOUT_SCLK_PHY_FSYS1_26M>;
274			clock-names = "fin_pll", "dout_aclk_fsys1_200",
275				      "dout_sclk_mmc0", "dout_sclk_mmc1",
276				      "dout_sclk_ufsunipro20", "dout_sclk_phy_fsys1",
277				      "dout_sclk_phy_fsys1_26m";
278		};
279
280		serial_0: serial@13630000 {
281			compatible = "samsung,exynos4210-uart";
282			reg = <0x13630000 0x100>;
283			interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
284			clocks = <&clock_peric0 PCLK_UART0>,
285				 <&clock_peric0 SCLK_UART0>;
286			clock-names = "uart", "clk_uart_baud0";
287			status = "disabled";
288		};
289
290		serial_1: serial@14c20000 {
291			compatible = "samsung,exynos4210-uart";
292			reg = <0x14c20000 0x100>;
293			interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
294			clocks = <&clock_peric1 PCLK_UART1>,
295				 <&clock_peric1 SCLK_UART1>;
296			clock-names = "uart", "clk_uart_baud0";
297			status = "disabled";
298		};
299
300		serial_2: serial@14c30000 {
301			compatible = "samsung,exynos4210-uart";
302			reg = <0x14c30000 0x100>;
303			interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>;
304			clocks = <&clock_peric1 PCLK_UART2>,
305				 <&clock_peric1 SCLK_UART2>;
306			clock-names = "uart", "clk_uart_baud0";
307			status = "disabled";
308		};
309
310		serial_3: serial@14c40000 {
311			compatible = "samsung,exynos4210-uart";
312			reg = <0x14c40000 0x100>;
313			interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>;
314			clocks = <&clock_peric1 PCLK_UART3>,
315				 <&clock_peric1 SCLK_UART3>;
316			clock-names = "uart", "clk_uart_baud0";
317			status = "disabled";
318		};
319
320		pinctrl_alive: pinctrl@10580000 {
321			compatible = "samsung,exynos7-pinctrl";
322			reg = <0x10580000 0x1000>;
323
324			wakeup-interrupt-controller {
325				compatible = "samsung,exynos7-wakeup-eint";
326				interrupt-parent = <&gic>;
327				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
328			};
329		};
330
331		pinctrl_bus0: pinctrl@13470000 {
332			compatible = "samsung,exynos7-pinctrl";
333			reg = <0x13470000 0x1000>;
334			interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
335		};
336
337		pinctrl_nfc: pinctrl@14cd0000 {
338			compatible = "samsung,exynos7-pinctrl";
339			reg = <0x14cd0000 0x1000>;
340			interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
341		};
342
343		pinctrl_touch: pinctrl@14ce0000 {
344			compatible = "samsung,exynos7-pinctrl";
345			reg = <0x14ce0000 0x1000>;
346			interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
347		};
348
349		pinctrl_ff: pinctrl@14c90000 {
350			compatible = "samsung,exynos7-pinctrl";
351			reg = <0x14c90000 0x1000>;
352			interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
353		};
354
355		pinctrl_ese: pinctrl@14ca0000 {
356			compatible = "samsung,exynos7-pinctrl";
357			reg = <0x14ca0000 0x1000>;
358			interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>;
359		};
360
361		pinctrl_fsys0: pinctrl@10e60000 {
362			compatible = "samsung,exynos7-pinctrl";
363			reg = <0x10e60000 0x1000>;
364			interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
365		};
366
367		pinctrl_fsys1: pinctrl@15690000 {
368			compatible = "samsung,exynos7-pinctrl";
369			reg = <0x15690000 0x1000>;
370			interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
371		};
372
373		pinctrl_bus1: pinctrl@14870000 {
374			compatible = "samsung,exynos7-pinctrl";
375			reg = <0x14870000 0x1000>;
376			interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
377		};
378
379		hsi2c_0: i2c@13640000 {
380			compatible = "samsung,exynos7-hsi2c";
381			reg = <0x13640000 0x1000>;
382			interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
383			#address-cells = <1>;
384			#size-cells = <0>;
385			pinctrl-names = "default";
386			pinctrl-0 = <&hs_i2c0_bus>;
387			clocks = <&clock_peric0 PCLK_HSI2C0>;
388			clock-names = "hsi2c";
389			status = "disabled";
390		};
391
392		hsi2c_1: i2c@13650000 {
393			compatible = "samsung,exynos7-hsi2c";
394			reg = <0x13650000 0x1000>;
395			interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
396			#address-cells = <1>;
397			#size-cells = <0>;
398			pinctrl-names = "default";
399			pinctrl-0 = <&hs_i2c1_bus>;
400			clocks = <&clock_peric0 PCLK_HSI2C1>;
401			clock-names = "hsi2c";
402			status = "disabled";
403		};
404
405		hsi2c_2: i2c@14e60000 {
406			compatible = "samsung,exynos7-hsi2c";
407			reg = <0x14e60000 0x1000>;
408			interrupts = <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>;
409			#address-cells = <1>;
410			#size-cells = <0>;
411			pinctrl-names = "default";
412			pinctrl-0 = <&hs_i2c2_bus>;
413			clocks = <&clock_peric1 PCLK_HSI2C2>;
414			clock-names = "hsi2c";
415			status = "disabled";
416		};
417
418		hsi2c_3: i2c@14e70000 {
419			compatible = "samsung,exynos7-hsi2c";
420			reg = <0x14e70000 0x1000>;
421			interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>;
422			#address-cells = <1>;
423			#size-cells = <0>;
424			pinctrl-names = "default";
425			pinctrl-0 = <&hs_i2c3_bus>;
426			clocks = <&clock_peric1 PCLK_HSI2C3>;
427			clock-names = "hsi2c";
428			status = "disabled";
429		};
430
431		hsi2c_4: i2c@13660000 {
432			compatible = "samsung,exynos7-hsi2c";
433			reg = <0x13660000 0x1000>;
434			interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
435			#address-cells = <1>;
436			#size-cells = <0>;
437			pinctrl-names = "default";
438			pinctrl-0 = <&hs_i2c4_bus>;
439			clocks = <&clock_peric0 PCLK_HSI2C4>;
440			clock-names = "hsi2c";
441			status = "disabled";
442		};
443
444		hsi2c_5: i2c@13670000 {
445			compatible = "samsung,exynos7-hsi2c";
446			reg = <0x13670000 0x1000>;
447			interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
448			#address-cells = <1>;
449			#size-cells = <0>;
450			pinctrl-names = "default";
451			pinctrl-0 = <&hs_i2c5_bus>;
452			clocks = <&clock_peric0 PCLK_HSI2C5>;
453			clock-names = "hsi2c";
454			status = "disabled";
455		};
456
457		hsi2c_6: i2c@14e00000 {
458			compatible = "samsung,exynos7-hsi2c";
459			reg = <0x14e00000 0x1000>;
460			interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
461			#address-cells = <1>;
462			#size-cells = <0>;
463			pinctrl-names = "default";
464			pinctrl-0 = <&hs_i2c6_bus>;
465			clocks = <&clock_peric1 PCLK_HSI2C6>;
466			clock-names = "hsi2c";
467			status = "disabled";
468		};
469
470		hsi2c_7: i2c@13e10000 {
471			compatible = "samsung,exynos7-hsi2c";
472			reg = <0x13e10000 0x1000>;
473			interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
474			#address-cells = <1>;
475			#size-cells = <0>;
476			pinctrl-names = "default";
477			pinctrl-0 = <&hs_i2c7_bus>;
478			clocks = <&clock_peric1 PCLK_HSI2C7>;
479			clock-names = "hsi2c";
480			status = "disabled";
481		};
482
483		hsi2c_8: i2c@14e20000 {
484			compatible = "samsung,exynos7-hsi2c";
485			reg = <0x14e20000 0x1000>;
486			interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>;
487			#address-cells = <1>;
488			#size-cells = <0>;
489			pinctrl-names = "default";
490			pinctrl-0 = <&hs_i2c8_bus>;
491			clocks = <&clock_peric1 PCLK_HSI2C8>;
492			clock-names = "hsi2c";
493			status = "disabled";
494		};
495
496		hsi2c_9: i2c@13680000 {
497			compatible = "samsung,exynos7-hsi2c";
498			reg = <0x13680000 0x1000>;
499			interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
500			#address-cells = <1>;
501			#size-cells = <0>;
502			pinctrl-names = "default";
503			pinctrl-0 = <&hs_i2c9_bus>;
504			clocks = <&clock_peric0 PCLK_HSI2C9>;
505			clock-names = "hsi2c";
506			status = "disabled";
507		};
508
509		hsi2c_10: i2c@13690000 {
510			compatible = "samsung,exynos7-hsi2c";
511			reg = <0x13690000 0x1000>;
512			interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
513			#address-cells = <1>;
514			#size-cells = <0>;
515			pinctrl-names = "default";
516			pinctrl-0 = <&hs_i2c10_bus>;
517			clocks = <&clock_peric0 PCLK_HSI2C10>;
518			clock-names = "hsi2c";
519			status = "disabled";
520		};
521
522		hsi2c_11: i2c@136a0000 {
523			compatible = "samsung,exynos7-hsi2c";
524			reg = <0x136a0000 0x1000>;
525			interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>;
526			#address-cells = <1>;
527			#size-cells = <0>;
528			pinctrl-names = "default";
529			pinctrl-0 = <&hs_i2c11_bus>;
530			clocks = <&clock_peric0 PCLK_HSI2C11>;
531			clock-names = "hsi2c";
532			status = "disabled";
533		};
534
535		pmu_system_controller: system-controller@105c0000 {
536			compatible = "samsung,exynos7-pmu", "syscon";
537			reg = <0x105c0000 0x5000>;
538		};
539
540		rtc: rtc@10590000 {
541			compatible = "samsung,s3c6410-rtc";
542			reg = <0x10590000 0x100>;
543			interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
544				     <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
545			clocks = <&clock_ccore PCLK_RTC>;
546			clock-names = "rtc";
547			status = "disabled";
548		};
549
550		watchdog: watchdog@101d0000 {
551			compatible = "samsung,exynos7-wdt";
552			reg = <0x101d0000 0x100>;
553			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
554			clocks = <&clock_peris PCLK_WDT>;
555			clock-names = "watchdog";
556			samsung,syscon-phandle = <&pmu_system_controller>;
557			status = "disabled";
558		};
559
560		gpu: gpu@14ac0000 {
561			compatible = "samsung,exynos5433-mali", "arm,mali-t760";
562			reg = <0x14ac0000 0x5000>;
563			interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
564				     <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
565				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
566			interrupt-names = "job", "mmu", "gpu";
567			status = "disabled";
568			/* TODO: operating points for DVFS, cooling device */
569		};
570
571		mmc_0: mmc@15740000 {
572			compatible = "samsung,exynos7-dw-mshc-smu";
573			interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
574			#address-cells = <1>;
575			#size-cells = <0>;
576			reg = <0x15740000 0x2000>;
577			clocks = <&clock_fsys1 ACLK_MMC0>,
578				 <&clock_top1 CLK_SCLK_MMC0>;
579			clock-names = "biu", "ciu";
580			fifo-depth = <0x40>;
581			status = "disabled";
582		};
583
584		mmc_1: mmc@15750000 {
585			compatible = "samsung,exynos7-dw-mshc";
586			interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
587			#address-cells = <1>;
588			#size-cells = <0>;
589			reg = <0x15750000 0x2000>;
590			clocks = <&clock_fsys1 ACLK_MMC1>,
591				 <&clock_top1 CLK_SCLK_MMC1>;
592			clock-names = "biu", "ciu";
593			fifo-depth = <0x40>;
594			status = "disabled";
595		};
596
597		mmc_2: mmc@15560000 {
598			compatible = "samsung,exynos7-dw-mshc-smu";
599			interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
600			#address-cells = <1>;
601			#size-cells = <0>;
602			reg = <0x15560000 0x2000>;
603			clocks = <&clock_fsys0 ACLK_MMC2>,
604				 <&clock_top1 CLK_SCLK_MMC2>;
605			clock-names = "biu", "ciu";
606			fifo-depth = <0x40>;
607			status = "disabled";
608		};
609
610		adc: adc@13620000 {
611			compatible = "samsung,exynos7-adc";
612			reg = <0x13620000 0x100>;
613			interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>;
614			clocks = <&clock_peric0 PCLK_ADCIF>;
615			clock-names = "adc";
616			#io-channel-cells = <1>;
617			status = "disabled";
618		};
619
620		pwm: pwm@136c0000 {
621			compatible = "samsung,exynos4210-pwm";
622			reg = <0x136c0000 0x100>;
623			interrupts = <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
624				     <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
625				     <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
626				     <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
627				     <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>;
628			samsung,pwm-outputs = <0>, <1>, <2>, <3>;
629			#pwm-cells = <3>;
630			clocks = <&clock_peric0 PCLK_PWM>;
631			clock-names = "timers";
632		};
633
634		tmuctrl_0: tmu@10060000 {
635			compatible = "samsung,exynos7-tmu";
636			reg = <0x10060000 0x200>;
637			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
638			clocks = <&clock_peris PCLK_TMU>,
639				 <&clock_peris SCLK_TMU>;
640			clock-names = "tmu_apbif", "tmu_sclk";
641			#thermal-sensor-cells = <0>;
642		};
643
644		ufs: ufs@15570000 {
645			compatible = "samsung,exynos7-ufs";
646			reg = <0x15570000 0x100>,  /* 0: HCI standard */
647				<0x15570100 0x100>,  /* 1: Vendor specificed */
648				<0x15571000 0x200>,  /* 2: UNIPRO */
649				<0x15572000 0x300>;  /* 3: UFS protector */
650			reg-names = "hci", "vs_hci", "unipro", "ufsp";
651			interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
652			clocks = <&clock_fsys1 ACLK_UFS20_LINK>,
653				<&clock_fsys1 SCLK_UFSUNIPRO20_USER>;
654			clock-names = "core_clk", "sclk_unipro_main";
655			freq-table-hz = <0 0>, <0 0>;
656			pinctrl-names = "default";
657			pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
658			phys = <&ufs_phy>;
659			phy-names = "ufs-phy";
660			status = "disabled";
661		};
662
663		ufs_phy: ufs-phy@15571800 {
664			compatible = "samsung,exynos7-ufs-phy";
665			reg = <0x15571800 0x240>;
666			reg-names = "phy-pma";
667			samsung,pmu-syscon = <&pmu_system_controller>;
668			#phy-cells = <0>;
669			clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,
670				 <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,
671				 <&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,
672				 <&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;
673			clock-names = "ref_clk", "rx1_symbol_clk",
674				      "rx0_symbol_clk",
675				      "tx0_symbol_clk";
676		};
677
678		usbdrd_phy: phy@15500000 {
679			compatible = "samsung,exynos7-usbdrd-phy";
680			reg = <0x15500000 0x100>;
681			clocks = <&clock_fsys0 ACLK_USBDRD300>,
682			       <&clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY>,
683			       <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>,
684			       <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>,
685			       <&clock_fsys0 SCLK_USBDRD300_REFCLK>;
686			clock-names = "phy", "ref", "phy_utmi", "phy_pipe", "itp";
687			samsung,pmu-syscon = <&pmu_system_controller>;
688			#phy-cells = <1>;
689		};
690
691		usbdrd: usb {
692			compatible = "samsung,exynos7-dwusb3";
693			clocks = <&clock_fsys0 ACLK_USBDRD300>,
694			       <&clock_fsys0 SCLK_USBDRD300_SUSPENDCLK>,
695			       <&clock_fsys0 ACLK_AXIUS_USBDRD30X_FSYS0X>;
696			clock-names = "usbdrd30", "usbdrd30_susp_clk",
697				"usbdrd30_axius_clk";
698			#address-cells = <1>;
699			#size-cells = <1>;
700			ranges;
701
702			usb@15400000 {
703				compatible = "snps,dwc3";
704				reg = <0x15400000 0x10000>;
705				interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
706				phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
707				phy-names = "usb2-phy", "usb3-phy";
708			};
709		};
710	};
711
712	thermal-zones {
713		atlas_thermal: cluster0-thermal {
714			polling-delay-passive = <0>; /* milliseconds */
715			polling-delay = <0>; /* milliseconds */
716			thermal-sensors = <&tmuctrl_0>;
717			#include "exynos7-trip-points.dtsi"
718		};
719	};
720
721	timer {
722		compatible = "arm,armv8-timer";
723		interrupts = <GIC_PPI 13
724				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
725			     <GIC_PPI 14
726				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
727			     <GIC_PPI 11
728				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
729			     <GIC_PPI 10
730				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
731	};
732};
733
734#include "exynos7-pinctrl.dtsi"
735#include "arm/exynos-syscon-restart.dtsi"
736