1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree fragment for LS1028A QDS board, serdes 7777
4 *
5 * Copyright 2019-2021 NXP
6 *
7 * Requires a LS1028A QDS board without lane B rework.
8 * Requires a SCH-30841 card without lane A/C rewire and with a FW with muxing
9 * disabled, plugged in slot 1.
10 */
11
12/dts-v1/;
13/plugin/;
14
15&mdio_slot1 {
16	#address-cells = <1>;
17	#size-cells = <0>;
18
19	/* 4 ports on AQR412 */
20	slot1_sxgmii0: ethernet-phy@0 {
21		reg = <0x0>;
22		compatible = "ethernet-phy-ieee802.3-c45";
23	};
24
25	slot1_sxgmii1: ethernet-phy@1 {
26		reg = <0x1>;
27		compatible = "ethernet-phy-ieee802.3-c45";
28	};
29
30	slot1_sxgmii2: ethernet-phy@2 {
31		reg = <0x2>;
32		compatible = "ethernet-phy-ieee802.3-c45";
33	};
34
35	slot1_sxgmii3: ethernet-phy@3 {
36		reg = <0x3>;
37		compatible = "ethernet-phy-ieee802.3-c45";
38	};
39};
40
41&mscc_felix_ports {
42	port@0 {
43		status = "okay";
44		phy-handle = <&slot1_sxgmii0>;
45		phy-mode = "2500base-x";
46	};
47
48	port@1 {
49		status = "okay";
50		phy-handle = <&slot1_sxgmii1>;
51		phy-mode = "2500base-x";
52	};
53
54	port@2 {
55		status = "okay";
56		phy-handle = <&slot1_sxgmii2>;
57		phy-mode = "2500base-x";
58	};
59
60	port@3 {
61		status = "okay";
62		phy-handle = <&slot1_sxgmii3>;
63		phy-mode = "2500base-x";
64	};
65};
66
67&mscc_felix {
68	status = "okay";
69};
70