1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
4 *
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
6 * Copyright 2018 NXP
7 *
8 * Mingkai Hu <Mingkai.hu@freescale.com>
9 */
10
11/dts-v1/;
12#include "fsl-ls1043a.dtsi"
13
14/ {
15	model = "LS1043A RDB Board";
16	compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
17
18	aliases {
19		serial0 = &duart0;
20		serial1 = &duart1;
21		serial2 = &duart2;
22		serial3 = &duart3;
23	};
24
25	chosen {
26		stdout-path = "serial0:115200n8";
27	};
28};
29
30&i2c0 {
31	status = "okay";
32	ina220@40 {
33		compatible = "ti,ina220";
34		reg = <0x40>;
35		shunt-resistor = <1000>;
36	};
37	adt7461a@4c {
38		compatible = "adi,adt7461";
39		reg = <0x4c>;
40	};
41	eeprom@52 {
42		compatible = "atmel,24c512";
43		reg = <0x52>;
44	};
45	eeprom@53 {
46		compatible = "atmel,24c512";
47		reg = <0x53>;
48	};
49	rtc@68 {
50		compatible = "pericom,pt7c4338";
51		reg = <0x68>;
52	};
53};
54
55&ifc {
56	status = "okay";
57	#address-cells = <2>;
58	#size-cells = <1>;
59	/* NOR, NAND Flashes and FPGA on board */
60	ranges = <0x0 0x0 0x0 0x60000000 0x08000000
61		  0x1 0x0 0x0 0x7e800000 0x00010000
62		  0x2 0x0 0x0 0x7fb00000 0x00000100>;
63
64		nor@0,0 {
65			compatible = "cfi-flash";
66			#address-cells = <1>;
67			#size-cells = <1>;
68			reg = <0x0 0x0 0x8000000>;
69			big-endian;
70			bank-width = <2>;
71			device-width = <1>;
72		};
73
74		nand@1,0 {
75			compatible = "fsl,ifc-nand";
76			#address-cells = <1>;
77			#size-cells = <1>;
78			reg = <0x1 0x0 0x10000>;
79		};
80
81		cpld: board-control@2,0 {
82			compatible = "fsl,ls1043ardb-cpld";
83			reg = <0x2 0x0 0x0000100>;
84		};
85};
86
87&dspi0 {
88	bus-num = <0>;
89	status = "okay";
90
91	flash@0 {
92		#address-cells = <1>;
93		#size-cells = <1>;
94		compatible = "n25q128a13", "jedec,spi-nor";  /* 16MB */
95		reg = <0>;
96		spi-max-frequency = <1000000>; /* input clock */
97	};
98
99	slic@2 {
100		compatible = "maxim,ds26522";
101		reg = <2>;
102		spi-max-frequency = <2000000>;
103		fsl,spi-cs-sck-delay = <100>;
104		fsl,spi-sck-cs-delay = <50>;
105	};
106
107	slic@3 {
108		compatible = "maxim,ds26522";
109		reg = <3>;
110		spi-max-frequency = <2000000>;
111		fsl,spi-cs-sck-delay = <100>;
112		fsl,spi-sck-cs-delay = <50>;
113	};
114};
115
116&duart0 {
117	status = "okay";
118};
119
120&duart1 {
121	status = "okay";
122};
123
124#include "fsl-ls1043-post.dtsi"
125
126&fman0 {
127	ethernet@e0000 {
128		phy-handle = <&qsgmii_phy1>;
129		phy-connection-type = "qsgmii";
130	};
131
132	ethernet@e2000 {
133		phy-handle = <&qsgmii_phy2>;
134		phy-connection-type = "qsgmii";
135	};
136
137	ethernet@e4000 {
138		phy-handle = <&rgmii_phy1>;
139		phy-connection-type = "rgmii-id";
140	};
141
142	ethernet@e6000 {
143		phy-handle = <&rgmii_phy2>;
144		phy-connection-type = "rgmii-id";
145	};
146
147	ethernet@e8000 {
148		phy-handle = <&qsgmii_phy3>;
149		phy-connection-type = "qsgmii";
150	};
151
152	ethernet@ea000 {
153		phy-handle = <&qsgmii_phy4>;
154		phy-connection-type = "qsgmii";
155	};
156
157	ethernet@f0000 { /* 10GEC1 */
158		phy-handle = <&aqr105_phy>;
159		phy-connection-type = "xgmii";
160	};
161
162	mdio@fc000 {
163		rgmii_phy1: ethernet-phy@1 {
164			reg = <0x1>;
165		};
166
167		rgmii_phy2: ethernet-phy@2 {
168			reg = <0x2>;
169		};
170
171		qsgmii_phy1: ethernet-phy@4 {
172			reg = <0x4>;
173		};
174
175		qsgmii_phy2: ethernet-phy@5 {
176			reg = <0x5>;
177		};
178
179		qsgmii_phy3: ethernet-phy@6 {
180			reg = <0x6>;
181		};
182
183		qsgmii_phy4: ethernet-phy@7 {
184			reg = <0x7>;
185		};
186	};
187
188	mdio@fd000 {
189		aqr105_phy: ethernet-phy@1 {
190			compatible = "ethernet-phy-ieee802.3-c45";
191			interrupts = <0 132 4>;
192			reg = <0x1>;
193		};
194	};
195};
196
197&uqe {
198	ucc_hdlc: ucc@2000 {
199		compatible = "fsl,ucc-hdlc";
200		rx-clock-name = "clk8";
201		tx-clock-name = "clk9";
202		fsl,rx-sync-clock = "rsync_pin";
203		fsl,tx-sync-clock = "tsync_pin";
204		fsl,tx-timeslot-mask = <0xfffffffe>;
205		fsl,rx-timeslot-mask = <0xfffffffe>;
206		fsl,tdm-framer-type = "e1";
207		fsl,tdm-id = <0>;
208		fsl,siram-entry-id = <0>;
209		fsl,tdm-interface;
210	};
211};
212
213&usb0 {
214	status = "okay";
215};
216
217&usb1 {
218	status = "okay";
219};
220