1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for NXP Layerscape-1043A family SoC.
4 *
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
6 * Copyright 2018, 2020 NXP
7 *
8 * Mingkai Hu <Mingkai.hu@freescale.com>
9 */
10
11#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12#include <dt-bindings/thermal/thermal.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14
15/ {
16	compatible = "fsl,ls1043a";
17	interrupt-parent = <&gic>;
18	#address-cells = <2>;
19	#size-cells = <2>;
20
21	aliases {
22		crypto = &crypto;
23		fman0 = &fman0;
24		ethernet0 = &enet0;
25		ethernet1 = &enet1;
26		ethernet2 = &enet2;
27		ethernet3 = &enet3;
28		ethernet4 = &enet4;
29		ethernet5 = &enet5;
30		ethernet6 = &enet6;
31		rtc1 = &ftm_alarm0;
32	};
33
34	cpus {
35		#address-cells = <1>;
36		#size-cells = <0>;
37
38		/*
39		 * We expect the enable-method for cpu's to be "psci", but this
40		 * is dependent on the SoC FW, which will fill this in.
41		 *
42		 * Currently supported enable-method is psci v0.2
43		 */
44		cpu0: cpu@0 {
45			device_type = "cpu";
46			compatible = "arm,cortex-a53";
47			reg = <0x0>;
48			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
49			next-level-cache = <&l2>;
50			cpu-idle-states = <&CPU_PH20>;
51			#cooling-cells = <2>;
52		};
53
54		cpu1: cpu@1 {
55			device_type = "cpu";
56			compatible = "arm,cortex-a53";
57			reg = <0x1>;
58			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
59			next-level-cache = <&l2>;
60			cpu-idle-states = <&CPU_PH20>;
61			#cooling-cells = <2>;
62		};
63
64		cpu2: cpu@2 {
65			device_type = "cpu";
66			compatible = "arm,cortex-a53";
67			reg = <0x2>;
68			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
69			next-level-cache = <&l2>;
70			cpu-idle-states = <&CPU_PH20>;
71			#cooling-cells = <2>;
72		};
73
74		cpu3: cpu@3 {
75			device_type = "cpu";
76			compatible = "arm,cortex-a53";
77			reg = <0x3>;
78			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
79			next-level-cache = <&l2>;
80			cpu-idle-states = <&CPU_PH20>;
81			#cooling-cells = <2>;
82		};
83
84		l2: l2-cache {
85			compatible = "cache";
86		};
87	};
88
89	idle-states {
90		/*
91		 * PSCI node is not added default, U-boot will add missing
92		 * parts if it determines to use PSCI.
93		 */
94		entry-method = "psci";
95
96		CPU_PH20: cpu-ph20 {
97			compatible = "arm,idle-state";
98			idle-state-name = "PH20";
99			arm,psci-suspend-param = <0x0>;
100			entry-latency-us = <1000>;
101			exit-latency-us = <1000>;
102			min-residency-us = <3000>;
103		};
104	};
105
106	memory@80000000 {
107		device_type = "memory";
108		reg = <0x0 0x80000000 0 0x80000000>;
109		      /* DRAM space 1, size: 2GiB DRAM */
110	};
111
112	reserved-memory {
113		#address-cells = <2>;
114		#size-cells = <2>;
115		ranges;
116
117		bman_fbpr: bman-fbpr {
118			compatible = "shared-dma-pool";
119			size = <0 0x1000000>;
120			alignment = <0 0x1000000>;
121			no-map;
122		};
123
124		qman_fqd: qman-fqd {
125			compatible = "shared-dma-pool";
126			size = <0 0x400000>;
127			alignment = <0 0x400000>;
128			no-map;
129		};
130
131		qman_pfdr: qman-pfdr {
132			compatible = "shared-dma-pool";
133			size = <0 0x2000000>;
134			alignment = <0 0x2000000>;
135			no-map;
136		};
137	};
138
139	sysclk: sysclk {
140		compatible = "fixed-clock";
141		#clock-cells = <0>;
142		clock-frequency = <100000000>;
143		clock-output-names = "sysclk";
144	};
145
146	reboot {
147		compatible = "syscon-reboot";
148		regmap = <&dcfg>;
149		offset = <0xb0>;
150		mask = <0x02>;
151	};
152
153	thermal-zones {
154		ddr-controller {
155			polling-delay-passive = <1000>;
156			polling-delay = <5000>;
157			thermal-sensors = <&tmu 0>;
158
159			trips {
160				ddr-ctrler-alert {
161					temperature = <85000>;
162					hysteresis = <2000>;
163					type = "passive";
164				};
165
166				ddr-ctrler-crit {
167					temperature = <95000>;
168					hysteresis = <2000>;
169					type = "critical";
170				};
171			};
172		};
173
174		serdes {
175			polling-delay-passive = <1000>;
176			polling-delay = <5000>;
177			thermal-sensors = <&tmu 1>;
178
179			trips {
180				serdes-alert {
181					temperature = <85000>;
182					hysteresis = <2000>;
183					type = "passive";
184				};
185
186				serdes-crit {
187					temperature = <95000>;
188					hysteresis = <2000>;
189					type = "critical";
190				};
191			};
192		};
193
194		fman {
195			polling-delay-passive = <1000>;
196			polling-delay = <5000>;
197			thermal-sensors = <&tmu 2>;
198
199			trips {
200				fman-alert {
201					temperature = <85000>;
202					hysteresis = <2000>;
203					type = "passive";
204				};
205
206				fman-crit {
207					temperature = <95000>;
208					hysteresis = <2000>;
209					type = "critical";
210				};
211			};
212		};
213
214		core-cluster {
215			polling-delay-passive = <1000>;
216			polling-delay = <5000>;
217			thermal-sensors = <&tmu 3>;
218
219			trips {
220				core_cluster_alert: core-cluster-alert {
221					temperature = <85000>;
222					hysteresis = <2000>;
223					type = "passive";
224				};
225
226				core_cluster_crit: core-cluster-crit {
227					temperature = <95000>;
228					hysteresis = <2000>;
229					type = "critical";
230				};
231			};
232
233			cooling-maps {
234				map0 {
235					trip = <&core_cluster_alert>;
236					cooling-device =
237						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
238						<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
239						<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
240						<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
241				};
242			};
243		};
244
245		sec {
246			polling-delay-passive = <1000>;
247			polling-delay = <5000>;
248			thermal-sensors = <&tmu 4>;
249
250			trips {
251				sec-alert {
252					temperature = <85000>;
253					hysteresis = <2000>;
254					type = "passive";
255				};
256
257				sec-crit {
258					temperature = <95000>;
259					hysteresis = <2000>;
260					type = "critical";
261				};
262			};
263		};
264	};
265
266	timer {
267		compatible = "arm,armv8-timer";
268		interrupts = <1 13 0xf08>, /* Physical Secure PPI */
269			     <1 14 0xf08>, /* Physical Non-Secure PPI */
270			     <1 11 0xf08>, /* Virtual PPI */
271			     <1 10 0xf08>; /* Hypervisor PPI */
272		fsl,erratum-a008585;
273	};
274
275	pmu {
276		compatible = "arm,armv8-pmuv3";
277		interrupts = <0 106 0x4>,
278			     <0 107 0x4>,
279			     <0 95 0x4>,
280			     <0 97 0x4>;
281		interrupt-affinity = <&cpu0>,
282				     <&cpu1>,
283				     <&cpu2>,
284				     <&cpu3>;
285	};
286
287	gic: interrupt-controller@1400000 {
288		compatible = "arm,gic-400";
289		#interrupt-cells = <3>;
290		interrupt-controller;
291		reg = <0x0 0x1401000 0 0x1000>, /* GICD */
292		      <0x0 0x1402000 0 0x2000>, /* GICC */
293		      <0x0 0x1404000 0 0x2000>, /* GICH */
294		      <0x0 0x1406000 0 0x2000>; /* GICV */
295		interrupts = <1 9 0xf08>;
296	};
297
298	soc: soc {
299		compatible = "simple-bus";
300		#address-cells = <2>;
301		#size-cells = <2>;
302		ranges;
303
304		clockgen: clocking@1ee1000 {
305			compatible = "fsl,ls1043a-clockgen";
306			reg = <0x0 0x1ee1000 0x0 0x1000>;
307			#clock-cells = <2>;
308			clocks = <&sysclk>;
309		};
310
311		scfg: scfg@1570000 {
312			compatible = "fsl,ls1043a-scfg", "syscon";
313			reg = <0x0 0x1570000 0x0 0x10000>;
314			big-endian;
315			#address-cells = <1>;
316			#size-cells = <1>;
317			ranges = <0x0 0x0 0x1570000 0x10000>;
318
319			extirq: interrupt-controller@1ac {
320				compatible = "fsl,ls1043a-extirq";
321				#interrupt-cells = <2>;
322				#address-cells = <0>;
323				interrupt-controller;
324				reg = <0x1ac 4>;
325				interrupt-map =
326					<0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
327					<1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
328					<2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
329					<3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
330					<4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
331					<5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
332					<6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
333					<7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
334					<8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
335					<9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
336					<10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
337					<11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
338				interrupt-map-mask = <0xf 0x0>;
339			};
340		};
341
342		crypto: crypto@1700000 {
343			compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
344				     "fsl,sec-v4.0";
345			fsl,sec-era = <3>;
346			#address-cells = <1>;
347			#size-cells = <1>;
348			ranges = <0x0 0x00 0x1700000 0x100000>;
349			reg = <0x00 0x1700000 0x0 0x100000>;
350			interrupts = <0 75 0x4>;
351			dma-coherent;
352
353			sec_jr0: jr@10000 {
354				compatible = "fsl,sec-v5.4-job-ring",
355					     "fsl,sec-v5.0-job-ring",
356					     "fsl,sec-v4.0-job-ring";
357				reg = <0x10000 0x10000>;
358				interrupts = <0 71 0x4>;
359			};
360
361			sec_jr1: jr@20000 {
362				compatible = "fsl,sec-v5.4-job-ring",
363					     "fsl,sec-v5.0-job-ring",
364					     "fsl,sec-v4.0-job-ring";
365				reg = <0x20000 0x10000>;
366				interrupts = <0 72 0x4>;
367			};
368
369			sec_jr2: jr@30000 {
370				compatible = "fsl,sec-v5.4-job-ring",
371					     "fsl,sec-v5.0-job-ring",
372					     "fsl,sec-v4.0-job-ring";
373				reg = <0x30000 0x10000>;
374				interrupts = <0 73 0x4>;
375			};
376
377			sec_jr3: jr@40000 {
378				compatible = "fsl,sec-v5.4-job-ring",
379					     "fsl,sec-v5.0-job-ring",
380					     "fsl,sec-v4.0-job-ring";
381				reg = <0x40000 0x10000>;
382				interrupts = <0 74 0x4>;
383			};
384		};
385
386		sfp: efuse@1e80000 {
387			compatible = "fsl,ls1021a-sfp";
388			reg = <0x0 0x1e80000 0x0 0x10000>;
389			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
390					    QORIQ_CLK_PLL_DIV(4)>;
391			clock-names = "sfp";
392		};
393
394		dcfg: dcfg@1ee0000 {
395			compatible = "fsl,ls1043a-dcfg", "syscon";
396			reg = <0x0 0x1ee0000 0x0 0x10000>;
397			big-endian;
398		};
399
400		ifc: memory-controller@1530000 {
401			compatible = "fsl,ifc";
402			reg = <0x0 0x1530000 0x0 0x10000>;
403			interrupts = <0 43 0x4>;
404		};
405
406		qspi: spi@1550000 {
407			compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
408			#address-cells = <1>;
409			#size-cells = <0>;
410			reg = <0x0 0x1550000 0x0 0x10000>,
411				<0x0 0x40000000 0x0 0x4000000>;
412			reg-names = "QuadSPI", "QuadSPI-memory";
413			interrupts = <0 99 0x4>;
414			clock-names = "qspi_en", "qspi";
415			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
416					    QORIQ_CLK_PLL_DIV(1)>,
417				 <&clockgen QORIQ_CLK_PLATFORM_PLL
418					    QORIQ_CLK_PLL_DIV(1)>;
419			status = "disabled";
420		};
421
422		esdhc: esdhc@1560000 {
423			compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
424			reg = <0x0 0x1560000 0x0 0x10000>;
425			interrupts = <0 62 0x4>;
426			clock-frequency = <0>;
427			voltage-ranges = <1800 1800 3300 3300>;
428			sdhci,auto-cmd12;
429			big-endian;
430			bus-width = <4>;
431		};
432
433		ddr: memory-controller@1080000 {
434			compatible = "fsl,qoriq-memory-controller";
435			reg = <0x0 0x1080000 0x0 0x1000>;
436			interrupts = <0 144 0x4>;
437			big-endian;
438		};
439
440		tmu: tmu@1f00000 {
441			compatible = "fsl,qoriq-tmu";
442			reg = <0x0 0x1f00000 0x0 0x10000>;
443			interrupts = <0 33 0x4>;
444			fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
445			fsl,tmu-calibration = <0x00000000 0x00000023
446					       0x00000001 0x0000002a
447					       0x00000002 0x00000031
448					       0x00000003 0x00000037
449					       0x00000004 0x0000003e
450					       0x00000005 0x00000044
451					       0x00000006 0x0000004b
452					       0x00000007 0x00000051
453					       0x00000008 0x00000058
454					       0x00000009 0x0000005e
455					       0x0000000a 0x00000065
456					       0x0000000b 0x0000006b
457
458					       0x00010000 0x00000023
459					       0x00010001 0x0000002b
460					       0x00010002 0x00000033
461					       0x00010003 0x0000003b
462					       0x00010004 0x00000043
463					       0x00010005 0x0000004b
464					       0x00010006 0x00000054
465					       0x00010007 0x0000005c
466					       0x00010008 0x00000064
467					       0x00010009 0x0000006c
468
469					       0x00020000 0x00000021
470					       0x00020001 0x0000002c
471					       0x00020002 0x00000036
472					       0x00020003 0x00000040
473					       0x00020004 0x0000004b
474					       0x00020005 0x00000055
475					       0x00020006 0x0000005f
476
477					       0x00030000 0x00000013
478					       0x00030001 0x0000001d
479					       0x00030002 0x00000028
480					       0x00030003 0x00000032
481					       0x00030004 0x0000003d
482					       0x00030005 0x00000047
483					       0x00030006 0x00000052
484					       0x00030007 0x0000005c>;
485			#thermal-sensor-cells = <1>;
486		};
487
488		qman: qman@1880000 {
489			compatible = "fsl,qman";
490			reg = <0x0 0x1880000 0x0 0x10000>;
491			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
492			memory-region = <&qman_fqd &qman_pfdr>;
493		};
494
495		bman: bman@1890000 {
496			compatible = "fsl,bman";
497			reg = <0x0 0x1890000 0x0 0x10000>;
498			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
499			memory-region = <&bman_fbpr>;
500		};
501
502		bportals: bman-portals@508000000 {
503			ranges = <0x0 0x5 0x08000000 0x8000000>;
504		};
505
506		qportals: qman-portals@500000000 {
507			ranges = <0x0 0x5 0x00000000 0x8000000>;
508		};
509
510		dspi0: spi@2100000 {
511			compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
512			#address-cells = <1>;
513			#size-cells = <0>;
514			reg = <0x0 0x2100000 0x0 0x10000>;
515			interrupts = <0 64 0x4>;
516			clock-names = "dspi";
517			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
518					    QORIQ_CLK_PLL_DIV(1)>;
519			spi-num-chipselects = <5>;
520			big-endian;
521			status = "disabled";
522		};
523
524		dspi1: spi@2110000 {
525			compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
526			#address-cells = <1>;
527			#size-cells = <0>;
528			reg = <0x0 0x2110000 0x0 0x10000>;
529			interrupts = <0 65 0x4>;
530			clock-names = "dspi";
531			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
532					    QORIQ_CLK_PLL_DIV(1)>;
533			spi-num-chipselects = <5>;
534			big-endian;
535			status = "disabled";
536		};
537
538		i2c0: i2c@2180000 {
539			compatible = "fsl,vf610-i2c";
540			#address-cells = <1>;
541			#size-cells = <0>;
542			reg = <0x0 0x2180000 0x0 0x10000>;
543			interrupts = <0 56 0x4>;
544			clock-names = "i2c";
545			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
546					    QORIQ_CLK_PLL_DIV(1)>;
547			dmas = <&edma0 1 38>,
548			       <&edma0 1 39>;
549			dma-names = "rx", "tx";
550			status = "disabled";
551		};
552
553		i2c1: i2c@2190000 {
554			compatible = "fsl,vf610-i2c";
555			#address-cells = <1>;
556			#size-cells = <0>;
557			reg = <0x0 0x2190000 0x0 0x10000>;
558			interrupts = <0 57 0x4>;
559			clock-names = "i2c";
560			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
561					    QORIQ_CLK_PLL_DIV(1)>;
562			status = "disabled";
563		};
564
565		i2c2: i2c@21a0000 {
566			compatible = "fsl,vf610-i2c";
567			#address-cells = <1>;
568			#size-cells = <0>;
569			reg = <0x0 0x21a0000 0x0 0x10000>;
570			interrupts = <0 58 0x4>;
571			clock-names = "i2c";
572			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
573					    QORIQ_CLK_PLL_DIV(1)>;
574			status = "disabled";
575		};
576
577		i2c3: i2c@21b0000 {
578			compatible = "fsl,vf610-i2c";
579			#address-cells = <1>;
580			#size-cells = <0>;
581			reg = <0x0 0x21b0000 0x0 0x10000>;
582			interrupts = <0 59 0x4>;
583			clock-names = "i2c";
584			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
585					    QORIQ_CLK_PLL_DIV(1)>;
586			status = "disabled";
587		};
588
589		duart0: serial@21c0500 {
590			compatible = "fsl,ns16550", "ns16550a";
591			reg = <0x00 0x21c0500 0x0 0x100>;
592			interrupts = <0 54 0x4>;
593			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
594					    QORIQ_CLK_PLL_DIV(1)>;
595		};
596
597		duart1: serial@21c0600 {
598			compatible = "fsl,ns16550", "ns16550a";
599			reg = <0x00 0x21c0600 0x0 0x100>;
600			interrupts = <0 54 0x4>;
601			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
602					    QORIQ_CLK_PLL_DIV(1)>;
603		};
604
605		duart2: serial@21d0500 {
606			compatible = "fsl,ns16550", "ns16550a";
607			reg = <0x0 0x21d0500 0x0 0x100>;
608			interrupts = <0 55 0x4>;
609			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
610					    QORIQ_CLK_PLL_DIV(1)>;
611		};
612
613		duart3: serial@21d0600 {
614			compatible = "fsl,ns16550", "ns16550a";
615			reg = <0x0 0x21d0600 0x0 0x100>;
616			interrupts = <0 55 0x4>;
617			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
618					    QORIQ_CLK_PLL_DIV(1)>;
619		};
620
621		gpio1: gpio@2300000 {
622			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
623			reg = <0x0 0x2300000 0x0 0x10000>;
624			interrupts = <0 66 0x4>;
625			gpio-controller;
626			#gpio-cells = <2>;
627			interrupt-controller;
628			#interrupt-cells = <2>;
629		};
630
631		gpio2: gpio@2310000 {
632			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
633			reg = <0x0 0x2310000 0x0 0x10000>;
634			interrupts = <0 67 0x4>;
635			gpio-controller;
636			#gpio-cells = <2>;
637			interrupt-controller;
638			#interrupt-cells = <2>;
639		};
640
641		gpio3: gpio@2320000 {
642			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
643			reg = <0x0 0x2320000 0x0 0x10000>;
644			interrupts = <0 68 0x4>;
645			gpio-controller;
646			#gpio-cells = <2>;
647			interrupt-controller;
648			#interrupt-cells = <2>;
649		};
650
651		gpio4: gpio@2330000 {
652			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
653			reg = <0x0 0x2330000 0x0 0x10000>;
654			interrupts = <0 134 0x4>;
655			gpio-controller;
656			#gpio-cells = <2>;
657			interrupt-controller;
658			#interrupt-cells = <2>;
659		};
660
661		uqe: uqe@2400000 {
662			#address-cells = <1>;
663			#size-cells = <1>;
664			compatible = "fsl,qe", "simple-bus";
665			ranges = <0x0 0x0 0x2400000 0x40000>;
666			reg = <0x0 0x2400000 0x0 0x480>;
667			brg-frequency = <100000000>;
668			bus-frequency = <200000000>;
669			fsl,qe-num-riscs = <1>;
670			fsl,qe-num-snums = <28>;
671
672			qeic: qeic@80 {
673				compatible = "fsl,qe-ic";
674				reg = <0x80 0x80>;
675				#address-cells = <0>;
676				interrupt-controller;
677				#interrupt-cells = <1>;
678				interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
679					     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
680			};
681
682			si1: si@700 {
683				#address-cells = <1>;
684				#size-cells = <0>;
685				compatible = "fsl,ls1043-qe-si",
686						"fsl,t1040-qe-si";
687				reg = <0x700 0x80>;
688			};
689
690			siram1: siram@1000 {
691				#address-cells = <1>;
692				#size-cells = <1>;
693				compatible = "fsl,ls1043-qe-siram",
694						"fsl,t1040-qe-siram";
695				reg = <0x1000 0x800>;
696			};
697
698			ucc@2000 {
699				cell-index = <1>;
700				reg = <0x2000 0x200>;
701				interrupts = <32>;
702				interrupt-parent = <&qeic>;
703			};
704
705			ucc@2200 {
706				cell-index = <3>;
707				reg = <0x2200 0x200>;
708				interrupts = <34>;
709				interrupt-parent = <&qeic>;
710			};
711
712			muram@10000 {
713				#address-cells = <1>;
714				#size-cells = <1>;
715				compatible = "fsl,qe-muram", "fsl,cpm-muram";
716				ranges = <0x0 0x10000 0x6000>;
717
718				data-only@0 {
719					compatible = "fsl,qe-muram-data",
720					"fsl,cpm-muram-data";
721					reg = <0x0 0x6000>;
722				};
723			};
724		};
725
726		lpuart0: serial@2950000 {
727			compatible = "fsl,ls1021a-lpuart";
728			reg = <0x0 0x2950000 0x0 0x1000>;
729			interrupts = <0 48 0x4>;
730			clocks = <&clockgen QORIQ_CLK_SYSCLK 0>;
731			clock-names = "ipg";
732			status = "disabled";
733		};
734
735		lpuart1: serial@2960000 {
736			compatible = "fsl,ls1021a-lpuart";
737			reg = <0x0 0x2960000 0x0 0x1000>;
738			interrupts = <0 49 0x4>;
739			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
740					    QORIQ_CLK_PLL_DIV(1)>;
741			clock-names = "ipg";
742			status = "disabled";
743		};
744
745		lpuart2: serial@2970000 {
746			compatible = "fsl,ls1021a-lpuart";
747			reg = <0x0 0x2970000 0x0 0x1000>;
748			interrupts = <0 50 0x4>;
749			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
750					    QORIQ_CLK_PLL_DIV(1)>;
751			clock-names = "ipg";
752			status = "disabled";
753		};
754
755		lpuart3: serial@2980000 {
756			compatible = "fsl,ls1021a-lpuart";
757			reg = <0x0 0x2980000 0x0 0x1000>;
758			interrupts = <0 51 0x4>;
759			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
760					    QORIQ_CLK_PLL_DIV(1)>;
761			clock-names = "ipg";
762			status = "disabled";
763		};
764
765		lpuart4: serial@2990000 {
766			compatible = "fsl,ls1021a-lpuart";
767			reg = <0x0 0x2990000 0x0 0x1000>;
768			interrupts = <0 52 0x4>;
769			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
770					    QORIQ_CLK_PLL_DIV(1)>;
771			clock-names = "ipg";
772			status = "disabled";
773		};
774
775		lpuart5: serial@29a0000 {
776			compatible = "fsl,ls1021a-lpuart";
777			reg = <0x0 0x29a0000 0x0 0x1000>;
778			interrupts = <0 53 0x4>;
779			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
780					    QORIQ_CLK_PLL_DIV(1)>;
781			clock-names = "ipg";
782			status = "disabled";
783		};
784
785		wdog0: watchdog@2ad0000 {
786			compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
787			reg = <0x0 0x2ad0000 0x0 0x10000>;
788			interrupts = <0 83 0x4>;
789			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
790					    QORIQ_CLK_PLL_DIV(1)>;
791			clock-names = "wdog";
792			big-endian;
793		};
794
795		edma0: dma-controller@2c00000 {
796			#dma-cells = <2>;
797			compatible = "fsl,vf610-edma";
798			reg = <0x0 0x2c00000 0x0 0x10000>,
799			      <0x0 0x2c10000 0x0 0x10000>,
800			      <0x0 0x2c20000 0x0 0x10000>;
801			interrupts = <0 103 0x4>,
802				     <0 103 0x4>;
803			interrupt-names = "edma-tx", "edma-err";
804			dma-channels = <32>;
805			big-endian;
806			clock-names = "dmamux0", "dmamux1";
807			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
808					    QORIQ_CLK_PLL_DIV(1)>,
809				 <&clockgen QORIQ_CLK_PLATFORM_PLL
810					    QORIQ_CLK_PLL_DIV(1)>;
811		};
812
813		usb0: usb@2f00000 {
814			compatible = "snps,dwc3";
815			reg = <0x0 0x2f00000 0x0 0x10000>;
816			interrupts = <0 60 0x4>;
817			dr_mode = "host";
818			snps,quirk-frame-length-adjustment = <0x20>;
819			snps,dis_rxdet_inp3_quirk;
820			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
821			status = "disabled";
822		};
823
824		usb1: usb@3000000 {
825			compatible = "snps,dwc3";
826			reg = <0x0 0x3000000 0x0 0x10000>;
827			interrupts = <0 61 0x4>;
828			dr_mode = "host";
829			snps,quirk-frame-length-adjustment = <0x20>;
830			snps,dis_rxdet_inp3_quirk;
831			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
832			status = "disabled";
833		};
834
835		usb2: usb@3100000 {
836			compatible = "snps,dwc3";
837			reg = <0x0 0x3100000 0x0 0x10000>;
838			interrupts = <0 63 0x4>;
839			dr_mode = "host";
840			snps,quirk-frame-length-adjustment = <0x20>;
841			snps,dis_rxdet_inp3_quirk;
842			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
843			status = "disabled";
844		};
845
846		sata: sata@3200000 {
847			compatible = "fsl,ls1043a-ahci";
848			reg = <0x0 0x3200000 0x0 0x10000>,
849				<0x0 0x20140520 0x0 0x4>;
850			reg-names = "ahci", "sata-ecc";
851			interrupts = <0 69 0x4>;
852			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
853					    QORIQ_CLK_PLL_DIV(1)>;
854			dma-coherent;
855		};
856
857		msi1: msi-controller1@1571000 {
858			compatible = "fsl,ls1043a-msi";
859			reg = <0x0 0x1571000 0x0 0x8>;
860			msi-controller;
861			interrupts = <0 116 0x4>;
862		};
863
864		msi2: msi-controller2@1572000 {
865			compatible = "fsl,ls1043a-msi";
866			reg = <0x0 0x1572000 0x0 0x8>;
867			msi-controller;
868			interrupts = <0 126 0x4>;
869		};
870
871		msi3: msi-controller3@1573000 {
872			compatible = "fsl,ls1043a-msi";
873			reg = <0x0 0x1573000 0x0 0x8>;
874			msi-controller;
875			interrupts = <0 160 0x4>;
876		};
877
878		pcie1: pcie@3400000 {
879			compatible = "fsl,ls1043a-pcie";
880			reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
881			      <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
882			reg-names = "regs", "config";
883			interrupts = <0 118 0x4>, /* controller interrupt */
884				     <0 117 0x4>; /* PME interrupt */
885			interrupt-names = "intr", "pme";
886			#address-cells = <3>;
887			#size-cells = <2>;
888			device_type = "pci";
889			dma-coherent;
890			num-viewport = <6>;
891			bus-range = <0x0 0xff>;
892			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
893				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
894			msi-parent = <&msi1>, <&msi2>, <&msi3>;
895			#interrupt-cells = <1>;
896			interrupt-map-mask = <0 0 0 7>;
897			interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
898					<0000 0 0 2 &gic 0 111 0x4>,
899					<0000 0 0 3 &gic 0 112 0x4>,
900					<0000 0 0 4 &gic 0 113 0x4>;
901			status = "disabled";
902		};
903
904		pcie2: pcie@3500000 {
905			compatible = "fsl,ls1043a-pcie";
906			reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
907			      <0x48 0x00000000 0x0 0x00002000>; /* configuration space */
908			reg-names = "regs", "config";
909			interrupts = <0 128 0x4>,
910				     <0 127 0x4>;
911			interrupt-names = "intr", "pme";
912			#address-cells = <3>;
913			#size-cells = <2>;
914			device_type = "pci";
915			dma-coherent;
916			num-viewport = <6>;
917			bus-range = <0x0 0xff>;
918			ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
919				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
920			msi-parent = <&msi1>, <&msi2>, <&msi3>;
921			#interrupt-cells = <1>;
922			interrupt-map-mask = <0 0 0 7>;
923			interrupt-map = <0000 0 0 1 &gic 0 120  0x4>,
924					<0000 0 0 2 &gic 0 121 0x4>,
925					<0000 0 0 3 &gic 0 122 0x4>,
926					<0000 0 0 4 &gic 0 123 0x4>;
927			status = "disabled";
928		};
929
930		pcie3: pcie@3600000 {
931			compatible = "fsl,ls1043a-pcie";
932			reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
933			      <0x50 0x00000000 0x0 0x00002000>; /* configuration space */
934			reg-names = "regs", "config";
935			interrupts = <0 162 0x4>,
936				     <0 161 0x4>;
937			interrupt-names = "intr", "pme";
938			#address-cells = <3>;
939			#size-cells = <2>;
940			device_type = "pci";
941			dma-coherent;
942			num-viewport = <6>;
943			bus-range = <0x0 0xff>;
944			ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
945				  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
946			msi-parent = <&msi1>, <&msi2>, <&msi3>;
947			#interrupt-cells = <1>;
948			interrupt-map-mask = <0 0 0 7>;
949			interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
950					<0000 0 0 2 &gic 0 155 0x4>,
951					<0000 0 0 3 &gic 0 156 0x4>,
952					<0000 0 0 4 &gic 0 157 0x4>;
953			status = "disabled";
954		};
955
956		qdma: dma-controller@8380000 {
957			compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
958			reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
959			      <0x0 0x8390000 0x0 0x10000>, /* Status regs */
960			      <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
961			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
962				     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
963				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
964				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
965				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
966			interrupt-names = "qdma-error", "qdma-queue0",
967				"qdma-queue1", "qdma-queue2", "qdma-queue3";
968			dma-channels = <8>;
969			block-number = <1>;
970			block-offset = <0x10000>;
971			fsl,dma-queues = <2>;
972			status-sizes = <64>;
973			queue-sizes = <64 64>;
974			big-endian;
975		};
976
977		rcpm: power-controller@1ee2140 {
978			compatible = "fsl,ls1043a-rcpm", "fsl,qoriq-rcpm-2.1+";
979			reg = <0x0 0x1ee2140 0x0 0x4>;
980			#fsl,rcpm-wakeup-cells = <1>;
981		};
982
983		ftm_alarm0: timer@29d0000 {
984			compatible = "fsl,ls1043a-ftm-alarm";
985			reg = <0x0 0x29d0000 0x0 0x10000>;
986			fsl,rcpm-wakeup = <&rcpm 0x20000>;
987			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
988			big-endian;
989		};
990	};
991
992	firmware {
993		optee {
994			compatible = "linaro,optee-tz";
995			method = "smc";
996		};
997	};
998
999};
1000
1001#include "qoriq-qman-portals.dtsi"
1002#include "qoriq-bman-portals.dtsi"
1003