1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2020 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/leds/common.h>
8#include <dt-bindings/phy/phy-imx8-pcie.h>
9
10/ {
11	aliases {
12		ethernet1 = &eth1;
13		usb0 = &usbotg1;
14		usb1 = &usbotg2;
15	};
16
17	led-controller {
18		compatible = "gpio-leds";
19		pinctrl-names = "default";
20		pinctrl-0 = <&pinctrl_gpio_leds>;
21
22		led-0 {
23			function = LED_FUNCTION_STATUS;
24			color = <LED_COLOR_ID_GREEN>;
25			gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
26			default-state = "on";
27			linux,default-trigger = "heartbeat";
28		};
29
30		led-1 {
31			function = LED_FUNCTION_STATUS;
32			color = <LED_COLOR_ID_RED>;
33			gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
34			default-state = "off";
35		};
36	};
37
38	pcie0_refclk: pcie0-refclk {
39		compatible = "fixed-clock";
40		#clock-cells = <0>;
41		clock-frequency = <100000000>;
42	};
43
44	pps {
45		compatible = "pps-gpio";
46		pinctrl-names = "default";
47		pinctrl-0 = <&pinctrl_pps>;
48		gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
49		status = "okay";
50	};
51
52	reg_3p3v: regulator-3p3v {
53		compatible = "regulator-fixed";
54		regulator-name = "3P3V";
55		regulator-min-microvolt = <3300000>;
56		regulator-max-microvolt = <3300000>;
57		regulator-always-on;
58	};
59
60	reg_usb_otg1_vbus: regulator-usb-otg1 {
61		pinctrl-names = "default";
62		pinctrl-0 = <&pinctrl_reg_usb1_en>;
63		compatible = "regulator-fixed";
64		regulator-name = "usb_otg1_vbus";
65		gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
66		enable-active-high;
67		regulator-min-microvolt = <5000000>;
68		regulator-max-microvolt = <5000000>;
69	};
70
71	reg_usb_otg2_vbus: regulator-usb-otg2 {
72		pinctrl-names = "default";
73		pinctrl-0 = <&pinctrl_reg_usb2_en>;
74		compatible = "regulator-fixed";
75		regulator-name = "usb_otg2_vbus";
76		gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
77		enable-active-high;
78		regulator-min-microvolt = <5000000>;
79		regulator-max-microvolt = <5000000>;
80	};
81};
82
83/* off-board header */
84&ecspi2 {
85	pinctrl-names = "default";
86	pinctrl-0 = <&pinctrl_spi2>;
87	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
88	status = "okay";
89};
90
91&gpio1 {
92	gpio-line-names = "rs485_term", "mipi_gpio4", "", "",
93		"", "", "pci_usb_sel", "dio0",
94		"", "dio1", "", "", "", "", "", "",
95		"", "", "", "", "", "", "", "",
96		"", "", "", "", "", "", "", "";
97};
98
99&gpio4 {
100	gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2",
101		"mipi_gpio1", "", "", "pci_wdis#",
102		"", "", "", "", "", "", "", "",
103		"", "", "", "", "", "", "", "",
104		"", "", "", "", "", "", "", "";
105};
106
107&i2c2 {
108	clock-frequency = <400000>;
109	pinctrl-names = "default";
110	pinctrl-0 = <&pinctrl_i2c2>;
111	status = "okay";
112
113	accelerometer@19 {
114		pinctrl-names = "default";
115		pinctrl-0 = <&pinctrl_accel>;
116		compatible = "st,lis2de12";
117		reg = <0x19>;
118		st,drdy-int-pin = <1>;
119		interrupt-parent = <&gpio4>;
120		interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
121		interrupt-names = "INT1";
122	};
123};
124
125/* off-board header */
126&i2c3 {
127	clock-frequency = <400000>;
128	pinctrl-names = "default";
129	pinctrl-0 = <&pinctrl_i2c3>;
130	status = "okay";
131};
132
133&pcie_phy {
134	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
135	fsl,clkreq-unsupported;
136	clocks = <&pcie0_refclk>;
137	clock-names = "ref";
138	status = "okay";
139};
140
141&pcie0 {
142	pinctrl-names = "default";
143	pinctrl-0 = <&pinctrl_pcie0>;
144	reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
145	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
146		 <&clk IMX8MM_CLK_PCIE1_AUX>;
147	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
148			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
149	assigned-clock-rates = <10000000>, <250000000>;
150	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
151				 <&clk IMX8MM_SYS_PLL2_250M>;
152	status = "okay";
153
154	pcie@0,0 {
155		reg = <0x0000 0 0 0 0>;
156		#address-cells = <1>;
157		#size-cells = <0>;
158
159		pcie@1,0 {
160			reg = <0x0000 0 0 0 0>;
161			#address-cells = <1>;
162			#size-cells = <0>;
163
164			pcie@2,3 {
165				reg = <0x1800 0 0 0 0>;
166				#address-cells = <1>;
167				#size-cells = <0>;
168
169				eth1: pcie@5,0 {
170					reg = <0x0000 0 0 0 0>;
171					#address-cells = <1>;
172					#size-cells = <0>;
173
174					local-mac-address = [00 00 00 00 00 00];
175				};
176			};
177		};
178	};
179};
180
181/* off-board header */
182&sai3 {
183	pinctrl-names = "default";
184	pinctrl-0 = <&pinctrl_sai3>;
185	assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
186	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
187	assigned-clock-rates = <24576000>;
188	status = "okay";
189};
190
191/* GPS */
192&uart1 {
193	pinctrl-names = "default";
194	pinctrl-0 = <&pinctrl_uart1>;
195	status = "okay";
196};
197
198/* off-board header */
199&uart3 {
200	pinctrl-names = "default";
201	pinctrl-0 = <&pinctrl_uart3>;
202	status = "okay";
203};
204
205/* RS232 */
206&uart4 {
207	pinctrl-names = "default";
208	pinctrl-0 = <&pinctrl_uart4>;
209	status = "okay";
210};
211
212&usbotg1 {
213	dr_mode = "otg";
214	over-current-active-low;
215	vbus-supply = <&reg_usb_otg1_vbus>;
216	status = "okay";
217};
218
219&usbotg2 {
220	dr_mode = "host";
221	disable-over-current;
222	vbus-supply = <&reg_usb_otg2_vbus>;
223	status = "okay";
224};
225
226/* microSD */
227&usdhc2 {
228	pinctrl-names = "default", "state_100mhz", "state_200mhz";
229	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
230	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
231	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
232	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
233	bus-width = <4>;
234	vmmc-supply = <&reg_3p3v>;
235	status = "okay";
236};
237
238&iomuxc {
239	pinctrl-names = "default";
240	pinctrl-0 = <&pinctrl_hog>;
241
242	pinctrl_hog: hoggrp {
243		fsl,pins = <
244			MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3		0x40000041 /* PLUG_TEST */
245			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6	0x40000041 /* PCI_USBSEL */
246			MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7	0x40000041 /* PCIE_WDIS# */
247			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7	0x40000041 /* DIO0 */
248			MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9	0x40000041 /* DIO1 */
249			MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0	0x40000104 /* RS485_TERM */
250			MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0	0x40000104 /* RS485 */
251			MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2	0x40000104 /* RS485_HALF */
252		>;
253	};
254
255	pinctrl_accel: accelgrp {
256		fsl,pins = <
257			MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5	0x159
258		>;
259	};
260
261	pinctrl_gpio_leds: gpioledgrp {
262		fsl,pins = <
263			MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5	0x19
264			MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4		0x19
265		>;
266	};
267
268	pinctrl_i2c3: i2c3grp {
269		fsl,pins = <
270			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
271			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
272		>;
273	};
274
275	pinctrl_pcie0: pcie0grp {
276		fsl,pins = <
277			MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6	0x41
278		>;
279	};
280
281	pinctrl_pps: ppsgrp {
282		fsl,pins = <
283			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x41
284		>;
285	};
286
287	pinctrl_reg_usb1_en: regusb1grp {
288		fsl,pins = <
289			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x41
290			MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC	0x41
291		>;
292	};
293
294	pinctrl_reg_usb2_en: regusb2grp {
295		fsl,pins = <
296			MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8	0x41
297		>;
298	};
299
300	pinctrl_sai3: sai3grp {
301		fsl,pins = <
302			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
303			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
304			MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
305			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
306			MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0	0xd6
307		>;
308	};
309
310	pinctrl_spi2: spi2grp {
311		fsl,pins = <
312			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0xd6
313			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0xd6
314			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0xd6
315			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0xd6
316		>;
317	};
318
319	pinctrl_uart1: uart1grp {
320		fsl,pins = <
321			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
322			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
323		>;
324	};
325
326	pinctrl_uart3: uart3grp {
327		fsl,pins = <
328			MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX	0x140
329			MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX	0x140
330		>;
331	};
332
333	pinctrl_uart4: uart4grp {
334		fsl,pins = <
335			MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX	0x140
336			MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX	0x140
337		>;
338	};
339
340	pinctrl_usdhc1: usdhc1grp {
341		fsl,pins = <
342			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x190
343			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0
344			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0
345			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0
346			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0
347			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0
348		>;
349	};
350
351	pinctrl_usdhc2: usdhc2grp {
352		fsl,pins = <
353			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
354			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
355			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
356			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
357			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
358			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
359		>;
360	};
361
362	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
363		fsl,pins = <
364			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
365			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
366			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
367			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
368			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
369			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
370		>;
371	};
372
373	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
374		fsl,pins = <
375			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
376			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
377			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
378			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
379			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
380			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
381		>;
382	};
383
384	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
385		fsl,pins = <
386			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12	0x1c4
387			MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B	0x1d0
388			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
389		>;
390	};
391};
392