1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2020 Gateworks Corporation 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/linux-event-codes.h> 10#include <dt-bindings/leds/common.h> 11#include <dt-bindings/phy/phy-imx8-pcie.h> 12 13#include "imx8mm.dtsi" 14 15/ { 16 model = "Gateworks Venice GW7901 i.MX8MM board"; 17 compatible = "gw,imx8mm-gw7901", "fsl,imx8mm"; 18 19 aliases { 20 ethernet0 = &fec1; 21 ethernet1 = &lan1; 22 ethernet2 = &lan2; 23 ethernet3 = &lan3; 24 ethernet4 = &lan4; 25 usb0 = &usbotg1; 26 usb1 = &usbotg2; 27 }; 28 29 chosen { 30 stdout-path = &uart2; 31 }; 32 33 memory@40000000 { 34 device_type = "memory"; 35 reg = <0x0 0x40000000 0 0x80000000>; 36 }; 37 38 gpio-keys { 39 compatible = "gpio-keys"; 40 41 user-pb { 42 label = "user_pb"; 43 gpios = <&gpio 2 GPIO_ACTIVE_LOW>; 44 linux,code = <BTN_0>; 45 }; 46 47 user-pb1x { 48 label = "user_pb1x"; 49 linux,code = <BTN_1>; 50 interrupt-parent = <&gsc>; 51 interrupts = <0>; 52 }; 53 54 key-erased { 55 label = "key_erased"; 56 linux,code = <BTN_2>; 57 interrupt-parent = <&gsc>; 58 interrupts = <1>; 59 }; 60 61 eeprom-wp { 62 label = "eeprom_wp"; 63 linux,code = <BTN_3>; 64 interrupt-parent = <&gsc>; 65 interrupts = <2>; 66 }; 67 68 tamper { 69 label = "tamper"; 70 linux,code = <BTN_4>; 71 interrupt-parent = <&gsc>; 72 interrupts = <5>; 73 }; 74 75 switch-hold { 76 label = "switch_hold"; 77 linux,code = <BTN_5>; 78 interrupt-parent = <&gsc>; 79 interrupts = <7>; 80 }; 81 }; 82 83 led-controller { 84 compatible = "gpio-leds"; 85 86 led-0 { 87 function = LED_FUNCTION_STATUS; 88 color = <LED_COLOR_ID_RED>; 89 label = "led01_red"; 90 gpios = <&leds_gpio 0 GPIO_ACTIVE_HIGH>; 91 default-state = "off"; 92 }; 93 94 led-1 { 95 function = LED_FUNCTION_STATUS; 96 color = <LED_COLOR_ID_GREEN>; 97 label = "led01_grn"; 98 gpios = <&leds_gpio 1 GPIO_ACTIVE_HIGH>; 99 default-state = "off"; 100 }; 101 102 led-2 { 103 function = LED_FUNCTION_STATUS; 104 color = <LED_COLOR_ID_RED>; 105 label = "led02_red"; 106 gpios = <&leds_gpio 2 GPIO_ACTIVE_HIGH>; 107 default-state = "off"; 108 }; 109 110 led-3 { 111 function = LED_FUNCTION_STATUS; 112 color = <LED_COLOR_ID_GREEN>; 113 label = "led02_grn"; 114 gpios = <&leds_gpio 3 GPIO_ACTIVE_HIGH>; 115 default-state = "off"; 116 }; 117 118 led-4 { 119 function = LED_FUNCTION_STATUS; 120 color = <LED_COLOR_ID_RED>; 121 label = "led03_red"; 122 gpios = <&leds_gpio 4 GPIO_ACTIVE_HIGH>; 123 default-state = "off"; 124 }; 125 126 led-5 { 127 function = LED_FUNCTION_STATUS; 128 color = <LED_COLOR_ID_GREEN>; 129 label = "led03_grn"; 130 gpios = <&leds_gpio 5 GPIO_ACTIVE_HIGH>; 131 default-state = "off"; 132 }; 133 134 led-6 { 135 function = LED_FUNCTION_STATUS; 136 color = <LED_COLOR_ID_RED>; 137 label = "led04_red"; 138 gpios = <&leds_gpio 8 GPIO_ACTIVE_HIGH>; 139 default-state = "off"; 140 }; 141 142 led-7 { 143 function = LED_FUNCTION_STATUS; 144 color = <LED_COLOR_ID_GREEN>; 145 label = "led04_grn"; 146 gpios = <&leds_gpio 9 GPIO_ACTIVE_HIGH>; 147 default-state = "off"; 148 }; 149 150 led-8 { 151 function = LED_FUNCTION_STATUS; 152 color = <LED_COLOR_ID_RED>; 153 label = "led05_red"; 154 gpios = <&leds_gpio 10 GPIO_ACTIVE_HIGH>; 155 default-state = "off"; 156 }; 157 158 led-9 { 159 function = LED_FUNCTION_STATUS; 160 color = <LED_COLOR_ID_GREEN>; 161 label = "led05_grn"; 162 gpios = <&leds_gpio 11 GPIO_ACTIVE_HIGH>; 163 default-state = "off"; 164 }; 165 166 led-a { 167 function = LED_FUNCTION_STATUS; 168 color = <LED_COLOR_ID_RED>; 169 label = "led06_red"; 170 gpios = <&leds_gpio 12 GPIO_ACTIVE_HIGH>; 171 default-state = "off"; 172 }; 173 174 led-b { 175 function = LED_FUNCTION_STATUS; 176 color = <LED_COLOR_ID_GREEN>; 177 label = "led06_grn"; 178 gpios = <&leds_gpio 13 GPIO_ACTIVE_HIGH>; 179 default-state = "off"; 180 }; 181 }; 182 183 pcie0_refclk: pcie0-refclk { 184 compatible = "fixed-clock"; 185 #clock-cells = <0>; 186 clock-frequency = <100000000>; 187 }; 188 189 reg_3p3v: regulator-3p3v { 190 compatible = "regulator-fixed"; 191 regulator-name = "3P3V"; 192 regulator-min-microvolt = <3300000>; 193 regulator-max-microvolt = <3300000>; 194 }; 195 196 regulator-ioexp { 197 pinctrl-names = "default"; 198 pinctrl-0 = <&pinctrl_reg_ioexp>; 199 compatible = "regulator-fixed"; 200 regulator-name = "ioexp"; 201 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; 202 enable-active-high; 203 startup-delay-us = <100>; 204 regulator-min-microvolt = <3300000>; 205 regulator-max-microvolt = <3300000>; 206 regulator-always-on; 207 }; 208 209 regulator-isouart { 210 pinctrl-names = "default"; 211 pinctrl-0 = <&pinctrl_reg_isouart>; 212 compatible = "regulator-fixed"; 213 regulator-name = "iso_uart"; 214 gpio = <&gpio1 13 GPIO_ACTIVE_LOW>; 215 startup-delay-us = <100>; 216 regulator-min-microvolt = <3300000>; 217 regulator-max-microvolt = <3300000>; 218 regulator-always-on; 219 }; 220 221 reg_usb2_vbus: regulator-usb2 { 222 pinctrl-names = "default"; 223 pinctrl-0 = <&pinctrl_reg_usb2>; 224 compatible = "regulator-fixed"; 225 regulator-name = "usb_usb2_vbus"; 226 gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; 227 enable-active-high; 228 regulator-min-microvolt = <5000000>; 229 regulator-max-microvolt = <5000000>; 230 }; 231 232 reg_wifi: regulator-wifi { 233 pinctrl-names = "default"; 234 pinctrl-0 = <&pinctrl_reg_wl>; 235 compatible = "regulator-fixed"; 236 regulator-name = "wifi"; 237 gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>; 238 enable-active-high; 239 startup-delay-us = <100>; 240 regulator-min-microvolt = <3300000>; 241 regulator-max-microvolt = <3300000>; 242 }; 243}; 244 245&ddrc { 246 operating-points-v2 = <&ddrc_opp_table>; 247 248 ddrc_opp_table: opp-table { 249 compatible = "operating-points-v2"; 250 251 opp-25M { 252 opp-hz = /bits/ 64 <25000000>; 253 }; 254 255 opp-100M { 256 opp-hz = /bits/ 64 <100000000>; 257 }; 258 259 opp-750M { 260 opp-hz = /bits/ 64 <750000000>; 261 }; 262 }; 263}; 264 265&disp_blk_ctrl { 266 status = "disabled"; 267}; 268 269&ecspi1 { 270 pinctrl-names = "default"; 271 pinctrl-0 = <&pinctrl_spi1>; 272 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 273 status = "okay"; 274 275 flash@0 { 276 compatible = "jedec,spi-nor"; 277 reg = <0>; 278 spi-max-frequency = <40000000>; 279 status = "okay"; 280 }; 281}; 282 283&fec1 { 284 pinctrl-names = "default"; 285 pinctrl-0 = <&pinctrl_fec1>; 286 phy-mode = "rgmii-id"; 287 local-mac-address = [00 00 00 00 00 00]; 288 status = "okay"; 289 290 fixed-link { 291 speed = <1000>; 292 full-duplex; 293 }; 294}; 295 296&gpio1 { 297 gpio-line-names = "uart1_rs422#", "", "", "uart1_rs485#", 298 "", "uart1_rs232#", "dig1_in", "dig1_out", 299 "", "", "", "", "", "", "", "", 300 "", "", "", "", "", "", "", "", 301 "", "", "", "", "", "", "", ""; 302}; 303 304&gpio4 { 305 gpio-line-names = "", "", "", "", 306 "", "", "uart3_rs232#", "uart3_rs422#", 307 "uart3_rs485#", "", "", "", "", "", "", "", 308 "", "", "", "", "", "", "", "", 309 "", "", "", "uart4_rs485#", "", "sim1det#", "sim2det#", ""; 310}; 311 312&gpio5 { 313 gpio-line-names = "", "", "", "dig2_out", "dig2_in", "sim2sel", "", "", 314 "", "", "uart4_rs232#", "", "", "uart4_rs422#", "", "", 315 "", "", "", "", "", "", "", "", 316 "", "", "", "", "", "", "", ""; 317}; 318 319&gpu_2d { 320 status = "disabled"; 321}; 322 323&gpu_3d { 324 status = "disabled"; 325}; 326 327&i2c1 { 328 clock-frequency = <100000>; 329 pinctrl-names = "default"; 330 pinctrl-0 = <&pinctrl_i2c1>; 331 status = "okay"; 332 333 gsc: gsc@20 { 334 compatible = "gw,gsc"; 335 reg = <0x20>; 336 pinctrl-0 = <&pinctrl_gsc>; 337 interrupt-parent = <&gpio4>; 338 interrupts = <16 IRQ_TYPE_EDGE_FALLING>; 339 interrupt-controller; 340 #interrupt-cells = <1>; 341 342 adc { 343 compatible = "gw,gsc-adc"; 344 #address-cells = <1>; 345 #size-cells = <0>; 346 347 channel@6 { 348 gw,mode = <0>; 349 reg = <0x06>; 350 label = "temp"; 351 }; 352 353 channel@8 { 354 gw,mode = <1>; 355 reg = <0x08>; 356 label = "vdd_bat"; 357 }; 358 359 channel@82 { 360 gw,mode = <2>; 361 reg = <0x82>; 362 label = "vin_aux1"; 363 gw,voltage-divider-ohms = <22100 1000>; 364 }; 365 366 channel@84 { 367 gw,mode = <2>; 368 reg = <0x84>; 369 label = "vin_aux2"; 370 gw,voltage-divider-ohms = <22100 1000>; 371 }; 372 373 channel@86 { 374 gw,mode = <2>; 375 reg = <0x86>; 376 label = "vdd_vin"; 377 gw,voltage-divider-ohms = <22100 1000>; 378 }; 379 380 channel@88 { 381 gw,mode = <2>; 382 reg = <0x88>; 383 label = "vdd_3p3"; 384 gw,voltage-divider-ohms = <10000 10000>; 385 }; 386 387 channel@8c { 388 gw,mode = <2>; 389 reg = <0x8c>; 390 label = "vdd_2p5"; 391 gw,voltage-divider-ohms = <10000 10000>; 392 }; 393 394 channel@8e { 395 gw,mode = <2>; 396 reg = <0x8e>; 397 label = "vdd_0p95"; 398 }; 399 400 channel@90 { 401 gw,mode = <2>; 402 reg = <0x90>; 403 label = "vdd_soc"; 404 }; 405 406 channel@92 { 407 gw,mode = <2>; 408 reg = <0x92>; 409 label = "vdd_arm"; 410 }; 411 412 channel@98 { 413 gw,mode = <2>; 414 reg = <0x98>; 415 label = "vdd_1p8"; 416 }; 417 418 channel@9a { 419 gw,mode = <2>; 420 reg = <0x9a>; 421 label = "vdd_1p2"; 422 }; 423 424 channel@9c { 425 gw,mode = <2>; 426 reg = <0x9c>; 427 label = "vdd_dram"; 428 }; 429 430 channel@a2 { 431 gw,mode = <2>; 432 reg = <0xa2>; 433 label = "vdd_gsc"; 434 gw,voltage-divider-ohms = <10000 10000>; 435 }; 436 }; 437 }; 438 439 gpio: gpio@23 { 440 compatible = "nxp,pca9555"; 441 reg = <0x23>; 442 gpio-controller; 443 #gpio-cells = <2>; 444 interrupt-parent = <&gsc>; 445 interrupts = <4>; 446 }; 447 448 eeprom@50 { 449 compatible = "atmel,24c02"; 450 reg = <0x50>; 451 pagesize = <16>; 452 }; 453 454 eeprom@51 { 455 compatible = "atmel,24c02"; 456 reg = <0x51>; 457 pagesize = <16>; 458 }; 459 460 eeprom@52 { 461 compatible = "atmel,24c02"; 462 reg = <0x52>; 463 pagesize = <16>; 464 }; 465 466 eeprom@53 { 467 compatible = "atmel,24c02"; 468 reg = <0x53>; 469 pagesize = <16>; 470 }; 471 472 rtc@68 { 473 compatible = "dallas,ds1672"; 474 reg = <0x68>; 475 }; 476}; 477 478&i2c2 { 479 clock-frequency = <400000>; 480 pinctrl-names = "default"; 481 pinctrl-0 = <&pinctrl_i2c2>; 482 status = "okay"; 483 484 pmic@4b { 485 compatible = "rohm,bd71847"; 486 reg = <0x4b>; 487 pinctrl-names = "default"; 488 pinctrl-0 = <&pinctrl_pmic>; 489 interrupt-parent = <&gpio3>; 490 interrupts = <20 IRQ_TYPE_LEVEL_LOW>; 491 rohm,reset-snvs-powered; 492 #clock-cells = <0>; 493 clocks = <&osc_32k 0>; 494 clock-output-names = "clk-32k-out"; 495 496 regulators { 497 /* vdd_soc: 0.805-0.900V (typ=0.8V) */ 498 BUCK1 { 499 regulator-name = "buck1"; 500 regulator-min-microvolt = <700000>; 501 regulator-max-microvolt = <1300000>; 502 regulator-boot-on; 503 regulator-always-on; 504 regulator-ramp-delay = <1250>; 505 }; 506 507 /* vdd_arm: 0.805-1.0V (typ=0.9V) */ 508 BUCK2 { 509 regulator-name = "buck2"; 510 regulator-min-microvolt = <700000>; 511 regulator-max-microvolt = <1300000>; 512 regulator-boot-on; 513 regulator-always-on; 514 regulator-ramp-delay = <1250>; 515 rohm,dvs-run-voltage = <1000000>; 516 rohm,dvs-idle-voltage = <900000>; 517 }; 518 519 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */ 520 BUCK3 { 521 regulator-name = "buck3"; 522 regulator-min-microvolt = <700000>; 523 regulator-max-microvolt = <1350000>; 524 regulator-boot-on; 525 regulator-always-on; 526 }; 527 528 /* vdd_3p3 */ 529 BUCK4 { 530 regulator-name = "buck4"; 531 regulator-min-microvolt = <3000000>; 532 regulator-max-microvolt = <3300000>; 533 regulator-boot-on; 534 regulator-always-on; 535 }; 536 537 /* vdd_1p8 */ 538 BUCK5 { 539 regulator-name = "buck5"; 540 regulator-min-microvolt = <1605000>; 541 regulator-max-microvolt = <1995000>; 542 regulator-boot-on; 543 regulator-always-on; 544 }; 545 546 /* vdd_dram */ 547 BUCK6 { 548 regulator-name = "buck6"; 549 regulator-min-microvolt = <800000>; 550 regulator-max-microvolt = <1400000>; 551 regulator-boot-on; 552 regulator-always-on; 553 }; 554 555 /* nvcc_snvs_1p8 */ 556 LDO1 { 557 regulator-name = "ldo1"; 558 regulator-min-microvolt = <1600000>; 559 regulator-max-microvolt = <1900000>; 560 regulator-boot-on; 561 regulator-always-on; 562 }; 563 564 /* vdd_snvs_0p8 */ 565 LDO2 { 566 regulator-name = "ldo2"; 567 regulator-min-microvolt = <800000>; 568 regulator-max-microvolt = <900000>; 569 regulator-boot-on; 570 regulator-always-on; 571 }; 572 573 /* vdda_1p8 */ 574 LDO3 { 575 regulator-name = "ldo3"; 576 regulator-min-microvolt = <1800000>; 577 regulator-max-microvolt = <3300000>; 578 regulator-boot-on; 579 regulator-always-on; 580 }; 581 582 LDO4 { 583 regulator-name = "ldo4"; 584 regulator-min-microvolt = <900000>; 585 regulator-max-microvolt = <1800000>; 586 regulator-boot-on; 587 regulator-always-on; 588 }; 589 590 LDO6 { 591 regulator-name = "ldo6"; 592 regulator-min-microvolt = <900000>; 593 regulator-max-microvolt = <1800000>; 594 regulator-boot-on; 595 regulator-always-on; 596 }; 597 }; 598 }; 599}; 600 601&i2c3 { 602 clock-frequency = <400000>; 603 pinctrl-names = "default"; 604 pinctrl-0 = <&pinctrl_i2c3>; 605 status = "okay"; 606 607 leds_gpio: gpio@20 { 608 compatible = "nxp,pca9555"; 609 reg = <0x20>; 610 gpio-controller; 611 #gpio-cells = <2>; 612 }; 613 614 switch: switch@5f { 615 compatible = "microchip,ksz9897"; 616 reg = <0x5f>; 617 pinctrl-0 = <&pinctrl_ksz>; 618 interrupt-parent = <&gpio4>; 619 interrupts = <18 IRQ_TYPE_EDGE_FALLING>; 620 phy-mode = "rgmii-id"; 621 622 ports { 623 #address-cells = <1>; 624 #size-cells = <0>; 625 626 lan1: port@0 { 627 reg = <0>; 628 label = "lan1"; 629 local-mac-address = [00 00 00 00 00 00]; 630 }; 631 632 lan2: port@1 { 633 reg = <1>; 634 label = "lan2"; 635 local-mac-address = [00 00 00 00 00 00]; 636 }; 637 638 lan3: port@2 { 639 reg = <2>; 640 label = "lan3"; 641 local-mac-address = [00 00 00 00 00 00]; 642 }; 643 644 lan4: port@3 { 645 reg = <3>; 646 label = "lan4"; 647 local-mac-address = [00 00 00 00 00 00]; 648 }; 649 650 port@5 { 651 reg = <5>; 652 label = "cpu"; 653 ethernet = <&fec1>; 654 phy-mode = "rgmii-id"; 655 656 fixed-link { 657 speed = <1000>; 658 full-duplex; 659 }; 660 }; 661 }; 662 }; 663 664 crypto@60 { 665 compatible = "atmel,atecc508a"; 666 reg = <0x60>; 667 }; 668}; 669 670&i2c4 { 671 clock-frequency = <400000>; 672 pinctrl-names = "default"; 673 pinctrl-0 = <&pinctrl_i2c4>; 674 status = "okay"; 675}; 676 677&pcie_phy { 678 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 679 fsl,clkreq-unsupported; 680 clocks = <&pcie0_refclk>; 681 status = "okay"; 682}; 683 684&pcie0 { 685 pinctrl-names = "default"; 686 pinctrl-0 = <&pinctrl_pcie0>; 687 reset-gpio = <&gpio5 2 GPIO_ACTIVE_LOW>; 688 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, 689 <&pcie0_refclk>; 690 clock-names = "pcie", "pcie_aux", "pcie_bus"; 691 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, 692 <&clk IMX8MM_CLK_PCIE1_CTRL>; 693 assigned-clock-rates = <10000000>, <250000000>; 694 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, 695 <&clk IMX8MM_SYS_PLL2_250M>; 696 status = "okay"; 697}; 698 699&pgc_gpu { 700 status = "disabled"; 701}; 702 703&pgc_gpumix { 704 status = "disabled"; 705}; 706 707&pgc_mipi { 708 status = "disabled"; 709}; 710 711&uart1 { 712 pinctrl-names = "default"; 713 pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>; 714 rts-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; 715 cts-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; 716 dtr-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; 717 dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; 718 dcd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; 719 status = "okay"; 720}; 721 722/* console */ 723&uart2 { 724 pinctrl-names = "default"; 725 pinctrl-0 = <&pinctrl_uart2>; 726 status = "okay"; 727}; 728 729&uart3 { 730 pinctrl-names = "default"; 731 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>; 732 cts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; 733 rts-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; 734 status = "okay"; 735}; 736 737&uart4 { 738 pinctrl-names = "default"; 739 pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_uart4_gpio>; 740 cts-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; 741 rts-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; 742 status = "okay"; 743}; 744 745&usbotg1 { 746 dr_mode = "host"; 747 disable-over-current; 748 status = "okay"; 749}; 750 751&usbotg2 { 752 dr_mode = "host"; 753 vbus-supply = <®_usb2_vbus>; 754 status = "okay"; 755}; 756 757/* SDIO WiFi */ 758&usdhc1 { 759 pinctrl-names = "default"; 760 pinctrl-0 = <&pinctrl_usdhc1>; 761 bus-width = <4>; 762 non-removable; 763 vmmc-supply = <®_wifi>; 764 status = "okay"; 765}; 766 767/* microSD */ 768&usdhc2 { 769 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 770 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 771 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 772 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 773 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 774 bus-width = <4>; 775 vmmc-supply = <®_3p3v>; 776 status = "okay"; 777}; 778 779/* eMMC */ 780&usdhc3 { 781 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 782 pinctrl-0 = <&pinctrl_usdhc3>; 783 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 784 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 785 bus-width = <8>; 786 non-removable; 787 status = "okay"; 788}; 789 790&wdog1 { 791 pinctrl-names = "default"; 792 pinctrl-0 = <&pinctrl_wdog>; 793 fsl,ext-reset-output; 794 status = "okay"; 795}; 796 797&iomuxc { 798 pinctrl-names = "default"; 799 pinctrl-0 = <&pinctrl_hog>; 800 801 pinctrl_hog: hoggrp { 802 fsl,pins = < 803 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* DIG2_OUT */ 804 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* DIG2_IN */ 805 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* DIG1_IN */ 806 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIG1_OUT */ 807 MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x40000041 /* SIM2DET# */ 808 MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x40000041 /* SIM1DET# */ 809 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* SIM2SEL */ 810 >; 811 }; 812 813 pinctrl_fec1: fec1grp { 814 fsl,pins = < 815 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 816 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 817 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 818 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 819 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 820 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 821 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 822 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 823 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 824 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 825 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 826 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 827 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 828 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 829 MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* IRQ# */ 830 MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* RST# */ 831 >; 832 }; 833 834 pinctrl_gsc: gscgrp { 835 fsl,pins = < 836 MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x159 837 >; 838 }; 839 840 pinctrl_i2c1: i2c1grp { 841 fsl,pins = < 842 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 843 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 844 >; 845 }; 846 847 pinctrl_i2c2: i2c2grp { 848 fsl,pins = < 849 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 850 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 851 >; 852 }; 853 854 pinctrl_i2c3: i2c3grp { 855 fsl,pins = < 856 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 857 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 858 >; 859 }; 860 861 pinctrl_i2c4: i2c4grp { 862 fsl,pins = < 863 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 864 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 865 >; 866 }; 867 868 pinctrl_ksz: kszgrp { 869 fsl,pins = < 870 MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x41 871 MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x41 /* RST# */ 872 >; 873 }; 874 875 pinctrl_pcie0: pciegrp { 876 fsl,pins = < 877 MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x40000041 /* WDIS# */ 878 MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x41 879 >; 880 }; 881 882 pinctrl_pmic: pmicgrp { 883 fsl,pins = < 884 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41 885 >; 886 }; 887 888 pinctrl_reg_isouart: regisouartgrp { 889 fsl,pins = < 890 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 891 >; 892 }; 893 894 pinctrl_reg_ioexp: regioexpgrp { 895 fsl,pins = < 896 MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 897 >; 898 }; 899 900 pinctrl_reg_wl: regwlgrp { 901 fsl,pins = < 902 MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x40000041 903 >; 904 }; 905 906 pinctrl_reg_usb2: regusb1grp { 907 fsl,pins = < 908 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x41 909 MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x140 910 MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x140 911 >; 912 }; 913 914 pinctrl_spi1: spi1grp { 915 fsl,pins = < 916 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 917 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 918 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 919 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140 920 >; 921 }; 922 923 pinctrl_uart1: uart1grp { 924 fsl,pins = < 925 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 926 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 927 MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140 928 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x140 929 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x140 930 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x140 931 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x140 932 >; 933 }; 934 935 pinctrl_uart1_gpio: uart1gpiogrp { 936 fsl,pins = < 937 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000041 /* RS422# */ 938 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x40000041 /* RS485# */ 939 MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x40000041 /* RS232# */ 940 >; 941 }; 942 943 pinctrl_uart2: uart2grp { 944 fsl,pins = < 945 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 946 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 947 >; 948 }; 949 950 pinctrl_uart3: uart3grp { 951 fsl,pins = < 952 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 953 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 954 MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x140 955 MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140 956 >; 957 }; 958 959 pinctrl_uart3_gpio: uart3gpiogrp { 960 fsl,pins = < 961 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000110 /* RS232# */ 962 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000110 /* RS422# */ 963 MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000110 /* RS485# */ 964 >; 965 }; 966 967 pinctrl_uart4: uart4grp { 968 fsl,pins = < 969 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 970 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 971 MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x140 972 MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x140 973 >; 974 }; 975 976 pinctrl_uart4_gpio: uart4gpiogrp { 977 fsl,pins = < 978 979 MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x40000041 /* RS232# */ 980 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000041 /* RS422# */ 981 MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* RS485# */ 982 >; 983 }; 984 985 pinctrl_usdhc1: usdhc1grp { 986 fsl,pins = < 987 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 988 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 989 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 990 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 991 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 992 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 993 >; 994 }; 995 996 pinctrl_usdhc2: usdhc2grp { 997 fsl,pins = < 998 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 999 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 1000 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 1001 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 1002 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 1003 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 1004 >; 1005 }; 1006 1007 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 1008 fsl,pins = < 1009 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 1010 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 1011 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 1012 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 1013 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 1014 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 1015 >; 1016 }; 1017 1018 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 1019 fsl,pins = < 1020 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 1021 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 1022 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 1023 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 1024 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 1025 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 1026 >; 1027 }; 1028 1029 pinctrl_usdhc2_gpio: usdhc2-gpiogrp { 1030 fsl,pins = < 1031 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 1032 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 1033 >; 1034 }; 1035 1036 pinctrl_usdhc3: usdhc3grp { 1037 fsl,pins = < 1038 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 1039 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 1040 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 1041 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 1042 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 1043 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 1044 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 1045 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 1046 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 1047 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 1048 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 1049 >; 1050 }; 1051 1052 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 1053 fsl,pins = < 1054 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 1055 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 1056 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 1057 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 1058 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 1059 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 1060 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 1061 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 1062 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 1063 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 1064 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 1065 >; 1066 }; 1067 1068 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 1069 fsl,pins = < 1070 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 1071 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 1072 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 1073 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 1074 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 1075 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 1076 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 1077 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 1078 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 1079 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 1080 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 1081 >; 1082 }; 1083 1084 pinctrl_wdog: wdoggrp { 1085 fsl,pins = < 1086 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 1087 >; 1088 }; 1089}; 1090 1091&cpu_alert0 { 1092 temperature = <95000>; 1093 hysteresis = <2000>; 1094 type = "passive"; 1095}; 1096 1097&cpu_crit0 { 1098 temperature = <105000>; 1099 hysteresis = <2000>; 1100 type = "critical"; 1101}; 1102