1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2020 Gateworks Corporation
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/linux-event-codes.h>
10#include <dt-bindings/leds/common.h>
11#include <dt-bindings/phy/phy-imx8-pcie.h>
12
13#include "imx8mm.dtsi"
14
15/ {
16	model = "Gateworks Venice GW7901 i.MX8MM board";
17	compatible = "gw,imx8mm-gw7901", "fsl,imx8mm";
18
19	aliases {
20		ethernet0 = &fec1;
21		ethernet1 = &lan1;
22		ethernet2 = &lan2;
23		ethernet3 = &lan3;
24		ethernet4 = &lan4;
25		usb0 = &usbotg1;
26		usb1 = &usbotg2;
27	};
28
29	chosen {
30		stdout-path = &uart2;
31	};
32
33	memory@40000000 {
34		device_type = "memory";
35		reg = <0x0 0x40000000 0 0x80000000>;
36	};
37
38	gpio-keys {
39		compatible = "gpio-keys";
40
41		key-user-pb {
42			label = "user_pb";
43			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
44			linux,code = <BTN_0>;
45		};
46
47		key-user-pb1x {
48			label = "user_pb1x";
49			linux,code = <BTN_1>;
50			interrupt-parent = <&gsc>;
51			interrupts = <0>;
52		};
53
54		key-erased {
55			label = "key_erased";
56			linux,code = <BTN_2>;
57			interrupt-parent = <&gsc>;
58			interrupts = <1>;
59		};
60
61		key-eeprom-wp {
62			label = "eeprom_wp";
63			linux,code = <BTN_3>;
64			interrupt-parent = <&gsc>;
65			interrupts = <2>;
66		};
67
68		key-tamper {
69			label = "tamper";
70			linux,code = <BTN_4>;
71			interrupt-parent = <&gsc>;
72			interrupts = <5>;
73		};
74
75		switch-hold {
76			label = "switch_hold";
77			linux,code = <BTN_5>;
78			interrupt-parent = <&gsc>;
79			interrupts = <7>;
80		};
81	};
82
83	led-controller {
84		compatible = "gpio-leds";
85
86		led-0 {
87			function = LED_FUNCTION_STATUS;
88			color = <LED_COLOR_ID_RED>;
89			label = "led01_red";
90			gpios = <&leds_gpio 0 GPIO_ACTIVE_HIGH>;
91			default-state = "off";
92		};
93
94		led-1 {
95			function = LED_FUNCTION_STATUS;
96			color = <LED_COLOR_ID_GREEN>;
97			label = "led01_grn";
98			gpios = <&leds_gpio 1 GPIO_ACTIVE_HIGH>;
99			default-state = "off";
100		};
101
102		led-2 {
103			function = LED_FUNCTION_STATUS;
104			color = <LED_COLOR_ID_RED>;
105			label = "led02_red";
106			gpios = <&leds_gpio 2 GPIO_ACTIVE_HIGH>;
107			default-state = "off";
108		};
109
110		led-3 {
111			function = LED_FUNCTION_STATUS;
112			color = <LED_COLOR_ID_GREEN>;
113			label = "led02_grn";
114			gpios = <&leds_gpio 3 GPIO_ACTIVE_HIGH>;
115			default-state = "off";
116		};
117
118		led-4 {
119			function = LED_FUNCTION_STATUS;
120			color = <LED_COLOR_ID_RED>;
121			label = "led03_red";
122			gpios = <&leds_gpio 4 GPIO_ACTIVE_HIGH>;
123			default-state = "off";
124		};
125
126		led-5 {
127			function = LED_FUNCTION_STATUS;
128			color = <LED_COLOR_ID_GREEN>;
129			label = "led03_grn";
130			gpios = <&leds_gpio 5 GPIO_ACTIVE_HIGH>;
131			default-state = "off";
132		};
133
134		led-6 {
135			function = LED_FUNCTION_STATUS;
136			color = <LED_COLOR_ID_RED>;
137			label = "led04_red";
138			gpios = <&leds_gpio 8 GPIO_ACTIVE_HIGH>;
139			default-state = "off";
140		};
141
142		led-7 {
143			function = LED_FUNCTION_STATUS;
144			color = <LED_COLOR_ID_GREEN>;
145			label = "led04_grn";
146			gpios = <&leds_gpio 9 GPIO_ACTIVE_HIGH>;
147			default-state = "off";
148		};
149
150		led-8 {
151			function = LED_FUNCTION_STATUS;
152			color = <LED_COLOR_ID_RED>;
153			label = "led05_red";
154			gpios = <&leds_gpio 10 GPIO_ACTIVE_HIGH>;
155			default-state = "off";
156		};
157
158		led-9 {
159			function = LED_FUNCTION_STATUS;
160			color = <LED_COLOR_ID_GREEN>;
161			label = "led05_grn";
162			gpios = <&leds_gpio 11 GPIO_ACTIVE_HIGH>;
163			default-state = "off";
164		};
165
166		led-a {
167			function = LED_FUNCTION_STATUS;
168			color = <LED_COLOR_ID_RED>;
169			label = "led06_red";
170			gpios = <&leds_gpio 12 GPIO_ACTIVE_HIGH>;
171			default-state = "off";
172		};
173
174		led-b {
175			function = LED_FUNCTION_STATUS;
176			color = <LED_COLOR_ID_GREEN>;
177			label = "led06_grn";
178			gpios = <&leds_gpio 13 GPIO_ACTIVE_HIGH>;
179			default-state = "off";
180		};
181	};
182
183	pcie0_refclk: pcie0-refclk {
184		compatible = "fixed-clock";
185		#clock-cells = <0>;
186		clock-frequency = <100000000>;
187	};
188
189	reg_3p3v: regulator-3p3v {
190		compatible = "regulator-fixed";
191		regulator-name = "3P3V";
192		regulator-min-microvolt = <3300000>;
193		regulator-max-microvolt = <3300000>;
194	};
195
196	regulator-ioexp {
197		pinctrl-names = "default";
198		pinctrl-0 = <&pinctrl_reg_ioexp>;
199		compatible = "regulator-fixed";
200		regulator-name = "ioexp";
201		gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
202		enable-active-high;
203		startup-delay-us = <100>;
204		regulator-min-microvolt = <3300000>;
205		regulator-max-microvolt = <3300000>;
206		regulator-always-on;
207	};
208
209	regulator-isouart {
210		pinctrl-names = "default";
211		pinctrl-0 = <&pinctrl_reg_isouart>;
212		compatible = "regulator-fixed";
213		regulator-name = "iso_uart";
214		gpio = <&gpio1 13 GPIO_ACTIVE_LOW>;
215		startup-delay-us = <100>;
216		regulator-min-microvolt = <3300000>;
217		regulator-max-microvolt = <3300000>;
218		regulator-always-on;
219	};
220
221	reg_usb2_vbus: regulator-usb2 {
222		pinctrl-names = "default";
223		pinctrl-0 = <&pinctrl_reg_usb2>;
224		compatible = "regulator-fixed";
225		regulator-name = "usb_usb2_vbus";
226		gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
227		enable-active-high;
228		regulator-min-microvolt = <5000000>;
229		regulator-max-microvolt = <5000000>;
230	};
231
232	reg_wifi: regulator-wifi {
233		pinctrl-names = "default";
234		pinctrl-0 = <&pinctrl_reg_wl>;
235		compatible = "regulator-fixed";
236		regulator-name = "wifi";
237		gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;
238		enable-active-high;
239		startup-delay-us = <100>;
240		regulator-min-microvolt = <3300000>;
241		regulator-max-microvolt = <3300000>;
242	};
243};
244
245&ddrc {
246	operating-points-v2 = <&ddrc_opp_table>;
247
248	ddrc_opp_table: opp-table {
249		compatible = "operating-points-v2";
250
251		opp-25000000 {
252			opp-hz = /bits/ 64 <25000000>;
253		};
254
255		opp-100000000 {
256			opp-hz = /bits/ 64 <100000000>;
257		};
258
259		opp-750000000 {
260			opp-hz = /bits/ 64 <750000000>;
261		};
262	};
263};
264
265&disp_blk_ctrl {
266	status = "disabled";
267};
268
269&ecspi1 {
270	pinctrl-names = "default";
271	pinctrl-0 = <&pinctrl_spi1>;
272	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
273	status = "okay";
274
275	flash@0 {
276		compatible = "jedec,spi-nor";
277		reg = <0>;
278		spi-max-frequency = <40000000>;
279		status = "okay";
280	};
281};
282
283&fec1 {
284	pinctrl-names = "default";
285	pinctrl-0 = <&pinctrl_fec1>;
286	phy-mode = "rgmii-id";
287	local-mac-address = [00 00 00 00 00 00];
288	status = "okay";
289
290	fixed-link {
291		speed = <1000>;
292		full-duplex;
293	};
294};
295
296&gpio1 {
297	gpio-line-names = "uart1_rs422#", "", "", "uart1_rs485#",
298		"", "uart1_rs232#", "dig1_in", "dig1_out",
299		"", "", "", "", "", "", "", "",
300		"", "", "", "", "", "", "", "",
301		"", "", "", "", "", "", "", "";
302};
303
304&gpio4 {
305	gpio-line-names = "", "", "", "",
306		"", "", "uart3_rs232#", "uart3_rs422#",
307		"uart3_rs485#", "", "", "", "", "", "", "",
308		"", "", "", "", "", "", "", "",
309		"", "", "", "uart4_rs485#", "", "sim1det#", "sim2det#", "";
310};
311
312&gpio5 {
313	gpio-line-names = "", "", "", "dig2_out", "dig2_in", "sim2sel", "", "",
314		"", "", "uart4_rs232#", "", "", "uart4_rs422#", "", "",
315		"", "", "", "", "", "", "", "",
316		"", "", "", "", "", "", "", "";
317};
318
319&gpu_2d {
320	status = "disabled";
321};
322
323&gpu_3d {
324	status = "disabled";
325};
326
327&i2c1 {
328	clock-frequency = <100000>;
329	pinctrl-names = "default", "gpio";
330	pinctrl-0 = <&pinctrl_i2c1>;
331	pinctrl-1 = <&pinctrl_i2c1_gpio>;
332	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
333	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
334	status = "okay";
335
336	gsc: gsc@20 {
337		compatible = "gw,gsc";
338		reg = <0x20>;
339		pinctrl-0 = <&pinctrl_gsc>;
340		interrupt-parent = <&gpio4>;
341		interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
342		interrupt-controller;
343		#interrupt-cells = <1>;
344
345		adc {
346			compatible = "gw,gsc-adc";
347			#address-cells = <1>;
348			#size-cells = <0>;
349
350			channel@6 {
351				gw,mode = <0>;
352				reg = <0x06>;
353				label = "temp";
354			};
355
356			channel@8 {
357				gw,mode = <1>;
358				reg = <0x08>;
359				label = "vdd_bat";
360			};
361
362			channel@82 {
363				gw,mode = <2>;
364				reg = <0x82>;
365				label = "vin_aux1";
366				gw,voltage-divider-ohms = <22100 1000>;
367			};
368
369			channel@84 {
370				gw,mode = <2>;
371				reg = <0x84>;
372				label = "vin_aux2";
373				gw,voltage-divider-ohms = <22100 1000>;
374			};
375
376			channel@86 {
377				gw,mode = <2>;
378				reg = <0x86>;
379				label = "vdd_vin";
380				gw,voltage-divider-ohms = <22100 1000>;
381			};
382
383			channel@88 {
384				gw,mode = <2>;
385				reg = <0x88>;
386				label = "vdd_3p3";
387				gw,voltage-divider-ohms = <10000 10000>;
388			};
389
390			channel@8c {
391				gw,mode = <2>;
392				reg = <0x8c>;
393				label = "vdd_2p5";
394				gw,voltage-divider-ohms = <10000 10000>;
395			};
396
397			channel@8e {
398				gw,mode = <2>;
399				reg = <0x8e>;
400				label = "vdd_0p95";
401			};
402
403			channel@90 {
404				gw,mode = <2>;
405				reg = <0x90>;
406				label = "vdd_soc";
407			};
408
409			channel@92 {
410				gw,mode = <2>;
411				reg = <0x92>;
412				label = "vdd_arm";
413			};
414
415			channel@98 {
416				gw,mode = <2>;
417				reg = <0x98>;
418				label = "vdd_1p8";
419			};
420
421			channel@9a {
422				gw,mode = <2>;
423				reg = <0x9a>;
424				label = "vdd_1p2";
425			};
426
427			channel@9c {
428				gw,mode = <2>;
429				reg = <0x9c>;
430				label = "vdd_dram";
431			};
432
433			channel@a2 {
434				gw,mode = <2>;
435				reg = <0xa2>;
436				label = "vdd_gsc";
437				gw,voltage-divider-ohms = <10000 10000>;
438			};
439		};
440	};
441
442	gpio: gpio@23 {
443		compatible = "nxp,pca9555";
444		reg = <0x23>;
445		gpio-controller;
446		#gpio-cells = <2>;
447		interrupt-parent = <&gsc>;
448		interrupts = <4>;
449	};
450
451	eeprom@50 {
452		compatible = "atmel,24c02";
453		reg = <0x50>;
454		pagesize = <16>;
455	};
456
457	eeprom@51 {
458		compatible = "atmel,24c02";
459		reg = <0x51>;
460		pagesize = <16>;
461	};
462
463	eeprom@52 {
464		compatible = "atmel,24c02";
465		reg = <0x52>;
466		pagesize = <16>;
467	};
468
469	eeprom@53 {
470		compatible = "atmel,24c02";
471		reg = <0x53>;
472		pagesize = <16>;
473	};
474
475	rtc@68 {
476		compatible = "dallas,ds1672";
477		reg = <0x68>;
478	};
479};
480
481&i2c2 {
482	clock-frequency = <400000>;
483	pinctrl-names = "default", "gpio";
484	pinctrl-0 = <&pinctrl_i2c2>;
485	pinctrl-1 = <&pinctrl_i2c2_gpio>;
486	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
487	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
488	status = "okay";
489
490	pmic@4b {
491		compatible = "rohm,bd71847";
492		reg = <0x4b>;
493		pinctrl-names = "default";
494		pinctrl-0 = <&pinctrl_pmic>;
495		interrupt-parent = <&gpio3>;
496		interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
497		rohm,reset-snvs-powered;
498		#clock-cells = <0>;
499		clocks = <&osc_32k 0>;
500		clock-output-names = "clk-32k-out";
501
502		regulators {
503			/* vdd_soc: 0.805-0.900V (typ=0.8V) */
504			BUCK1 {
505				regulator-name = "buck1";
506				regulator-min-microvolt = <700000>;
507				regulator-max-microvolt = <1300000>;
508				regulator-boot-on;
509				regulator-always-on;
510				regulator-ramp-delay = <1250>;
511			};
512
513			/* vdd_arm: 0.805-1.0V (typ=0.9V) */
514			BUCK2 {
515				regulator-name = "buck2";
516				regulator-min-microvolt = <700000>;
517				regulator-max-microvolt = <1300000>;
518				regulator-boot-on;
519				regulator-always-on;
520				regulator-ramp-delay = <1250>;
521				rohm,dvs-run-voltage = <1000000>;
522				rohm,dvs-idle-voltage = <900000>;
523			};
524
525			/* vdd_0p9: 0.805-1.0V (typ=0.9V) */
526			BUCK3 {
527				regulator-name = "buck3";
528				regulator-min-microvolt = <700000>;
529				regulator-max-microvolt = <1350000>;
530				regulator-boot-on;
531				regulator-always-on;
532			};
533
534			/* vdd_3p3 */
535			BUCK4 {
536				regulator-name = "buck4";
537				regulator-min-microvolt = <3000000>;
538				regulator-max-microvolt = <3300000>;
539				regulator-boot-on;
540				regulator-always-on;
541			};
542
543			/* vdd_1p8 */
544			BUCK5 {
545				regulator-name = "buck5";
546				regulator-min-microvolt = <1605000>;
547				regulator-max-microvolt = <1995000>;
548				regulator-boot-on;
549				regulator-always-on;
550			};
551
552			/* vdd_dram */
553			BUCK6 {
554				regulator-name = "buck6";
555				regulator-min-microvolt = <800000>;
556				regulator-max-microvolt = <1400000>;
557				regulator-boot-on;
558				regulator-always-on;
559			};
560
561			/* nvcc_snvs_1p8 */
562			LDO1 {
563				regulator-name = "ldo1";
564				regulator-min-microvolt = <1600000>;
565				regulator-max-microvolt = <1900000>;
566				regulator-boot-on;
567				regulator-always-on;
568			};
569
570			/* vdd_snvs_0p8 */
571			LDO2 {
572				regulator-name = "ldo2";
573				regulator-min-microvolt = <800000>;
574				regulator-max-microvolt = <900000>;
575				regulator-boot-on;
576				regulator-always-on;
577			};
578
579			/* vdda_1p8 */
580			LDO3 {
581				regulator-name = "ldo3";
582				regulator-min-microvolt = <1800000>;
583				regulator-max-microvolt = <3300000>;
584				regulator-boot-on;
585				regulator-always-on;
586			};
587
588			LDO4 {
589				regulator-name = "ldo4";
590				regulator-min-microvolt = <900000>;
591				regulator-max-microvolt = <1800000>;
592				regulator-boot-on;
593				regulator-always-on;
594			};
595
596			LDO6 {
597				regulator-name = "ldo6";
598				regulator-min-microvolt = <900000>;
599				regulator-max-microvolt = <1800000>;
600				regulator-boot-on;
601				regulator-always-on;
602			};
603		};
604	};
605};
606
607&i2c3 {
608	clock-frequency = <400000>;
609	pinctrl-names = "default", "gpio";
610	pinctrl-0 = <&pinctrl_i2c3>;
611	pinctrl-1 = <&pinctrl_i2c3_gpio>;
612	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
613	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
614	status = "okay";
615
616	leds_gpio: gpio@20 {
617		compatible = "nxp,pca9555";
618		reg = <0x20>;
619		gpio-controller;
620		#gpio-cells = <2>;
621	};
622
623	switch: switch@5f {
624		compatible = "microchip,ksz9897";
625		reg = <0x5f>;
626		pinctrl-0 = <&pinctrl_ksz>;
627		interrupt-parent = <&gpio4>;
628		interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
629		phy-mode = "rgmii-id";
630
631		ports {
632			#address-cells = <1>;
633			#size-cells = <0>;
634
635			lan1: port@0 {
636				reg = <0>;
637				label = "lan1";
638				phy-mode = "internal";
639				local-mac-address = [00 00 00 00 00 00];
640			};
641
642			lan2: port@1 {
643				reg = <1>;
644				label = "lan2";
645				phy-mode = "internal";
646				local-mac-address = [00 00 00 00 00 00];
647			};
648
649			lan3: port@2 {
650				reg = <2>;
651				label = "lan3";
652				phy-mode = "internal";
653				local-mac-address = [00 00 00 00 00 00];
654			};
655
656			lan4: port@3 {
657				reg = <3>;
658				label = "lan4";
659				phy-mode = "internal";
660				local-mac-address = [00 00 00 00 00 00];
661			};
662
663			port@5 {
664				reg = <5>;
665				label = "cpu";
666				ethernet = <&fec1>;
667				phy-mode = "rgmii-id";
668
669				fixed-link {
670					speed = <1000>;
671					full-duplex;
672				};
673			};
674		};
675	};
676
677	crypto@60 {
678		compatible = "atmel,atecc508a";
679		reg = <0x60>;
680	};
681};
682
683&i2c4 {
684	clock-frequency = <400000>;
685	pinctrl-names = "default", "gpio";
686	pinctrl-0 = <&pinctrl_i2c4>;
687	pinctrl-1 = <&pinctrl_i2c4_gpio>;
688	scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
689	sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
690	status = "okay";
691};
692
693&pcie_phy {
694	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
695	fsl,clkreq-unsupported;
696	clocks = <&pcie0_refclk>;
697	clock-names = "ref";
698	status = "okay";
699};
700
701&pcie0 {
702	pinctrl-names = "default";
703	pinctrl-0 = <&pinctrl_pcie0>;
704	reset-gpio = <&gpio5 2 GPIO_ACTIVE_LOW>;
705	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
706		 <&clk IMX8MM_CLK_PCIE1_AUX>;
707	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
708			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
709	assigned-clock-rates = <10000000>, <250000000>;
710	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
711				 <&clk IMX8MM_SYS_PLL2_250M>;
712	status = "okay";
713};
714
715&pgc_gpu {
716	status = "disabled";
717};
718
719&pgc_gpumix {
720	status = "disabled";
721};
722
723&pgc_mipi {
724	status = "disabled";
725};
726
727&uart1 {
728	pinctrl-names = "default";
729	pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
730	rts-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
731	cts-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
732	dtr-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
733	dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
734	dcd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
735	status = "okay";
736};
737
738/* console */
739&uart2 {
740	pinctrl-names = "default";
741	pinctrl-0 = <&pinctrl_uart2>;
742	status = "okay";
743};
744
745&uart3 {
746	pinctrl-names = "default";
747	pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
748	cts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
749	rts-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
750	status = "okay";
751};
752
753&uart4 {
754	pinctrl-names = "default";
755	pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_uart4_gpio>;
756	cts-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
757	rts-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
758	status = "okay";
759};
760
761&usbotg1 {
762	dr_mode = "host";
763	disable-over-current;
764	status = "okay";
765};
766
767&usbotg2 {
768	dr_mode = "host";
769	vbus-supply = <&reg_usb2_vbus>;
770	over-current-active-low;
771	status = "okay";
772};
773
774/* SDIO WiFi */
775&usdhc1 {
776	pinctrl-names = "default";
777	pinctrl-0 = <&pinctrl_usdhc1>;
778	bus-width = <4>;
779	non-removable;
780	vmmc-supply = <&reg_wifi>;
781	status = "okay";
782};
783
784/* microSD */
785&usdhc2 {
786	pinctrl-names = "default", "state_100mhz", "state_200mhz";
787	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
788	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
789	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
790	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
791	bus-width = <4>;
792	vmmc-supply = <&reg_3p3v>;
793	status = "okay";
794};
795
796/* eMMC */
797&usdhc3 {
798	pinctrl-names = "default", "state_100mhz", "state_200mhz";
799	pinctrl-0 = <&pinctrl_usdhc3>;
800	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
801	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
802	bus-width = <8>;
803	non-removable;
804	status = "okay";
805};
806
807&wdog1 {
808	pinctrl-names = "default";
809	pinctrl-0 = <&pinctrl_wdog>;
810	fsl,ext-reset-output;
811	status = "okay";
812};
813
814&iomuxc {
815	pinctrl-names = "default";
816	pinctrl-0 = <&pinctrl_hog>;
817
818	pinctrl_hog: hoggrp {
819		fsl,pins = <
820			MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3		0x40000041 /* DIG2_OUT */
821			MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4		0x40000041 /* DIG2_IN */
822			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6	0x40000041 /* DIG1_IN */
823			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7	0x40000041 /* DIG1_OUT */
824			MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30	0x40000041 /* SIM2DET# */
825			MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29	0x40000041 /* SIM1DET# */
826			MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5	0x40000041 /* SIM2SEL */
827		>;
828	};
829
830	pinctrl_fec1: fec1grp {
831		fsl,pins = <
832			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
833			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
834			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
835			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
836			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
837			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
838			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
839			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
840			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
841			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
842			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
843			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
844			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
845			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
846			MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18		0x19 /* IRQ# */
847			MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19		0x19 /* RST# */
848		>;
849	};
850
851	pinctrl_gsc: gscgrp {
852		fsl,pins = <
853			MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16	0x159
854		>;
855	};
856
857	pinctrl_i2c1: i2c1grp {
858		fsl,pins = <
859			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
860			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
861		>;
862	};
863
864	pinctrl_i2c1_gpio: i2c1gpiogrp {
865		fsl,pins = <
866			MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14	0x400001c3
867			MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15	0x400001c3
868		>;
869	};
870
871	pinctrl_i2c2: i2c2grp {
872		fsl,pins = <
873			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
874			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
875		>;
876	};
877
878	pinctrl_i2c2_gpio: i2c2gpiogrp {
879		fsl,pins = <
880			MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16	0x400001c3
881			MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17	0x400001c3
882		>;
883	};
884
885	pinctrl_i2c3: i2c3grp {
886		fsl,pins = <
887			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
888			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
889		>;
890	};
891
892	pinctrl_i2c3_gpio: i2c3gpiogrp {
893		fsl,pins = <
894			MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18	0x400001c3
895			MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19	0x400001c3
896		>;
897	};
898
899	pinctrl_i2c4: i2c4grp {
900		fsl,pins = <
901			MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL		0x400001c3
902			MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA		0x400001c3
903		>;
904	};
905
906	pinctrl_i2c4_gpio: i2c4gpiogrp {
907		fsl,pins = <
908			MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20	0x400001c3
909			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21	0x400001c3
910		>;
911	};
912
913	pinctrl_ksz: kszgrp {
914		fsl,pins = <
915			MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18	0x41
916			MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19	0x41 /* RST# */
917		>;
918	};
919
920	pinctrl_pcie0: pciegrp {
921		fsl,pins = <
922			MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31	0x40000041 /* WDIS# */
923			MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2	0x41
924		>;
925	};
926
927	pinctrl_pmic: pmicgrp {
928		fsl,pins = <
929			MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20	0x41
930		>;
931	};
932
933	pinctrl_reg_isouart: regisouartgrp {
934		fsl,pins = <
935			MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13	0x40000041
936		>;
937	};
938
939	pinctrl_reg_ioexp: regioexpgrp {
940		fsl,pins = <
941			MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21	0x40000041
942		>;
943	};
944
945	pinctrl_reg_wl: regwlgrp {
946		fsl,pins = <
947			MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25	0x40000041
948		>;
949	};
950
951	pinctrl_reg_usb2: regusb1grp {
952		fsl,pins = <
953			MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2	0x41
954			MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17	0x140
955			MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC	0x140
956		>;
957	};
958
959	pinctrl_spi1: spi1grp {
960		fsl,pins = <
961			MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK	0x82
962			MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI	0x82
963			MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO	0x82
964			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9	0x140
965		>;
966	};
967
968	pinctrl_uart1: uart1grp {
969		fsl,pins = <
970			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
971			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
972			MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1	0x140
973			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10	0x140
974			MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11	0x140
975			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x140
976			MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14	0x140
977		>;
978	};
979
980	pinctrl_uart1_gpio: uart1gpiogrp {
981		fsl,pins = <
982			MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0	0x40000041 /* RS422# */
983			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x40000041 /* RS485# */
984			MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5	0x40000041 /* RS232# */
985		>;
986	};
987
988	pinctrl_uart2: uart2grp {
989		fsl,pins = <
990			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
991			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
992		>;
993	};
994
995	pinctrl_uart3: uart3grp {
996		fsl,pins = <
997			MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX	0x140
998			MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX	0x140
999			MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9	0x140
1000			MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10	0x140
1001		>;
1002	};
1003
1004	pinctrl_uart3_gpio: uart3gpiogrp {
1005		fsl,pins = <
1006			MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6	0x40000110 /* RS232# */
1007			MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7	0x40000110 /* RS422# */
1008			MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8	0x40000110 /* RS485# */
1009		>;
1010	};
1011
1012	pinctrl_uart4: uart4grp {
1013		fsl,pins = <
1014			MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX	0x140
1015			MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX	0x140
1016			MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11	0x140
1017			MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12	0x140
1018		>;
1019	};
1020
1021	pinctrl_uart4_gpio: uart4gpiogrp {
1022		fsl,pins = <
1023
1024			MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10	0x40000041 /* RS232# */
1025			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0x40000041 /* RS422# */
1026			MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27	0x40000041 /* RS485# */
1027		>;
1028	};
1029
1030	pinctrl_usdhc1: usdhc1grp {
1031		fsl,pins = <
1032			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x190
1033			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0
1034			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0
1035			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0
1036			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0
1037			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0
1038		>;
1039	};
1040
1041	pinctrl_usdhc2: usdhc2grp {
1042		fsl,pins = <
1043			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
1044			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
1045			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
1046			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
1047			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
1048			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
1049		>;
1050	};
1051
1052	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
1053		fsl,pins = <
1054			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
1055			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
1056			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
1057			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
1058			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
1059			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
1060		>;
1061	};
1062
1063	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
1064		fsl,pins = <
1065			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
1066			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
1067			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
1068			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
1069			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
1070			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
1071		>;
1072	};
1073
1074	pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
1075		fsl,pins = <
1076			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12	0x1c4
1077			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
1078		>;
1079	};
1080
1081	pinctrl_usdhc3: usdhc3grp {
1082		fsl,pins = <
1083			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x190
1084			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d0
1085			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d0
1086			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d0
1087			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d0
1088			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d0
1089			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d0
1090			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d0
1091			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d0
1092			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d0
1093			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x190
1094		>;
1095	};
1096
1097	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1098		fsl,pins = <
1099			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x194
1100			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d4
1101			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4
1102			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4
1103			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4
1104			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4
1105			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d4
1106			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4
1107			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4
1108			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d4
1109			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x194
1110		>;
1111	};
1112
1113	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1114		fsl,pins = <
1115			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x196
1116			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d6
1117			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d6
1118			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d6
1119			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d6
1120			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d6
1121			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d6
1122			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d6
1123			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d6
1124			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d6
1125			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x196
1126		>;
1127	};
1128
1129	pinctrl_wdog: wdoggrp {
1130		fsl,pins = <
1131			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
1132		>;
1133	};
1134};
1135